Samsung S5PC110, Manual

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S5PC110_UM 4 POWER MANAGEMENT
4-35
4.9.2.1 Watchdog Reset
Watchdog reset is asserted when software fails to prevent the watchdog timer from timing out. In watchdog reset
all units in S5PC110 (except some blocks listed in
Table 4-10
) are reset to their predefined reset states. The
behavior after Watchdog reset is asserted, is the same as Hardware reset case. (Refer to
4.9 "Reset Control
")
During the watchdog reset, the following actions occur:
•
All units (except some blocks listed in
Table 4-10
) go into their pre-defined reset state.
•
All pins get their reset state.
•
The XnRSTOUT pin is asserted during watchdog reset.
Watchdog reset can be activated in NORMAL and IDLE (DEEP-IDLE) mode because watchdog timer can expire
with clock.
Watchdog reset is asserted when watchdog timer and reset are enabled (WTCON[5] = 1, WTCON[0]=1) and
watchdog timer is expired.
Watchdog reset is asserted then, the following sequence occurs:
1. WDT generate time-out signal.
2. SYSCON invokes reset signals and initialize internal IPs.
3. The reset including nRSTOUT will be asserted until the reset counter, RST_STABLE, is expired.
4.9.2.2 Software Reset
Software reset is asserted when CPU write “1” to SWRESET register in NORMAL mode.
During the software reset, the following actions occur:
•
All units (except some blocks listed in
Table 4-10
) go into their pre-defined reset state.
•
All pins get their reset state.
•
The XnRSTOUT pin is asserted during software reset.
When Software reset is asserted the following sequence occurs.
1. SYSCON requests bus controller to finish current transactions.
2. Bus controller send acknowledge to SYSCON after completed bus transactions.
3. SYSCON request memory controller to enter into self refresh mode.
4. SYSCON wait for self refresh acknowledge from memory controller.
5. Internal reset signals and XnRSTOUT are asserted and reset counter is activated.
6. Reset counter is expired, then internal reset signals and XnRSTOUT are deasserted.