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S5PC110_UM
1 DRAM CONTROLLER
1-39
1.4.1.10 AC Timing Register for Auto Refresh of memory (TimingAref, R/W, Address = 0xF000_0030,
0xF140_0030)
TIMINGAREF
Bit
Description
R/W
Initial
State
Reserved [31:16]
Should
be
zero
0x0
t_refi
[15:0]
Average Periodic Refresh Interval
Should be minimum memory tREFI (all bank) < t_refi * T(mclk),
For example, for the all bank refresh period of 7.8us, and an
mclk frequency of 133MHz, the following value should be
programmed :
7.8 us * 133 MHz = 1038
R/W
0x40E
1.4.1.11 AC Timing Register for the Row of memory (TimingRow, R/W, Address = 0xF000_0034,
0xF140_0034)
TIMINGROW
Bit
Description
R/W
Initial
State
t_rfc
[31:24]
Auto refresh to Active / Auto refresh command period, in
cycles
t_rfc * T(mclk) should be greater than or equal to the minimum
value of memory tRFC.
R/W
0xF
t_rrd
[23:20]
Active bank A to Active bank B delay, in cycles
t_rrd * T(mclk) should be greater than or equal to the minimum
value of memory tRRD.
R/W
0x2
t_rp
[19:16]
Precharge command period, in cycles
t_rp * T(mclk) should be greater than or equal to the minimum
value of memory tRP.
R/W
0x3
t_rcd
[15:12]
Active to Read or Write delay, in cycles
t_rcd * T(mclk) should be greater than or equal to the minimum
value of memory tRCD
R/W
0x3
t_rc
[11:6]
Active to Active period, in cycles
t_rc * T(mclk) should be greater than or equal to the minimum
value of memory tRC.
R/W
0xA
t_ras
[5:0]
Active to Precharge command period, in cycles
t_ras * T(mclk) should be greater than or equal to the minimum
value of memory tRAS.
R/W
0x6
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...