S5PC110_UM
2 1BCAMERA INTERFACE
2-27
Register
Address
R/W
Description
Reset Value
CICPTSEQ2 0xFB40_00C4
R/W
Specifies sequence-related capture.
0xFFFF_FFFF
CITHOLD2 0xFB40_00C8
R/W Specifies QoS threshold.
0x0000_0000
CIIMGEFF2 0xFB40_00D0
R/W
Specifies related image effects.
0x0010_0080
CIIYSA02 0xFB40_00D4
R/W
Specifies Y frame start address for Input DMA.
0x0000_0000
CIICBSA02 0xFB40_00D8
R/W
Specifies
Cb
frame start address for Input DMA.
0x0000_0000
CIICRSA02
0xFB40_00DC R/W Specifies Cr frame start address for Input DMA.
0x0000_0000
CIILINESKIP_Y2 0xFB40_00EC R/W Specifies input DMA Y line skip.
0x0000_0000
CIILINESKIP_Cb2 0xFB40_00F0 R/W Specifies input DMA Cb line skip.
0x0000_0000
CIILINESKIP_Cr2 0xFB40_00F4 R/W Specifies input DMA Cr line skip. 0x0000_0000
CIREAL_ISIZE2 0xFB40_00F8 R/W Specifies real input DMA image size.
0x0000_0000
MSCTRL2 0xFB40_00FC
R/W
Specifies input DMA control register.
0x0400_0000
CIIYSA12
0xFB40_0144
R/W Specifies Y frame start address 1 for Input DMA.
0x0000_0000
CIICBSA12 0xFB40_0148
R/W
Specifies
Cb
frame
start address 1 for Input DMA.
0x0000_0000
CIICRSA12
0xFB40_014C
R/W Specifies Cr frame start address 1 for Input DMA.
0x0000_0000
CIOYOFF2 0xFB40_0168
R/W
Specifies output DMA Y offset.
0x0000_0000
CIOCBOFF2 0xFB40_016C
R/W
Specifies output DMA Cb offset.
0x0000_0000
CIOCROFF2 0xFB40_0170
R/W
Specifies output DMA Cr offset.
0x0000_0000
CIIYOFF2
0xFB40_0174
R/W Specifies input DMA Y offset.
0x0000_0000
CIICBOFF2
0xFB40_0178
R/W Specifies input DMA Cb offset.
0x0000_0000
CIICROFF2
0xFB40_017C
R/W Specifies input DMA Cr offset.
0x0000_0000
ORGISIZE2 0xFB40_0180
R/W
Specifies input DMA original image size.
0x0000_0000
ORGOSIZE2 0xFB40_0184
R/W
Specifies
output DMA original image size.
0x0000_0000
CIEXTEN2 0xFB40_0188
R/W
Specifies
real output DMA image size.
0x0000_0000
CIDMAPARAM2 0xFB40_018C R/W Specifies DMA parameter register.
0x0000_0000
CSIIMGFMT2 0xFB40_0194
R/W
Specifies
MIPI CSI image format register.
0x0000_001E
CMISC2 0xFB40_0198
R/W
Specifies miscellaneous control
0x0000_0000
CIKEY2 0xFB40_019C
R/W
Specifies key detect register. 0x0000_0000
NOTE:
The last ‘L’ column means that SFR can change at vsync edge during camera capture. (O: possible change, X:
impossible change). Also, ‘M’ column means that SFRs have relationship capturing result while using input DMA path.
(O: relationship, X: no relationship).
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...