Samsung S5PC110, Manual

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S5PC110_UM 2 IIC-BUS INTERFACE
2-1
2
IIC-BUS INTERFACE
2.1 OVERVIEW OF IIC-BUS INTERFACE
The S5PC110 RISC microprocessor supports four multi-master I
2
C bus serial interfaces. To carry information
between bus masters and peripheral devices connected to the I
2
C bus, a dedicated Serial Data Line (SDA) and
an Serial Clock Line (SCL) is used. Both SDA and SCL lines are bi-directional.
In multi-master I
2
C-bus mode, multiple S5PC110 RISC microprocessors receive or transmit serial data to or from
slave devices. The master S5PC110 initiates and terminates a data transfer over the I
2
C bus. The I
2
C bus in the
S5PC110 uses a standard bus arbitration procedure.
To control multi-master I
2
C-bus operations, values must be written to the following registers:
•
Multi-master I
2
C-bus control register- I2CCON
•
Multi-master I
2
C-bus control/status register- I2CSTAT
•
Multi-master I
2
C-bus Tx/Rx data shift register- I2CDS
•
Multi-master I
2
C-bus address register- I2CADD
If the I
2
C-bus is free, both SDA and SCL lines should be both at High level. A High-to-Low transition of SDA
initiates a Start condition. A Low-to-High transition of SDA initiates a Stop condition while SCL remains steady at
High Level.
The master device always generates Start and Stop conditions. First 7-bit address value in the data byte that is
transferred via SDA line after the Start condition has been initiated, can determine the slave device which the bus
master device has selected. The 8th bit determines the direction of the transfer (read or write).
Every data byte put onto the SDA line should be eight bits in total. There is no limit to send or receive bytes during
the bus transfer operation. Data is always sent from most-significant bit (MSB) first, and every byte should be
immediately followed by acknowledge (ACK) bit.