Samsung S5PC110, Manual

Page: 2021 / 2426

S5PC110_UM 1 ELECTRICAL DATA
1-14
Table 1-9 OneNAND Bus Timing Constants
(VDDINT = 1.1V
±
5%, TA = -25 to 85
°
C, VDDm0 = 1.7V - 1.9V)
Parameter Symbol Minimum Maximum Unit
OneNAND SMCLK cycle
t
CLK
12 - ns
OneNAND Clock High time
t
CLKH
5 - ns
OneNAND Clock Low time
t
CLKL
5 - ns
OneNAND CSn Setup time to SMCLK
t
CES
4.5 - ns
OneNAND Initial Access time
t
IAA
- 70 ns
OneNAND Burst Access time valid SMCLK to Output delay
t
BA
- 9 ns
OneNAND Data Hold time from next clock cycle
t
BDH
2 - ns
OneNAND Output Enable to Data
t
OE
- 20 ns
OneNAND CSn Disable to Output High Z
t
CEZ
- 20 ns
OneNAND OEn Disable to Output High Z
t
OEZ
- 15 ns
OneNAND Address Setup time to SMCLK
t
ACS
4 - ns
OneNAND Address Hold time to SMCLK
t
ACH
6 - ns
OneNAND ADRVALID Setup time to SMCLK
t
AVDS
4 - ns
OneNAND ADRVALID Hold time to SMCLK
t
AVDH
6 - ns
OneNAND Write Data Setup time to SMCLK
t
WDS
4 - ns
OneNAND Write Data Hold time to SMCLK
t
WDH
2 - ns
OneNAND WEn Setup time to SMCLK
t
WES
4 - ns
OneNAND WEn Hold time to SMCLK
t
WEH
6 - ns
OneNAND ADRVALID high to OEn low
t
AVDO
0 - ns
OneNAND Access time from CSn low
t
CE
- 76 ns
OneNAND Asynchronous Access time from ADRVALID low
t
AA
- 76 ns
OneNAND Asynchronous Access time from address valid
t
ACC
- 76 ns
OneNAND Read Cycle time
t
RC
76 - ns
OneNAND ADRVALID low pulse width
t
AVDP
12 - ns
OneNAND Address Setup to rising edge of ADRVALID
t
AAVDS
5 - ns
OneNAND Address Hold to rising edge of ADRVALID
t
AAVDH
7 - ns
OneNAND CSn Setup to ADRVALID falling edge
t
CA
0 - ns
OneNAND WEn Disable to ADRVALID enable
t
WEA
15 - ns
OneNAND Address to OEn low
t
ASO
10 - ns
OneNAND WEn Cycle time
t
WC
70 - ns
OneNAND Data Setup time
t
DS
30 - ns