Samsung S5PC110, Manual

Page: 1310 / 2426

S5PC110_UM 2 1BCAMERA INTERFACE
2-63
2.8.2.11 Input DMA Y0 Start Register (CIIYSA0n)
•
CIIYSA0, R/W, Address = 0xFB20_00D4
•
CIIYSA1, R/W, Address = 0xFB30_00D4
•
CIIYSA2, R/W, Address = 0xFB40_00D4
CIIYSA0n Bit Description Initial State
CIIYSA0 [31:0] Input format: YCbCr 2/3 plane → Y frame start address
Input format: YCbCr 1 plane → YCbCr frame start address
Input format: RGB → RGB frame start address
Note: In tile mode, this value should be aligned 4Kbytes. That is to
say, CIOYSA1[11:0] shoule be 0x000.
(ML=OX)
0
2.8.2.12 Input DMA Cb0 Start Register (CIICBSA0n)
•
CIICBSA00, R/W, Address = 0xFB20_00D8
•
CIICBSA01, R/W, Address = 0xFB30_00D8
•
CIICBSA02, R/W, Address = 0xFB40_00D8
CIICBSA0n Bit Description Initial State
CIICBSA0 [31:0] Input format: YCbCr 3 plane → Cb frame start address
Input format: YCbCr 2 plane → CbCr frame start address
Note: In tile mode, this value should be aligned 4Kbytes. That is to
say, CIOYSA1[11:0] shoule be 0x000.
(ML=OX)
0
2.8.2.13 Input DMA Cr0 Start Register (CIICRSA0n)
•
CIICRSA00, R/W, Address = 0xFB20_00DC
•
CIICRSA01, R/W, Address = 0xFB30_00DC
•
CIICRSA02, R/W, Address = 0xFB40_00DC
CIICRSA0n Bit Description Initial State
CIICRSA0 [31:0] Input format: YCbCr 3 plane → Cr frame start address
Note: In tile mode, this value should be aligned 4Kbytes.
That is to say, CIOYSA1[11:0] shoule be 0x000.
(ML=OX)
0