Samsung S5PC110, Manual

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S5PC110_UM 3 IIS-BUS INTERFACE
3-4
3.4.2 DMA TRANSFER
In the DMA transfer mode, use external DMA controller to access the transmitter or receiver FIFO. The transmitter
or receiver FIFO state activates the DMA service request internally. The FTXEMPT, FRXEMPT, FTXFULL, and
FRXFULL bits of I2SCON register represent the transmitter or receiver FIFO data state. Especially, FTXEMPT
and FRXFULL bit are the ready flag for DMA service request; the transmit DMA service request is activated when
TXFIFO is not empty and the receiver DMA service request is activated when RXFIFO is not full.
The DMA transfer uses only handshaking method for single data. Note that during DMA acknowledge activation;
the data read or write operation should be performed.
* Reference: DMA request point
• TX mode: (FIFO is not full) & (TXDMACTIVE is active)
• RX mode: (FIFO is not empty) & (RXDMACTIVE is active)
3.4.3 AUDIO SERIAL DATA FORMAT
3.4.3.1 IIS-bus Format
The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO, left/right channel select
clock I2SLRCLK, and serial bit clock I2SSCLK; master generates I2SLRCLK and I2SSCLK.
Serial data is transmitted in 2's complement with the MSB first with a fixed position, whereas the position of the
LSB depends on the word length. The transmitter sends the MSB of the next word at one clock period after the
I2SLRCLK is changed. Serial data sent by the transmitter can be synchronized either with the trailing or with the
leading edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of
the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the
leading edge.
The LR channel select line indicates the channel being transmitted. I2SLRCLK may be changed either on a
trailing or leading edge of the serial clock, but it does not need to be symmetrical. In the slave, this signal is
latched on the leading edge of the clock signal. The I2SLRCLK line changes one clock period before the MSB is
transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for
transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word.
3.4.3.2 MSB (Left) Justified
MSB-Justified (Left-Justified) format is similar to IIS bus format, except that in MSB-justified format, the transmitter
always sends the MSB of the next word at the same time whenever the I2SLRCLK is changed.