Samsung S5PC110, Manual

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S5PC110_UM 8 TRANSPORT STREAM INTERFACE
8-21
8.2.2.3 TSI SYNC Control Register (TS_SYNC, R/W, Address = 0xEB40_0008)
TS_SYNC Bit Description R/W Initial State
Reserved [31:20] - R -
sync_csdc3 [19:16] Specifies the Current sync detecting count3. R 4’h0
sync_csdc2 [15:12] Specifies the Current sync detecting count2. R 4’h0
sync_csdc1 [11:8] Specifies the Current sync detecting count1. R/W 4’h0
sync_det_cnt [7:4] Specifies the Sync detecting count. If the sync
detecting mode uses sync byte, this field indicates the
initial detecting count. - 4’hF
Reserved [3:2] - R/W -
sync_det_mode [1:0] Specifies the Sync detecting mode.
00 = Using TS_SYNC (detecting consecutive 8-bit)
01 = Using TS_SYNC (detecting only 1-bit)
1x = Using sync byte (0x47)
2’b00
8.2.2.4 TSI Clock Count Register (TS_CNT, R/W, Address = 0xEB40_000C)
TS_CNT Bit Description R/W Initial State
ts_clk_error_cnt [31:0] Specifies the TS_CLK timeout period. If the ts_clk
does not toggle for n-times of hclk, ts_clk_timeout
interrupt is generated.
TS_CLK timeout period: HCLK(7.5ns) * n
R/W 32’h00FF_FFFF
8.2.2.5 TS Buffer Base Address Register (TS_BASE, R/W, Address = 0xEB40_0010)
TS_BASE Bit Description R/W Initial State
ts_base_addr [31:2] Specifies the TS buffer base address (word aligned). R/W 30’h0
- [1:0] - - -
8.2.2.6 TS Buffer Size Address Register (TS_SIZE, R/W, Address = 0xEB40_0014)
TS_SIZE Bit Description R/W Initial State
Reserved [31:16] - - -
ts_buffer_size [15:0] This field should be 47-word (188-byte) * n
, where n specifies the stream packet word count
(0~348 word).
If the buffer is full, the buffer write address is cleared to
the buffer base address. R/W 16’h0