Samsung S5PC110, Manual

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S5PC110_UM 5 PCM AUDIO INTERFACE
5-2
5.3 PCM AUDIO INTERFACE
The PCM Audio Interface provides a serial interface to an external Codec. The PCM module receives an input
PCMCODEC_CLK to generate the serial shift timing. The PCM interface outputs a serial data out, a serial shift
clock, and a sync signal. Data is received from the external Codec over a serial input line. The serial data in, serial
data out, and sync signal are all synchronized to the serial shift clock.
The serial shift clock, PCMSCLK, is generated from a programmable divide of the input PCMCODEC_CLK. The
sync signal, PCMSYNC, is generated based upon a programmable number of serial clocks and is one serial clock
wide.
The PCM data words are 16-bit wide, serially shifted out 1-bit per PCMSCLK. Only one 16-bit word is shifted out
for each PCMSYNC. The PCMSCLK will continue to toggle even after all 16-bit have been shifted out. The
PCMSOUT data iis not valid after the 16-bit word is complete. The next PCMSYNC will signal the start of the next
PCM data word.
The TX FIFO provides the 16-bit data word to be serially shifted out. This data is serially shifted out MSB first, one
bit per PCMSCLK. The PCM serial output data, PCMSOUT, is clocked out using the rising edge of the PCMSCLK.
The MSB bit position relative to the PCMSYNC is programmable to either match the PCMSYNC or one PCMCLK
later. After all 16-bit have been shifted out, to indicate the end of the transfer you can generate an interrupt.
At the same time data is being shifted out, the PCMSIN input is used to serially shift data from the external codec.
The data is received MSB first and is clocked in on the falling edge of PCMSCLK. The position of the first bit is
programmable to be coincident with the PCMSYNC or one PCMSCLK later.
The first 16-bit are serially shifted into the PCM_DATAIN register which is then loaded into the RX FIFO.
Subsequent bits are ignored until the next PCMSYNC.
Various Interrupts are available to indicate the status of the RX and TX FIFO. Each FIFO has a programmable flag
to indicate when the CPU needs to service the FIFO. In the RX FIFO, there is an interrupt, which will be raised
when the FIFO exceeds a certain programmable ALMOST_FULL depth. Similarly there is a programmable
ALMOST_EMPTY interrupt for the TX FIFO.