Samsung S5PC110, Manual

Page: 1841 / 2426

S5PC110_UM 2 IIS MULTI AUDIO INTERFACE
2-24
2.9.1.2 IIS Interface Mode Register (IISMOD, R/W, Address = 0xEEE3_0004)
IISMOD Bit Description R/W Initial State
OP_CLK [31:30] Operation clock for IIS logic.
00 = Codec clock out
01 = Codec clock in
10 = Bit clock out
11 = Audio bus clock
R/W 00
Reserved [29] - R 0
OP_MUX_SEL [28] Mux selection for secondary TX FIFO_S
0 = TX FIFO_S gets data from APB SFR interface
1 = TX FIFO_S gets data form internal DMA interface
Before trying to change this field from 1 to 0, s/w must poll
IISTRNCNT register to confirm that all the transfer is done
according to internal DMA setting.
There is no restriction on switching from 0 to 1.
R/W 0
BLC_S [27:26] Bit Length Control Bit which decides transmission of
8/16/24 bits per audio channel for Secondary TX FIFO_S
00 = 16 Bits per channel
01 = 8 Bits Per Channel
10 = 24 Bits Per Channel
11 = Reserved
R/W 00
BLC_P [25:24] Bit Length Control Bit Which decides transmission of
8/16/24 bits per audio channel for Primary TX FIFOx
00 = 16 Bits per channel
01 = 8 Bits Per Channel
10 = 24 Bits Per Channel
11 = Reserved
R/W 00
Reserved [23:22] - R 00
CDD2 [21:20] Channel-2 Data Discard. Discard means zero padding. It
only supports 8/16 bit mode.
00 = No Discard
01 = I2STXD[15:0] Discard
10 = I2STXD[31:16] Discard
11 = Reserved
R/W 00
CDD1 [19:18] Channel-1 Data Discard. Discard means zero padding. It
only supports 8/16 bit mode.
00 = No Discard
01 = I2STXD[15:0] Discard
10 = I2STXD[31:16] Discard
11 = Reserved
R/W 00
DCE [17:16] Enables Data Channel.
[17]: Enables SD2 channel
[16]: Enables SD1 channel
R/W 00
Reserved [15] - R 0