Samsung S5PC110, Manual

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S5PC110_UM 7 SD/MMC CONTROLLER
7-80
CAPAREG Bit Description Initial State
This bit indicates whether the Host Controller is capable of using
ADMA2.
1 = ADMA2 Support
0 = ADMA2 not Support
Reserved [28] Reserved 0
CAPAMAXBLKLEN [17:16] Max Block Length (HWInit)
This value indicates the maximum block size that the Host Driver
can read and write to the buffer in the Host Controller. The buffer
transfers this block size without wait cycles. Three sizes are
defined as indicated below.
00 = 512-byte
01 = 1024-byte
10 = 2048-byte
11 = Reserved
0
Reserved [15:14] Reserved 0
CAPABASECLK [13:8] Base Clock Frequency For SD Clock (HWInit)
This value indicates the base (maximum) clock frequency for the
SD Clock. Unit values are 1MHz. If the real frequency is
16.5MHz, the lager value is set to 01 0001b (17MHz) because
the Host Driver use this value to calculate the clock divider value
(Refer to the SDCLK Frequency Select in the Clock Control
register.) and it does not exceed upper limit of the SD Clock
frequency. The supported clock range is 10MHz to 63MHz. If
these bits are all 0, the Host System has to get information via
another method.
Not 0 = 1MHz to 63MHz
000000b = Get information via another method
0
CAPATOUTUNIT [7] Timeout Clock Unit (HWInit)
This bit shows the unit of base clock frequency used to detect
Data Timeout Error.
0 = kHz
1 = MHz
1
Reserved [6] Reserved 0
CAPATOUTCLK [5:0] Timeout Clock Frequency (HWInit)
This bit shows the base clock frequency used to detect Data
Timeout Error. The Timeout Clock Unit defines the unit of this
field value.
Timeout Clock Unit =0 [kHz] unit: 1kHz to 63kHz
Timeout Clock Unit =1 [MHz] unit: 1MHz to 63MHz
Not 0 = 1kHz to 63kHz or 1MHz to 63MHz
00 0000b = Get information via another method
0