Samsung S5PC110, Manual

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S5PC110_UM 1 0BDISPLAY CONTROLLER
1-99
1.5.2.35 Rame Buffer Address 2 Register (VIDW)
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VIDW00ADD2, R/W, Address = 0xF800_0100
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VIDW01ADD2, R/W, Address = 0xF800_0104
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VIDW02ADD2, R/W, Address = 0xF800_0108
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VIDW03ADD2, R/W, Address = 0xF800_010C
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VIDW04ADD2, R/W, Address = 0xF800_0110
VIDWxxADD2 Bit Description Initial State
OFFSIZE_F [25:13] Specifies the Virtual screen offset size (number of byte).
This value defines the difference between address of last byte
displayed on the previous Video line and address of first byte
to be displayed in the new Video line.
OFFSIZE_F must have value that is multiple of 4-byte size or
0. 0
PAGEWIDTH_F [12:0] Specifies the Virtual screen page width (number of byte).
This value defines the width of view port in the frame.
PAGEWIDTH must have bigger value than the burst size and
the size must be aligned word boundary. 0
NOTE:
‘PAG OFFSET’ should be aligned double-word aligned (8-byte).
1.5.2.36 Video Interrupt Control 0 Register (VIDINTCON0, R/W, Address = 0xF800_0130)
VIDINTCON0 Bit Description Initial State
Reserved [31:26] Reserved 0
FIFOINTERVAL [25:20] Controls the interval of the FIFO interrupt. 0
SYSMAINCON [19] Sends complete interrupt enable bit to Main LCD
0 = Disables Interrupt
1 = Enables Interrupt
Note: This bit is meaningful if both INTEN and I80IFDONE are
high.
0
SYSSUBCON [18] Sends complete interrupt enable bit to Sub LCD
0 = Disables Interrupt.
1 = Enables Interrupt.
Note: This bit is meaningful if both INTEN and I80IFDONE are
high. 0
I80IFDONE [17] Enables the I80 Interface Interrupt (only for I80 Interface
mode).
0 = Disables Interrupt.
1 = Enables Interrupt.
Note: This bit is meaningful if INTEN is high. 0
FRAMESEL0 [16:15] Specifies the Video Frame Interrupt 0 at start of:
00 = BACK Porch
01 = VSYNC
10 = ACTIVE 0