Samsung S5PC110, Manual

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S5PC110_UM 1 VECTORED INTERRUPT CONTROLLER
1-26
1.4.1.24 Interrupt select register
(TZICIntSelect, R/W, Address=0xF280_0008, 0xF290_0008, 0xF2A0_0008, 0xF2B0_0008)
TZICRawIntr Bit Description Initial State
IntSelect [31:0] Selects whether the interrupt source generates an FIQ
interrupt or passes straight through to TZICIRQOUT.
0 = Interrupt passes through to TZICIRQOUT
1 = Interrupt is available for FIQ generation
0x00000000
1.4.1.25 FIQ Enable Register
(TZICFIQEnable, R/W, Address=0xF280_000C, 0xF290_000C, 0xF2A0_000C, 0xF2B0_000C)
TZICFIQEnable Bit Description Initial State
FIQEnable [31:0] Enables the FIQ-selected interrupt lines, allowing the
interrupts to reach the processor.
Read:
0 = Disables Interrupt
1 = Enables Interrupt.
To enable the interrupt use this register. You must use the
TZICFIQEnClear Register to disable the interrupt enable.
Write:
0 = No effect
1 = Enables Interrupt.
If Reset it disables all interrupts. There is 1 bit of the register
for each interrupt source.
0x00000000
1.4.1.26 FIQ Enable Clear Register
(TZICFIQENClear, W, Address=0xF280_0010, 0xF290_0010, 0xF2A0_0010, 0xF2B0_0010)
TZICFIQENClear Bit Description Initial State
FIQEnClear [31:0] Clears bits in the TZICFIQEnable Register.
Writing a HIGH clears the corresponding bit in the
TZICFIQEnable Register.
Writing a LOW has no effect.
-
1.4.1.27 FIQ Bypass Register
(TZICFIQBypass, R/W, Address=0xF280_0014, 0xF290_0014, 0xF2A0_0014, 0xF2B0_0014)
TZICFIQBypass Bit Description Initial State
- [31:1] Read undefined. Write as 0. 0x0
FIQBypass [0] Enables nNSFIQIN to route directly to nFIQ.
0 = No Bypass
1 = Bypass.
0x0