Samsung S5PC110, Manual

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S5PC110_UM 4 POWER MANAGEMENT
4-49
4.10.4.10 Power Management Register (OSC_FREQ, R/W, Address = 0xE010_C100)
OSC_FREQ Bit Description Initial State
Reserved [31:4] Reserved 0x000_0000
OSC_FREQ_VALUE [3:0] Oscillator frequency scale counter
( OSC_FREQ_VALUE / oscillator_frequency > 200ns) 0xF
4.10.4.11 Power Management Register (OSC_STABLE, R/W, Address = 0xE010_C104)
OSC_STABLE Bit Description Initial State
Reserved [31:20] Reserved 0x000
OSC_CNT_VALUE [19:0] 20-bit oscillator stable counter value.
It sets required period of time for oscillator to be stabilized.
Whenever oscillator is turned on, corresponding counter
increments from zero until it gets 16 times as big as this field
value.
The reference clock for the counter is external oscillator clock
input.
0x0_FFFF
4.10.4.12 Power Management Register (PWR_STABLE, R/W, Address = 0xE010_C108)
PWR_STABLE Bit Description Initial State
Reserved [31:20] Reserved 0x000
PWR_CNT_VALUE [19:0]
20-bit power stable counter value.
It sets required period of time for external power regulator to
be stabilized.
Whenever external power regulator is turned on,
corresponding counter increments from zero until it gets 16
times as big as this field value.
The reference clock for the counter is external oscillator clock
input.
0x0_FFFF
4.10.4.13 Power Management Register (MTC_STABLE, R/W, Address = 0xE010_C110)
MTC_STABLE Bit Description Initial State
AUDIO [31:28] Memory power stabilization counter for Audio sub-block 0xF
Reserved [27:24] Reserved 0x0
CAM [23:20] Memory power stabilization counter for CAM-block 0xF
TV [19:16] Memory power stabilization counter for TV-block 0xF
LCD [15:12] Memory power stabilization counter for LCD-block 0xF
G3D [11:8] Memory power stabilization counter for G3D block 0xF
MFC [7:4] Memory power stabilization counter for MFC-block 0xF
TOP [3:0] Memory power stabilization counter for TOP block 0xF