Samsung S5PC110, Manual

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S5PC110_UM 4 POWER MANAGEMENT
4-7
4.3.2 NORMAL MODE
In NORMAL mode, clock gating, power gating, and frequency scaling can be used for power saving.
Clock gating can be done on the basis of module-by-module. In other words, you can decide which modules to
turn on or off. To disable the clock of one or more modules, set the corresponding bits in clock gating control
registers CLK_GATE_IP0-4 and CLK_GATE_BLOCK in SYSCON module. Changing these bits (except some bits
related AXI modules) will enable/ disable the clock to corresponding modules immediately.
Some bits related to AXI modules will disable the clock input after some time, but will enable the clock input
almost immediately. The delay to disable the clock input is due to handshaking procedure of Low power interface.
If you want to disable the AXI module, set the bit related to that module to 1’b0, then SYSCON asserts CSYSREQ
to 1’b0 to request the AXI module to enter the low power state. If the module asserts CSYSACK to 1’b0, then
SYSCON will disable the clock to that module.
NOTE:
Use Standby mode to disable CPU clock internally. The Standby mode is one of the power modes of ARM Cortex-A8.
The clock to CPU is disabled to reduce switching current in ARM Cortex-A8. When S5PC110 enters IDLE mode, CPU
clock is disabled using Standby mode, where application program is not running until wakeup event occurs.
Frequency scaling is done in PLL-by-PLL basis. Change the PLL P/M/S values to lower the operating frequency of
the modules. Changing a P/M/S value results in PLL lock operation, which takes maximum 100us time. S5PC110
stops its operation during the PLL lock period, since the PLL output clock is masked. For more information on how
to change P/M/S value and related clock divider value, refer to Chapter 2.10, "Clock Strategy".
Power gating is done on the basis of block-by-block. Set the corresponding bits in NORMAL_CFG register to
perform power gating in one or more blocks. The IP blocks that can be power-gated in NORMAL mode are MFC,
G3D, IMG sub-system, LCD sub-system, and TV sub-system (Refer to
Table 4-2
).
Power gating of a block will disconnect the current path to the logic gates.
The power domain can also be powered “ON” by setting the corresponding bit in NORMAL_CFG register. Change
the multiple bits in the NORMAL_CFG registers to power “ON” or power-gate multiple power domains at the same
time. However, you should not initiate power “ON” (or power-gate) before power gating (or power on) is complete.
Power gating status of each power domain is found in the BLK_PWR_STAT register. BLK_PWR_STAT is not
updated until the power-up or power-down process is completed. NORMAL_CFG and BLK_PWR_STAT will have
different values while the power-up or power-down procedure is in progress, and will have the same value after
the power state change is completed. Look up BLK_PWR_STAT register value to know whether power gating is
complete or not.
The power gating does not preserve the state of normal flip-flops in the power-down domain. A power domain
(except TOP domain) has only normal F/Fs and is not implemented with retention F/Fs. Therefore, a power
domain (except TOP domain) namely sub-domain does not preserve the state of F/Fs when the sub-domain is
power-gated. When a sub-domain is powered up again, a wakeup reset is asserted for the modules in the sub-
domain. However, top domain has retention F/Fs instead of normal F/Fs, therefore top domain keeps the state of
F/Fs when the top domain is power-gated. When top domain is powered up again, a wakeup reset is not asserted
for the modules in the top domain.
The power-up takes time to stabilize the internal logic gates and memory after power is supplied again. The
power-up time is required because a simultaneous power-up of all logic gates and memories is not allowed since
it will drain a large amount of current in a very short period and cause system malfunction consequently.