Samsung S5PC110, Manual

Page: 314 / 2426

S5PC110_UM 3 CLOCK CONTROLLER
3-17
Register Address R/W Description Reset Value
4)
CLKDIV_IEM_L3 0xE010_3214 R/W Clock divider for IEM (performance level-
3) 0x0000_0000
CLKDIV_IEM_L2 0xE010_3218 R/W Clock divider for IEM (performance level-
2) 0x0000_0000
CLKDIV_IEM_L1 0xE010_321C R/W Clock divider for IEM (performance level-
1) 0x0000_0000
Reserved 0xE010_3220~
0xE010_32FC
- Reserved -
APLL_CON1_L8 0xE010_3300 R/W Control PLL AFC (performance level-1) 0x0000_0000
APLL_CON1_L7 0xE010_3304 R/W Control PLL AFC (performance level-7) 0x0000_0000
APLL_CON1_L6 0xE010_3308 R/W Control PLL AFC (performance level-6) 0x0000_0000
APLL_CON1_L5 0xE010_330C R/W Control PLL AFC (performance level-5) 0x0000_0000
APLL_CON1_L4 0xE010_3310 R/W Control PLL AFC (performance level-4) 0x0000_0000
APLL_CON1_L3 0xE010_3314 R/W Control PLL AFC (performance level-3) 0x0000_0000
APLL_CON1_L2 0xE010_3318 R/W Control PLL AFC (performance level-2) 0x0000_0000
APLL_CON1_L1 0xE010_331C R/W Control PLL AFC (performance level-1) 0x0000_0000
Reserved 0xE010_3320~
0xE010_7004
- Reserved -
DISPLAY_CONTROL 0xE010_7008 R/W Display output path selection. 0x0000_0000
AUDIO_ENDIAN 0xE010_700C R/W Endian selection for audio subsystem 0x0000_0000
SFRs consist of several parts.
The SFRs with address 0xE010_0XXX controls clock-related logics. They control the output frequency of three
PLLs, clock source selection, clock divider ratio, and clock gating.
The SFRs with address 0xE010_2XXX controls SW reset.
The SFRs with address 0xE010_3XXX controls IEM block.
The SFRs with address 0xE010_6XXX controls S5PC110 system.
The SFRs withe address 0xE010_7XXX include miscellaneous registers.
The SFRs with address 0xE010_8XXX controls the power management block.