S5PC110_UM
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
1-20
1.6.1.4 UART Modem Control Register
•
UMCON0, R/W, Address = 0xE290_000C
•
UMCON1, R/W, Address = 0xE290_040C
•
UMCON2, R/W, Address = 0xE290_080C
•
Reserved (Address = 0xE290_0C0C)
There are three UART MODEM control registers in the UART block, namely, UMCON0, UMCON1 and UMCON2.
UMCONn
Bit
Description
Initial State
Reserved [31:8]
Reserved
0
RTS trigger Level
[7:5] Determines the trigger level of Rx FIFO to control nRTS
signal. If AFC bit is enabled and Rx FIFO have bytes that are
greater than or equal to the trigger level, nRTS signal is
deactivated.
[Channel 0]
000 = 255 bytes 001 = 224 bytes
010 = 192 bytes 011 = 160 bytes
100 = 128 bytes 101 = 96 bytes
110 = 64 bytes 111 = 32 bytes
[Channel 1]
000 = 63 bytes 001 = 56 bytes
010 = 48 bytes 011 = 40 bytes
100 = 32 bytes 101 = 24 bytes
110 = 16 bytes 111 = 8 bytes
[Channel 2]
000 = 15 bytes 001 = 14 bytes
010 = 12 bytes 011 = 10 bytes
100 = 8 bytes 101 = 6 bytes
110 = 4 bytes 111 = 2 bytes
000
Auto Flow Control (AFC)
[4]
0 = Disables
1 = Enables
0
Modem Interrupt Enable
[3] 0 = Disables
1 = Enables
0
Reserved
[2:1] These bits must be 0
00
Request to Send
[0]
If AFC bit is enabled, this value will be ignored. In this case
the S5PC110 controls nRTS signals automatically.
If AFC bit is disabled, the software must control nRTS signal.
0 = 'H' level (Inactivate nRTS)
1 = 'L' level (Activate nRTS)
0
NOTE:
UART 2 supports AFC function, if nRxD3 and nTxD3 are set as nRTS2 and nCTS2 by GPA1CON.
UART 3 does not support AFC function, because the S5PC110 has no nRTS3 and nCTS3.
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...