Samsung S5PC110, Manual

Page: 1397 / 2426

S5PC110_UM 6 5BMULTI FORMAT CODEC
6-5
6.2 HARDWARE OVERVIEW
6.2.1 BLOCK DIAGRAM
Top level of the MFC in
Figure 6-1
contains the hardware modules, including an OpenRISC with 8KB I-cache and
4KB D-cache. The optimum partition of the codec functions into software and hardware has ensured that the small
sized hardware supports multiple standards. The hardware operates encoding and decoding at the slice level. On
the other hand, the firmware on RISC performs other processing, such as slice header parsing and/or generation.
Settings by the host processor can be changed at the frame boundary through the host interface.
Figure 6-1
presents a block diagram of MFC which is composed of RISC, MFC core, RG, bus interface, host
interface, and stream interface. MFC core includes many codec accelerators. RG stands for register group which
can be accessed by RISC and HOST. Host and RISC can communicate through registers in RG and risc2host
interrupt generated by register in RG. If RISC gets some interrupt or information from HW, RISC set the registers
to let host know the status of MFC. Host clears the interrupt signal by resetting the MFC_RISC_HOST_INT
register.
There are two AXI master interfaces in which both Port_A and Port_B are used for full performance. As per the
AXI standard, MFC masters take care of read/write hazard issues. Before read access of written data by MFC,
internal masters in MFC always check the response of write access.
The search SRAM in the diagram contains reference image for motion estimation and motion compensation.
The shared SRAM is for sharing current image for encoding.
To reduce bandwidth for reference image loading, there is a pixel cache in the MFC core. The size is 2KB for luma
and 1KB for chroma. In encoding case, only chroma reference will be loaded by pixel cache, because luma
reference is already loaded in search SRAM for motion estimation. To use the pixel cache in decoding,
reconstruction image have to be placed in Port_A memory area.