Samsung S5PC110, Manual

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S5PC110_UM 1 DRAM CONTROLLER
1-35
1.4.1.8 PHY Control1 Register (PhyControl1, R/W, Address = 0xF000_001C, 0xF140_001C)
PHYCONTROL1 Bit Description R/W
Initial
State
Reserved [31:23] Should be zero 0x0
ctrl_offsetd [22:16] This field is for debug purpose.
If this field is fixed, field value must not be changed during
operation. This value is valid after ctrl_resync becomes HIGH
and LOW.
offset amount for 270' clock generation
ctrl_offsetd[6] = 1 : (tFS : fine step delay)
270' delay amount - ctrl_offsetd[5:0] x
tFS
ctrl_offsetd[6] = 0 :
270' delay ctrl_offsetd[5:0] x
tFS
R/W 0x0
drv_type [15] Driving Type of Bidirectional Pins in Idle State
0x0 = Drive all to zeros
0x1 = Pull down all
If CAS or read data latency is 2, this register must not set be to
0x0. 0x0
ctrl_offsetc [14:8] Delay Offset for DQS Cleaning
Gate offset amount for DDR. If this field is fixed, this value
should not be changed during operation. This value is valid
after ctrl_resync becomes HIGH and LOW.
ctrl_offsetc[6] = 1 : (tFS : fine step delay)
GATEout delay amount - ctrl_offsetc[5:0] x
tFS
ctrl_offsetc[6] = 0 :
GATEout delay ctrl_offsetc[5:0] x
tFS
R/W 0x0
ctrl_ref [7:4] Reference Count for DLL Lock Confirmation R/W 0x4
fp_resync [3] Force DLL Resynchronization R/W 0x0
ctrl_shiftc [2:0] Phase Delay for DQS Cleaning
GATEout signal delay amount for DDR. If this field is fixed, this
value should not be changed during operation. This value is
valid after ctrl_resync becomes HIGH and LOW.
0x0 = T/128 (2.8125' shift)
0x1 = T/64 (5.625' shift)
0x
2
= T/32 (11.25' shift)
0x
3
= T/16 (22.5' shift)
0x
4
= T/8 (45' shift)
0x
5
= T/4 (90' shift)
0x
6
= T/2 (180' shift)
0x
7
= T (360' shift)
Recommended values according to memory type :
0x
5
when LPDDR/LPDDR2 @200MHz
0x
6
when DDR2 @200MHz
R/W 0x0