Samsung S5PC110, Manual

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S5PC110_UM 5 PCM AUDIO INTERFACE
5-3
5.4 PCM TIMING
Figure 5-1
shows the timing relationship for the PCM transfers.
Note in all cases, the PCM shift timing is derived by dividing the input clock, PCMCODEC_CLK. While the timing
is based upon the PCMCODEC_CLK, there is no attempt to realign the rising edge of the output PCMSCLK with
the original PCMCODEC_CLK input clock. These edges will be skewed by internal delay through the pads as well
as the divider logic. This does not represent a problem because the actual shift clock, PCMSCLK, is synchronized
with the data. Furthermore, even if the PCMSCLK output is not used, the skew will be significantly less than the
period of the PCMCODEC_CLK and does not represent a problem since most PCM interfaces capture data on the
falling edge of the clock.
Figure 5-1
shows a PCM transfer with the MSB configured to be coincident with the PCMSYNC. This MSB
positioning corresponds to setting the TX_MSB_POS and RX_MSB_POS bits in PCMCTL register to be 0.
PCMFSYNC
PCMSOUT
14 15 13 1 0 dont care 15 14
. . .
output
output
output PCMSCLK
input
pcm_irq
( sync to DSP clk )
14 15 13 1 0 dont care 15 14
. . .
input
internal
PCMSIN
PCMCODEC _CLK
datain_reg_valid
Figure 5-1 PCM timing, POS_MSB_WR/RD = 0