Samsung S5PC110, Manual

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S5PC110_UM 3 IIS-BUS INTERFACE
3-3
3.4 FUNCTIONAL DESCRIPTIONS
IIS interface consists of register bank, FIFOs, shift registers, clock control, DMA finite state machine, and channel
control block as shown in
Figure 3-1
. Note that each FIFO has 32-bit width and 64 depth structure, which contains
left/right channel data. Thus, FIFO access and data transfer are handled with left/right pair unit.
Figure 3-1
shows
the functional block diagram of IIS interface.
3.4.1 MASTER/SLAVE MODE
To select master or slave mode, set IMS bit of IISMOD register. In master mode, I2SSCLK and I2SLRCLK are
generated internally and supplied to external device. Therefore, a root clock is required to generate I2SSCLK and
I2SLRCLK. The IIS pre-scaler (clock divider) is employed to generate a root clock with divided frequency from
internal system clock. In external master mode, the root clock can be directly fed from IIS external. The I2SSCLK
and I2SLRCLK are supplied from the pin (GPIOs) in slave mode. That is, whatever source clock is, Only Master
can generate I2SLRCLK and I2SSCLK.
Master/Slave mode is different compared to TX/RX. Master/Slave mode presents the direction of I2SLRCLK and
I2SSCLK. The direction of I2SCDCLK (This is only auxiliary.) is not important. If IIS bus interface transmits clock
signals to IIS codec, IIS bus is master mode. But if IIS bus interface receives clock signal from IIS codec, IIS bus
is slave mode. TX/RX mode indicates the direction of data flow. If IIS bus interface transmits data to IIS codec,
this indicates TX mode. Conversely, IIS bus interface receives data from IIS codec this indicates RX mode.
Figure 3-2
shows the route of the root clock with internal master or external master mode setting in IIS clock
control block and system controller. Note that RCLK indicates root clock and this clock can be supplied to external
IIS codec chip in internal master mode.
1/N
1/M
PCLK
RCLKSRC
RCLK
BCLKmaster
CODECLKO
CDCLKCON
IIS
OSC
PLLs
CLOCK
CONTROLLER
PAD
Pre-scaler
Figure 3-2 IIS Clock Control Block Diagram