S5PC110_UM
6 5BMULTI FORMAT CODEC
6-4
6.1.3 TARGET PERFORMANCE AND FUNCTIONS
6.1.3.1 Video Decoding Capability
•
Decoding up to 1080p@30fps at 200MHz core clock frequency and 200MHz bus clock frequency
•
The maximum resolution can be limited by the video standards, even though MFC has a capability to handle
up to 1080p.
6.1.3.2 Video Encoding Capability
•
Encoding up to 1080p@30fps at 200MHz core clock frequency and 200MHz bus clock frequency
•
The performance numbers are verified under the condition that the number of reference frames for a P frame
is 1.
•
The maximum resolution can be limited by the video standards, even though MFC has a capability to handle
up to 1080p.
6.1.3.3 Error Detection
•
H264
−
Header
error
detection
o
Checking if firmware parsing is out of range
−
H/W
o
VLD error detection: When there is no stream to decode before stream decoder is complete.
o
Macroblock error detection: When MB type is out of range (i.e., 0~25 @ I slice / 0~30 @ P slice /
0~48 @ B slice)
o
Sub MB type error detection: When sub_MB_type or intra prediction mode is out of range (i.e., Intra
prediction mode 0~7, sub_mb_type 0~2 @ P slice / 0~11 @ B slice)
o
IDF error detection: When ref_idx value is greater than num_ref_idx_lx_active_minus1 (PPS)
o
Delta Q error detection: When mb_qp_delta is out of range (i.e., -26~25)
o
Timeout interrupt: When decoding time is greater than the firmware setting
•
MPEG2/ MPEG4/ H.263/ VC-1
−
Header error detection: When the result of firmware parsing is out of range
−
H/W
o
VLD error: When VLD Result is out of table.
o
Coeff error: When AC/DC coefficient of 1 block is more than 64
o
Time out interrupt: When decoding time is greater than firmware setting
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...