Samsung S5PC110, Manual

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S5PC110_UM 7 SD/MMC CONTROLLER
7-50
PRNSTS Bit Description Initial State
Complete interrupt in the Normal Interrupt Status register.
This bit is set in either of the following cases:
(1) After the end bit of the write command.
(2) If 1 is written to Continue Request in the Block Gap Control
register to continue a write transfer.
This bit is cleared in either of the following cases:
(1) If the SD card releases write busy of the last data block the Host
Controller detects if output is not busy. If SD card does not drive
busy signal for 8 SD Clocks, the Host Controller considers the card
drive “Not Busy”.
(2) If the SD card releases write busy prior to waiting for write
transfer as a result of a Stop At Block Gap Request.
1 = DAT Line Active
0 = DAT Line Inactive
CMDINHDAT [1] Command Inhibit (DAT) (ROC)
(ROC)
This status bit is generated if either the DAT Line Active or the Read
Transfer Active is set to 1. If this bit is 0, it indicates the Host
Controller can issue the next SD Command. Commands with busy
signal belong to Command Inhibit (DAT) (ex. R1b, R5b type).
Changing from 1 to 0 generates a Transfer Complete interrupt in the
Normal Interrupt Status register.
Note: The SD Host Driver saves registers in the range of 000-00Dh
for a suspend transaction after this bit has changed from 1 to 0.
1 = Cannot issue command which uses the DAT line
0 = Issues command which uses the DAT line 0
CMDINHCMD [0] Command Inhibit (CMD) (ROC)
If this bit is 0, it indicates the CMD line is not in use and the Host
Controller issues a SD Command using the CMD line.
This bit is set immediately after the Command register (00Fh) is
written. This bit is cleared if the command response is received.
Even if the Command Inhibit (DAT) is set to 1, Commands using
only the CMD line is issued if this bit is 0. Changing from 1 to 0
generates a Command
Complete interrupt in the Normal Interrupt Status register. If the Host
Controller cannot issue the command because of a command
conflict error (Refer to Command CRC Error) or because of
Command Not Issued By Auto CMD12 Error, this bit remains 1 and
the Command Complete is not set. Status issuing Auto CMD12 is
not read from this bit.
1 = Cannot issue command
0 = Issues command using only CMD line 0
NOTE:
Buffer Write Enable in Present register must not be asserted for DMA transfers since it generates Buffer Write
Ready interrupt.