S5PC110_UM
6 5BMULTI FORMAT CODEC
6-57
6.3.4.1.7 Memory Structure Setting Register of Current Frame (ENC_MAP_FOR_CUR, R/W, Address =
0xF170_C51C)
ENC_MAP_FOR_CUR
Bit
Description
Initial State
Reserved [31:2]
Reserved
0
ENC_MAP_FOR_CUR [1:0]
Memory
structure of the current frame
0 = Linear mode
3 = 64x32 tiled mode
0
6.3.4.1.8 Padding Value Control Register (ENC_PADDING_CTRL, R/W, Address = 0xF170_C520)
ENC_PADDING_CTRL
Bit
Description
Initial State
PAD_CTRL_ON
[31]
0 = Use boundary pixel for current image padding in
case that its image size is not a multiple of 16
1 = Use ENC_PADDING_CTRL[23:0] for current
image padding
0
Reserved [30:24]
Reserved
0
CR_PAD_VAL
[23:16] Value for original CR image’s padding when
PAD_CTRL_ON is 1.
0
CB_PAD_VAL
[15:8]
Value for original CB image’s padding when
PAD_CTRL_ON is 1.
0
LUMA_PAD_VAL
[7:0]
Value for original Y image’s padding when
PAD_CTRL_ON is 1.
0
6.3.4.1.9 Encoder Intra Mode Bias Register (ENC_COMMON_INTRA_BIAS, R/W, Address = 0xF170_C588)
ENC_INT_MASK
Bit
Description
Initial State
Reserved [31:16]
Reserved
0
ENC_COMMON_INTRA_BIAS
[15:0] The register is used in favor of the intra mode in the
weighted macroblock mode decision.
Mode decision will be done by comparing 1)
inte ENC_COMMON_INTRA_BIAS and 2)
intra_cost.
If inter_cost is zero, the mode is always determined to
inter macroblock.
To disable this option, set
ENC_COMMON_INTRA_BIAS to zero.
0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...