S5PC110_UM
5 INTELLIGENT ENERGY MANAGEMENT
5-26
5.5.2.17 DPM Command Register (IECDPMCR, R/W, Address = 0xE080_0100)
IECDPMCR
Bit
Description
Initial State
Reserved [31:12]
Reserved,
read undefined, do not modify.
0
DPMCH3CMD
[11:8]
DPM Channel 3 command.
0
DPMCH2CMD
[7:4]
DPM Channel 2 command.
0
DPMCH1CMD
[3:0]
DPM Channel 1 command.
0
DPMCHxCMD
Command
Description
Initial State
b’0000
Freeze
The channel is frozen and stops accumulating.
This is also the reset value.
0
b’0001
Reset
The channel is reset to zero.
0
b’0010
Accumulate
The channel starts accumulating.
0
5.5.2.18 DPM Channel Rate Registers (IECDPM2RATE, R/W, Address = 0xE080_0108)
IECDPM2RATE
Bit
Description
Initial State
-
[31:8]
Reserved, read undefined, do not modify.
0
IECDPM2RATE
[7:0]
The fractional rate that DPM channel 2 counts. The
reset value of this register is 0x80, that is, 100%.
0x80
5.5.2.19 DPM Channel Rate Registers (IECDPM3RATE, R/W, Address = 0xE080_010C)
IECDPM3RATE
Bit
Description
Initial State
-
[31:8] Reserved, read undefined, do not modify.
0
IECDPM3RATE
[7:0]
The fractional rate that DPM channel 3 counts. The
reset value of this register is 0x80, that is, 100%.
0x80
5.5.2.20 DPM Channel Registers (IECDPM1LO, R, Address = 0xE080_0180)
IECDPM1LO
Bit
Description
Initial State
IECDPM1LO
[31:0]
Low 32-bit of DPM channel 1.
The reset value is 0x00000000.
0x00000000.
5.5.2.21 DPM Channel Registers (IECDPM1HI, R, Address = 0xE080_0184)
IECDPM1HI
Bit
Description
Initial State
IECDPM1HI
[31:0]
High 32-bit of DPM channel 1.
The reset value is 0x00000000.
0x00000000
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...