S5PC110_UM
7 SD/MMC CONTROLLER
7-63
7.10.11 NORMAL INTERRUPT STATUS REGISTER
7.10.11.1 Normal Interrupt Status Register
•
NORINTSTS0, ROC/RW1C, Address = 0xEB00_0030
•
NORINTSTS1, ROC/RW1C, Address = 0xEB10_0030
•
NORINTSTS2, ROC/RW1C, Address = 0xEB20_0030
•
NORINTSTS3, ROC/RW1C, Address = 0xEB30_0030
The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not
affect these reads. An interrupt is generated if the Normal Interrupt Signal Enable is enabled and at least one of
the status bits is set to 1. For all bits except Card Interrupt and Error Interrupt, writing 1 to a bit clears it; writing 0
keeps the bit unchanged. More than one status is cleared with a single register write. The Card Interrupt is cleared
if the card stops asserting the interrupt; that is, if the Card Driver services the interrupt condition.
NORINTSTS
Bit
Description
Initial State
STAERR [15]
Error
Interrupt
If any of the bits in the Error Interrupt Status register are set, then
this bit is set. Therefore the Host Driver checks this bit first to
efficiently tests for an error. This bit is read only. (ROC)
0 = No Error
1 = Error
0
STAFIA3
[14]
FIFO SD Address Pointer Interrupt 3 Status (RW1C)
0 = Occurred
1 = Not Occurred
If the FIFO Address of the SD clock side reaches the FIFO
Interrupt Address register 3 values, this status bit is asserted.
0
STAFIA2
[13]
FIFO SD Address Pointer Interrupt 2 Status (RW1C)
0 = Occurred
1 = Not Occurred
If the FIFO Address of the SD clock side reaches the FIFO
Interrupt Address register 2 values, this status bit is asserted.
0
STAFIA1
[12]
FIFO SD Address Pointer Interrupt 1 Status (RW1C)
0 = Occurred
1 = Not Occurred
If the FIFO Address of the SD clock side reaches the FIFO
Interrupt Address register 1 value, this status bit is asserted.
0
STAFIA0
[11]
FIFO SD Address Pointer Interrupt 0 Status (RW1C)
0 = Occurred
1 = Not Occurred
If the FIFO Address of the SD clock side reaches the FIFO
Interrupt Address register 0 value, this status bit is asserted.
0
STARWAIT
[10]
Read Wait Interrupt Status (RW1C)
0 = Read Wait Interrupt Not Occurred
1 = Read Wait Interrupt Occurred
Note: After checking response for the suspend command,
release Read Wait interrupt status manually if BS = 0 (BS means
0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...