Samsung S5PC110, Manual

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S5PC110_UM 2 IIS MULTI AUDIO INTERFACE
2-29
2.9.1.8 IIS Interface Transmit Data Register for TXFIFO_S (IISTXDS, W, Address = 0xEEE3_001C)
IISTXDS Bit Description R/W Initial State
IISTXDS [31:0] Secondary TX FIFO_S write data. Note that the left/right
channel data is allocated as the following bit fields.
R[31:16], L[15:0] when 16-bit BLC
R[23:16], L[7:0] when 8-bit BLC
Refer Figure 10.2-7 when 24-bit BLC
W 0x00
2.9.1.9 IIS AHB DMA Control Register (IISAHB, R/W, Address = 0xEEE3_0020)
IISAHB Bit Description R/W Initial State
Reserved [31:28] - R 0x00
IISLVL3EN [27] Enables buffer level 3 interrupt.
0 = Disables IISLVL3INT.
1 = Enables IISLVL3INT.
R/W 0
IISLVL2EN [26] Enables buffer level 2 interrupt.
0 = Disables IISLVL2INT.
1 = Enables IISLVL2INT.
R/W 0
IISLVL1EN [25] Enable buffer level 1 interrupt.
0 = Disables IISLVL1INT.
1 = Enables IISLVL1INT.
R/W 0
IISLVL0EN [24] Enable buffer level 0 interrupt.
0 = Disables IISLVL0INT.
1 = Enables IISLVL0INT.
R/W 0
IISLVL3INT [23] Buffer level 3 interrupt status flag.
During operation of DMA, when generated address in DMA
matches with IISLVL3ADDR, this flag will be set. To clear this
flag, use IISLVL3CLR field.
R 0
IISLVL2INT [22] Buffer level 2 interrupt status flag.
During operation of DMA, when generated address in DMA
matches with IISLVL2ADDR, this flag will be set. To clear this
flag, use IISLVL2CLR field.
R 0
IISLVL1INT [21] Buffer level 1 interrupt status flag.
During operation of DMA, when generated address in DMA
matches with IISLVL1ADDR, this flag will be set. To clear this
flag, use IISLVL1CLR field.
R 0
IISLVL0INT [20] Buffer level 0 interrupt status flag.
During operation of DMA, when generated address in DMA
matches with IISLVL0ADDR, this flag will be set. To clear this
flag, use IISLVL0CLR field.
R 0
IISLVL3CLR [19] Clear IISLVL3INT flag
When IISLVL3INT is set, setting IISLVL3CLR to 1 will clear
IISLVL3INT to 0. Writing zero has no effect.
R/W 0