Samsung S5PC110, Manual

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S5PC110_UM 2 IIC-BUS INTERFACE
2-6
2.3.4 READ-WRITE OPERATION
In data is transmitted in Transmitter mode, the I
2
C-bus interface waits until I
2
C-bus Data Shift (I2CDS) register
receives the new data. Before the new data is written to the register, the SCL line is held low. The line is only
released after the data has been written. S5PC110 holds the interrupt to identify the completion of current data
transfer. After the CPU receives the interrupt request, it writes new data to the I2CDS register again.
If data is received in Receive mode, the I
2
C-bus interface waits until I2CDS register is read. Before the new data
is read out, the SCL line is held low. The line is only released after the data has been read. S5PC110 holds the
interrupt to identify the completion of new data reception. After the CPU receives the interrupt request, it reads the
data from the I2CDS register.
2.3.5 BUS ARBITRATION PROCEDURES
Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with
a SDA High level detects other master with a SDA active Low level, it does not initiate a data transfer because the
current level on the bus does not correspond to its own. The arbitration procedure extends until the SDA line turns
High.
If the masters lower the SDA line simultaneously, each master evaluates whether the mastership is allocated itself
or not. For the purpose of evaluation each master detects the address bits. While each master generates the
slave address, it detects the address bit on the SDA line because the SDA line is likely to get Low rather than
high.
Assume that one master generates a Low as first address bit, while the other master is maintaining High. In this
case, both masters detect Low on the bus because the Low status is superior to the High status in power. If this
happens, Low (as the first bit of address) generating master gets the mastership while High (as the first bit of
address) generating master withdraws the mastership. If both masters generate Low as the first bit of address,
there is arbitration for the second address bit again. This arbitration continues to the end of last address bit.
2.3.6 ABORT CONDITIONS
If a slave receiver cannot acknowledge the confirmation of the slave address, it holds the level of the SDA line
High. In this case, the master generates a Stop condition and cancels the transfer.
If a master receiver is involved in the aborted transfer, it signals the end of slave transmit operation by canceling
the generation of an ACK after the last data byte received from the slave. The slave transmitter releases the SDA
to allow a master to generate a Stop condition.
2.3.7 CONFIGURING I
I
C-BUS
To control the frequency of the serial clock (SCL), the 4-bit prescaler value is programmed in the I2CCON register.
The I
2
C-bus interface address is stored in the I
2
C-bus address (I2CADD) register (By default, the I
2
C-bus
interface address has an unknown value).