Samsung S5PC110, Manual

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S5PC110_UM 3 2BMIPI DSIM
3-6
3.1.3.1 Interface Timing and Protocol
3.1.3.1.1 Display Controller Interface
MIPI DSI Master has two-display controller interfaces, namely, RGB INTERFACE for main display and CPU
INTERFACE (I80 INTERFACE) for main/ sub display. The Video mode uses RGB INTERFACE while the
Command mode uses CPU INTERFACE.
The RGB image data is loaded on the data bus of RGB INTERFACE and I80 INTERFACE with the same order:
RGB_VD[23:0] or SYS_VDOUT[23:0] is {R[7:0],G[7:0],B[7:0]}. Each byte aligns to the most significant bit. For
instance, in the 12-bit mode, only three 4-bit values are valid as R, G, and B each, that is, data[23:20],
data[15:12], and data[7:4]. The DSIM ignores rest of the bits.
3.1.3.1.2 RGB Interface
Vsync, Hsync, and VDEN are active high signals. Among the three signals, Vsync and Hsync are pulse types that
spend several video clocks. RGB_VD[23:0] is {R[7:0],G[7:0],B[7:0]}. All sync signals are synchronized to the rising
edge of RGB_VCLK. The display controller sends minimum one horizontal line length of Vsync pulse, V back
porch, and V front porch. Hsync pulse width should be longer than 1-byte clock cycle.
3.1.3.1.3 HSA Mode
HSA mode specifies the Horizontal Sync Pulse area disable mode.
Hsync start packet
Hsync end packet
Non burst mode
with Sync pulses
(HSAmode)
RGB
HFP HBP
HS
A
RGB
HFP HBP
HS
A
Figure 3-4 Block Timing Diagram of HSA Mode (HSA mode reset: DSIM_CONFIG[20] = 0)
Figure 3-5 Block Timing Diagram of HSA Mode (HSA mode set: DSIM_CONFIG[20] = 1)