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S5PC110_UM
3 SERIAL PERIPHERAL INTERFACE
3-11
3.4.2.3 SPI FIFO Control Register
•
MODE_CFG0,
R/W,
Address = 0xE130_0008
•
MODE_CFG1, R/W, Address = 0xE140_0008
MODE_CFGn
Bit
Description
Initial State
CH_WIDTH
[30:29] 00 = Byte
01 = Halfword
10 = Word
11 = Reserved
0
TRAILING_CNT
[28:19] Count value from writing the last data in RX FIFO to flush
trailing bytes in FIFO
0
BUS_WIDTH [18:17]
00 = Byte
01 = Halfword
10 = Word
11 = Reserved
0
RX_RDY_LVL [16:11]
Rx
FIFO
trigger level in INT mode.
Port 0: trigger level (bytes) = 4 x N
Port 1: trigger level (bytes) = N
(N = value of RX_RDY_LVL field)
0
TX_RDY_LVL
[10:5] Tx FIFO trigger level in INT mode.
Port 0: trigger level (bytes) = 4 x N
Port 1: trigger level (bytes) = N
(N = value of TX_RDY_LVL field)
0
Reserved [4:3]
Reserved
-
RX_DMA_SW
[2]
Rx DMA mode enable/disable
0 = Disables DMA Mode
1 = Enables DMA Mode
0
TX_DMA_SW
[1]
Tx DMA mode on/off
0 = Disables DMA Mode
1 = Enables DMA Mode
0
DMA_TYPE
[0]
DMA transfer type, single or 4 busts.
0 = Single
1 = 4 burst
DMA transfer size must be set as the same size in SPI DMA.
0
NOTE:
1. CH_WIDTH is shift-register width.
2. BUS_WIDTH is SPI FIFO width, transfer data size should be aligned at BUS_WIDTH.
3. CH_WIDTH must be smaller than BUS_WIDTH or same.
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...