S5PC110_UM
2 1BCAMERA INTERFACE
2-50
CISCCTRLn
Bit
Description
Initial State
0 = Enables for DMA output.
If FIFO mode is enabled, then the input mode should be DMA
input and WSWP bit at WINCON0(0xF800_0020) in LCD
controller should be ‘0’.
The FIFO mode output format is YCbCr4;4:4 3 Plane or RGB
24-bit. Its selection depends on OutFormat register.
OutFormat = RGB
→
RGB24bit. Other setting means
YCbCr4:4:4.
If interlace out end DMA input want to set together, Output
mode should be FIFO output
(ML=OO)
Interlace
[25]
Output scan method selection register. (RAW and JPEG input
formats are not available)
1 : Interlace scan out (Input data should be progressive mode)
0 : progressive scan out
Note) If this bit is configured by 0 for interlacced input, the
output is also interlaced format not converted into progressive
one.
(ML=OX)
0
MainHorRatio [24:16]
Specifies
horizontal scale ratio for main-scaler.
Note)
CAMIF1 : Refer to the gathering extension
register(MainHorRatio_ext).
(ML=OO)
0
ScalerStart
[15]
Specifies the Scaler start.
1 = Scaler start
0 = Scaler stop or scaler bypass
(ML=OO)
0
InRGB_FMT
[14:13] Specifies input DMA RGB format.
00 = RGB565, 01 = RGB666
10 = RGB888, 11 = Reserved
(ML=OX)
0
OutRGB_FMT
[12:11] Specifies output DMA RGB format.
00 = RGB565
01 = RGB666
10 = RGB888
11 = Reserved
(ML=OO)
0
Ext_RGB
[10]
Specifies input RGB data extension enable bit for conversion
of RGB565/666 mode to RGB888 mode.
1 = Extension
0 = normal
i) Input R = 5-bit in RGB565 mode
10100 -> 10100101 (Extension): [7]=[2], [6]=[1], [5]=[0]
10100 -> 10100000 (Normal)
0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...