Samsung S5PC110, Manual

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S5PC110_UM 3 CLOCK CONTROLLER
3-39
3.7.5 CLOCK GATING CONTROL REGISTER
There are two types of clock gating control registers for disable/enable operation, namely:
•
Clock gating control register by block
•
Clock gating register for by IP
The above two registers are ANDed together to generate a final clock gating enable signal. As a result, if either of
the two register field is turned OFF, the resulting clock is stopped.
3.7.5.1 Clock Gating Control Register (CLK_GATE_SCLK, R/W, Address = 0xE010_0444)
CLK_GATE_SCLK Bit Description Gated Clock Name Initial State
Reserved [31:6] Reserved Reserved 0x3FF_FFFF
SCLK_FIMC_LCLK [5] Gating special clock for FIMC local clock
(0: mask, 1: pass) SCLK_FIMC_LCLK 1
Reserved [4:0] Should be one for all bit Reserved 0x1F
3.7.5.2 Clock Gating Control Register (CLK_GATE_IP0, R/W, Address = 0xE010_0460)
CLK_GATE_IP0 Bit Description Gated Clock Name Initial State
CLK_CSIS [31] Gating all clocks for CSIS PCLK_CSIS
SCLK_CSIS 1
Reserved [30] Reserved Reserved 1
CLK_ROTATOR [29] Gating all clocks for ROTATOR
(0: mask, 1: pass) ACLK_ROTATOR 1
CLK_JPEG [28] Gating all clocks for JPEG
(0: mask, 1: pass) ACLK_JPEG 1
Reserved [27] Reserved Reserved 1
CLK_FIMC2 [26] Gating all clocks for FIMC2
(0: mask, 1: pass) ACLK_FIMC2
SCLK_FIMC_LCLK
SCLK_CAM0, 1
1
CLK_FIMC1 [25] Gating all clocks for FIMC1
(0: mask, 1: pass) ACLK_FIMC1
SCLK_CAM0, 1
1
CLK_FIMC0 [24] Gating all clocks for FIMC0
(0: mask, 1: pass) ACLK_FIMC0
SCLK_CAM0, 1
1
Reserved [23:17] Reserved Reserved 0x7F
CLK_MFC [16] Gating all clocks for MFC
(0: mask, 1: pass) PCLK_MFC
SCLK_MFC 1
Reserved [15:13] Reserved Reserved 0x7
CLK_G2D [12] Gating all clocks for G2D ACLK_G2D
SCLK_G2D 0x1