Samsung S5PC110, Manual

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S5PC110_UM 3 ONENAND CONTROLLER
3-15
3.6.3 ONENAND DEVICE INTERRUPT HANDLING
The OneNAND interface provides two mechanisms to check the INT pin status of the OneNAND devices, namely:
1. Polling the INTD (INT Done) bits of the OneNAND Interface Status (ONENAND_IF_STATUS) register
2. Interrupt-driven checking.
The OneNAND controller requires that the system software should follow the correct operation sequence to check
the INT pin status of the OneNAND device as shown in
Figure 3-6
and
Figure 3-7
.
Note that the OneNAND interface detects only the rising edge of the INT pin. Therefore, set the INT Polarity
(INTpol) bit of the System Configuration 1 register (device address offset: 0x1E442) of the OneNAND device to 1.
Figure 3-8
illustrates the timing diagram of the INT pin of the OneNAND device and related SFR signals. The
Figure 3-8
is described below:
•
T1: New command (ex. load, program or erase) is written to the OneNAND device Command register
•
T2: OneNAND device INT pin rising edge occurs
•
T3: The INTD[x] bit of the OneNAND Interface Status (ONENAND_IF_STATUS) register is set to 1.
•
T4: OSINTD[x] (OneNAND Status INT Done) bit of the Interrupt Controller OneNAND Status
(INTC_ONENAND_STATUS) register is set to 1 because OMINTD[x] (OneNAND Mask INT Done) bit of the
Interrupt Controller OneNAND Mask (INTC_ONENAND_MASK) is deasserted to 0. Simultaneously,
ARM_IRQ pin is asserted to high to generate an interrupt to the system
•
T5: The system software (ex. ISR (Interrupt Service Routine)) writes 1 to the INTC[x] bit of the OneNAND
Interface Command (ONENAND_IF_CMD) register to clear the INTD[x] bit of the OneNAND Interface Status
(ONENAND_IF_STATUS) register.
•
T6: The INTD[x] bit of the OneNAND Interface Status (ONENAND_IF_STATUS) register is cleared to 0. T7:
The system software (ex. ISR (Interrupt Service Routine)) writes 1 to the OCINTD[x] bit (OneNAND Clear INT
Done) of the Interrupt Controller OneNAND Clear (INTC_ONENAND_CLR) register to clear the OSINTD[x]
(OneNAND Status INT Done) bit of the Interrupt Controller OneNAND Status (INTC_ONENAND_STATUS)
register.
•
T8: The OSINTD[x] (OneNAND Status INT Done) bit of the Interrupt Controller OneNAND Status
(INTC_ONENAND_STATUS) register is cleared to 0. Simultaneously, ARM_IRQ pin is deasserted to low.