Samsung S5PC110, Manual

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S5PC110_UM 5 4BG3D
5-6
Table 5-1 Glossary of Terms
Term Description Term Description
VS Vertex Shader USSE Universal Scalable Shader Engine
PS Pixel Shader TF Texture Filter
OGL Open GL Application Programming
Interface MADD Mux/ Arb/ Demux/ Decompress –
Cache Management Module
DMS Data Master Selector MTE Macro Tiling Engine
PP Pixel Presenter ROP Collective Term For 2D Raster
Operations
VDM Vertex Data Master MRT Multiple Render Target
GPDM General Purpose Data Master TE Tiling Engine
PDM Pixel Data Master DPM Dynamic Parameter Management
ISP Image Synthesis Processor – Hidden
Surface Removal Engine TSP FPU Texturing and Shading Floating Point
Setup Unit
PDS Programmable Data Sequencer TAG Texture Address Generator
The SGX540 block is based on the PowerVR SGX core from Imagination Technologies.
5.1.5.1 Coarse Grain Scheduler
The Coarse Grain Scheduler (CGS) specifies the main system controller for the PowerVR SGX540 architecture. It
consists of two stages, namely, the Data Master Selector (DMS) and the Programmable Data Sequencer (PDS).
The DMS processes requests from data masters and determines which tasks will be executed based on the
resource requirements. The PDS then controls the loading and processing of data on the USSE.
5.1.5.2 Data Master Selector
The DMS processes request from the data masters and selects a task to be executed by the USSE and PDS by
tracking task resource requirements. The selected data master then has its resource allocated and source data
from the individual data master, which is passed to the PDS sequencing engine.
There are three data masters in the SGX540 core, namely:
•
Pixel Data Master (PDM)
•
Vertex Data Master (VDM)
•
General Purpose Data Master (GPDM)