List of Tables
Table Title
Page
Number Number
Table 1-1 32BPP (8:8:8:8) Palette Data Format .............................................................................................. 1-24
Table 1-2 25BPP (A: 8:8:8) Palette Data Format............................................................................................. 1-24
Table 1-3 19BPP (A: 6:6:6) Palette Data Format............................................................................................. 1-25
Table 1-4 16BPP (A: 5:5:5) Palette Data Format............................................................................................. 1-25
Table 1-5 Relation 16BPP Between VCLK and CLKVAL (TFT, Frequency of Video Clock Source=60MHz). 1-40
Table 1-6 i80 Output Mode............................................................................................................................... 1-44
Table 1-7 Timing Reference Code (XY Definition)........................................................................................... 1-55
Table 1-8 Parallel/ Serial RGB Data Pin Map (Not Used)................................................................................ 1-56
Table 2-1 Maximum Size.................................................................................................................................... 2-3
Table 2-2 ITU Camera Interface Signal Description .......................................................................................... 2-6
Table 2-3 Video Timing Reference Codes of ITU-656 8-Bit Format.................................................................. 2-8
Table 2-4 Sync Signal Timing Requirements..................................................................................................... 2-9
Table 2-5 DATA Order of YCbCr422 Align ...................................................................................................... 2-10
Table 2-6 Color Space Conversion Equations................................................................................................. 2-52
Table 2-7 FIFO Mode Image Format ............................................................................................................... 2-52
Table 3-1 Internal Primary FIFO List.................................................................................................................. 3-3
Table 3-2 I80 Interface Address Map............................................................................................................... 3-10
Table 3-4 MIPI-DPHY Interface Slave Signal .................................................................................................. 3-14
Table 3-5 PMS and Frequency Constraint....................................................................................................... 3-31
Table 3-6 AFC Code ........................................................................................................................................ 3-31
Table 3-7 Band Control Setting........................................................................................................................ 3-32
Table 4-1 Timing Diagram of Output Data ......................................................................................................... 4-3
Table 4-2 Data Order of YUV422 Alignment...................................................................................................... 4-4
Table 5-1 Glossary of Terms.............................................................................................................................. 5-6
Table 5-2 Power Mode Summary About G3D.................................................................................................. 5-10
Table 5-3 G3D Register Summary................................................................................................................... 5-11
Table 6-1 Payload in the Shared Memory........................................................................................................ 6-76
Table 7-1 Filter Coefficients of Anti-aliasing Filters for Luminance Y ................................................................ 7-8
Table 7-2 Filter Coefficients of Anti-aliasing Filters for Chrominance Cb .......................................................... 7-9
Table 7-3 Filter Coefficients of Anti-aliasing Filters for Chrominance Cr ........................................................... 7-9
Table 7-4 Over-sampling Filter Coefficients Configuration .............................................................................. 7-19
Table 7-5 Port Description of Video DAC......................................................................................................... 7-60
Table 9-1 Graphic Blending-factor Alpha in Case of Normal Mode................................................................. 9-18
Table 9-2 Graphic Blending Method ................................................................................................................ 9-18
Table 10-1 HDMI LINK Timing Generator Configuration Guide ........................................................................ 10-5
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...