Samsung S5PC110, Manual

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S5PC110_UM 1 0BDISPLAY CONTROLLER
1-40
1.3.8 VTIME CONTROLLER OPERATION
VTIME comprises of two blocks, namely:
•
VTIME_RGB_TV for RGB timing control
•
VTIME_I80 for indirect i80 interface timing control
1.3.8.1 RGB Interface Controller
VTIME generates control signals such as RGB_VSYNC, RGB_HSYNC, RGB_VDEN, and RGB_VCLK signal for
the RGB interface. These control signals are used while configuring the VIDTCON0/ 1/ 2 registers in the VSFR
register.
Based on the programmable configurations of display control registers in the VSFR, the VTIME module generates
programmable control signals that support different types of display devices.
The RGB_VSYNC signal causes the LCD line pointer to begin at the top of display. The configuration of both
HOZVAL field and LINEVAL registers control pulse generation of RGB_VSYNC and RGB_HSYNC. Based on the
following equations, the size of the LCD panel determines HOZVAL and LINEVAL:
•
HOZVAL = (Horizontal display size) -1
•
LINEVAL = (Vertical display size) -1
The CLKVAL field in VIDCON0 register controls the rate of RGB_VCLK signal.
Table 1-5
defines the relationship
of RGB_VCLK and CLKVAL. The minimum value of CLKVAL is 1.
−
RGB_VCLK (Hz) =HCLK/ (1), where CLKVAL >= 1
Table 1-5 Relation 16BPP Between VCLK and CLKVAL
(TFT, Frequency of Video Clock Source=60MHz)
CLKVAL 60MHz/X VCLK
2 60 MHz/3 20.0 MHz
3 60 MHz/4 15.0 MHz
: : :
63 60 MHz/64 937.5 kHz
VSYNC, VBPD, VFPD, HSYNC, HBPD, HFPD, HOZVAL, and LINEVAL configure RGB_HSYNC and
RGB_VSYNC signal. For more information, refer to Figure 9.1-20.
The frame rate is RGB_VSYNC signal frequency. The frame rate is related to the field of VSYNC, VBPD, VFPD,
LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL registers. Most LCD drivers need their own adequate
frame rate.
To calculate frame rate, use the following equation:
•
Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LI 1) + (VFPD+1) } x {(HSPW+1) + (HBPD +1)
+ (HFPD+1) + ( 1) } x { ( 1 ) / ( Frequency of Clock source ) } ]