Samsung S5PC110, Manual

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S5PC110_UM 1 DRAM CONTROLLER
1-26
CONCONTROL Bit Description R/W
Initial
State
drv_en [7] PHY Driving
0x0 = Disables
0x1 = Enables
During the high-Z state of the memory bidirectional pins, PHY
drives these pins with the zeros or pull down these pins for
preventing current leakage. Set PhyControl1.drv_type register
to select driving type.
R/W 0x0
ctc_rtr_gap_en [6] Read Cycle Gap for Two Different Chips
0x0 = Disables
0x1 = Enables
To prevent collision between reads from two different memory
devices, a one-cycle gap is required. Enable this register to
insert the gap automatically for continuous reads from two
different memory devices. R/W 0x1
aref_en [5] Auto Refresh Counter
0x0 = Disables
0x1 = Enables
Enable this to decrease the auto refresh counter by 1 at the
rising edge of the mclk.
R/W 0x0
out_of [4] Out of Order Scheduling
0x0 = Disables
0x1 = Enables
The embedded scheduler enables out-of order operation to
improve SDRAM utilization R/W 0x1
Reserved [3:0] Should be zero 0x0