S5PC110_UM
10 9BHIGH-DEFINITION MULTIMEDIA INTERFACE
10-65
10.3.3.59 HDCP Register Description (HDCP_KSV_LIST_CON, R/W, Address = 0xFA11_0664)
HDCP_KSV_LIST_CON
Bit
Description
Initial State
- [7:4]
Reserved
4b0000
Hdcp_Ksv_Write_Done [3] After writing KSV data into HDCP_KSV_LIST_X registers
and then writing “1” to this register, the HW processes the
written KSV value and clears this bit to “0”.
0 = Does not write
1 = Writes KSV data into HDCP_KSV_LIST_X registers
and then writes “1” to this register
0
Hdcp_Ksv_List_Empty
[2]
If the number of KSV list is zero, set this value to enable
the SHA-1 module calculate without KSV list.
0 = Not empty
1 = Empty
0
Hdcp_Ksv_End
[1]
Indicates that current KSV value in HDCP_KSV_LIST_X
registers is the last one.
0 = Not End
1 = End
0
Hdcp_Ksv_Read
[0]
After writing KSV data in HDCP_KSV_LIST_X registers,
the HDCP SHA-1 module keeps the KSV value in internal
buffer and sets this flag to ‘1’ for notifying it has been read.
After setting the flag to ‘1’, the SW clears to ‘0’ at the
same time when writing the HDCP_KSV_WRITE_DONE
bit for next KSV list value.
0 = Not Read
1 = Read
1
10.3.3.60 HDCP Register Description (HDCP_CTRL1, R/W, Address = 0xFA11_0680)
HDCP_CTRL1
Bit
Description
Initial State
- [7:4]
Reserved
4b0000
- [3]
Reserved
0
Timeout
[2]
Sets if Rx is the repeater and its KSV list is not ready until
five seconds.
0 = Not timeout
1 = Timeout (KSV Ready bit in the HDCP_BCAPS register
is not high until five seconds) and re-starts the 1st
authentication.
Refer to Figure 2-6 in the HDCP 1.3 specification.
0
CP_Desired [1]
Enables
HDCP.
0 = Not Desired
1 = Desired
0
- [0]
Reserved
0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...