Samsung S5PC110, Manual

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S5PC110_UM 1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
1-18
1.6.1.3 UART FIFO Control Register
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UFCON0, R/W, Address = 0xE290_0008
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UFCON1, R/W, Address = 0xE290_0408
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UFCON2, R/W, Address = 0xE290_0808
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UFCON3, R/W, Address = 0xE290_0C08
There are four UART FIFO control registers in the UART block, namely, UFCON0, UFCON1, UFCON2 and
UFCON3.
UFCONn Bit Description Initial State
Reserved [31:11] Reserved 0
Tx FIFO Trigger
Level [10:8] Determines the trigger level of Tx FIFO. If data count of Tx FIFO is
less than or equal to the trigger level, Tx interrupt occurs.
[Channel 0]
000 = 0 byte 001 = 32 bytes
010 = 64 bytes 011 = 96 bytes
100 = 128 bytes 101 = 160 bytes
110 = 192 bytes 111 = 224 bytes
[Channel 1]
000 = 0 byte 001 = 8 bytes
010 = 16 bytes 011 = 24 bytes
100 = 32 bytes 101 = 40 bytes
110 = 48 bytes 111 = 56 bytes
[Channel 2, 3]
000 = 0 byte 001 = 2 bytes
010 = 4 bytes 011 = 6 bytes
100 = 8 bytes 101 = 10 bytes
110 = 12 bytes 111 = 14 bytes
000
Reserved [7] Reserved 0
Rx FIFO Trigger
Level [6:4] Determines the trigger level of Rx FIFO. If data count of Rx FIFO
is more than or equal to the trigger level, Rx interrupt occurs.
[Channel 0]
000 = 32 byte 001 = 64 bytes
010 = 96 bytes 011 = 128 bytes
100 = 160 bytes 101 = 192 bytes
110 = 224 bytes 111 = 256 bytes
[Channel 1]
000 = 8 byte 001 = 16 bytes
010 = 24 bytes 011 = 32 bytes
100 = 40 bytes 101 = 48 bytes
110 = 56 bytes 111 = 64 bytes 000