Samsung S5PC110, Manual

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S5PC110_UM 13 12BG2D
13-14
13.5.2.5 AXI ID Mode Register (AXI_ID_MODE_REG, R/W, Address = 0xFA00_0014)
AXI_ID_MODE_REG Bit Description Initial State
Reserved [31:1] Reserved 0x0
AXI_RD_ID_MODE [0] This bit is for out of ordering of AXI Master Read. If this bit is
set, the several read port of this engine have each AXI RID
on only one AXI MASTER I/F
1 = Multiple ID (out of order)
0 = Single ID fixing on 4’b0 (In order) 0x0
13.5.2.6 Cache Control Register (CACHECTL_REG, R/W, Address = 0xFA00_0018)
CACHECTL_REG Bit Description Initial State
Reserved [31:3] Reserved 0x0
PATCACHE_CLEAR [2] Pattern cache clear (Automatically set to 0b after a cycle)
This bit is used to invalidate the contents of pattern cache.
0 = Default stages; pattern cache invalidation unchanged
1 = Pattern cache starts invalidation 0x0
SRCBUFFER_CLEAR [1] Source buffer clear (Automatically set to 0b after a cycle)
This bit is used to invalidate the contents of source buffer.
0 = Default stages; source buffer invalidation unchanged
1 = Source buffer starts invalidation 0x0
MASKBUFFER_CLEAR [0] Mask buffer clear (Automatically set to 0b after a cycle)
This bit is used to invalidate the contents of mask buffer.
0 = Default stages; Mask buffer invalidation unchanged
1 = Mask buffer starts invalidation
0x0