Samsung S5PC110, Manual

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S5PC110_UM 1 DRAM CONTROLLER
1-45
1.4.1.17 Counter Status Register for the Auto Refresh (ArefStatus, R, Address=0xF000_0050,
0xF140_0050)
AREFSTATUS Bit Description R/W
Initial
State
Reserved [31:16] Should be zero 0x0
aref_cnt [15:0] Current Value of Auto Refresh Counter
Shows the current value of all bank auto refresh counter.
This is updated if a new t_refi is programmed into the
TimingAref register and decreases by 1 at the rising edge of
mclk.
An all bank auto refresh command is issued to memory device
and this counter is reloaded with TimingAref.t_ref if this
becomes zero. R 0xFFFF
1.4.1.18 Memory Mode Registers Status Register (MrStatus, Read Only, Address = 0xF000_0054,
0xF140_0054)
MRSTATUS Bit Description R/W
Initial
State
Reserved [31:8] Should be zero 0x0
mr_status [7:0] Mode Registers Status R 0x0
1.4.1.19 PHY Test Register 0 (PhyTest0, R/W, Address = 0xF000_0058, 0xF140_0058)
PHYTEST0 Bit Description R/W
Initial
State
ctrl_fb_cnt4 [31:24] Count Value for Control Channel R 0x0
Reserved [23:21] Should be zero 0x0
ctrl_fb_oky [20:16] ctrl_fb_okay[4] : Error status for control,
ctrl_fb_okay[3:0] : Error status for data R 0x0
Reserved [15:13] Should be zero 0x0
ctrl_fb_err [12:8] ctrl_fb_err[4] : Error for control,
ctrl_fb_err[3:0] : Error for data R 0x0
Reserved [7:5] Should be zero 0x0
ctrl_fb_start [4:0] ctrl_fb_start[4] : Start for control,
ctrl_fb_start[3:0] : Start for data R/W 0x0