Samsung S5PC110, Manual

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S5PC110_UM 5 USB2.0 HS OTG
5-50
GLPMCFG Bit Description R/W Initial State
the timer TL1TokenRetry. has expired. To stop the PHY
clock, the application must set the Port Clock Stop bit, which
asserts the PHY’s Suspend input pin. The application must
rely on SlpSts and not ACK in CoreL1Res to confirm
transition into sleep. The core comes out of sleep:
•
When there is any activity on the USB line_state
•
When the application writes to the Remote Wakeup
Signaling bit in the Device Control register
(DCTL.RmtWkUpSig) or when the application resets or soft-
disconnects the device.
Host Mode: The handshake response received from the
local device for LPM transaction
•
11: ACK
•
10: NYET
•
01: STALL
•
00: ERROR (No handshake response)
CoreL1Res [14:13]
Device Mode: The core’s response to the received LPM
transaction is reflected in these two bits.
R 2'b0
HIRD_Thres [12:8] Host Mode: The core asserts L1SuspendM to put the PHY
into Deep Low-Power mode in L1 when HIRD_Thres[4] is
set to 1’b1. HIRD_Thres[3:0] specifies the time for which
resume signaling is to be reflected by the host
(TL1HubDrvResume2) on the USB when it detects device-
initiated resume. HIRD_Thres must not be programmed with
a value greater than 4’b1100 in Host mode, because this
exceeds maximum TL1HubDrvResume2. Host mode
resume
Sl. No HIRD_Thres[3:0] signaling time (
μ
s)
1 4’b0000 60
2 4’b0001 135
3 4’b0010 210
4 4’b0011 285
5 4’b0100 360
6 4’b0101 435
7 4’b0110 510
8 4’b0111 585
9 4’b1000 660
10 4’b1001 735
11 4’b1010 810
12 4’b1011 885
13 4’b1100 960
14 4’b1101 invalid
15 4’b1110 invalid
16 4’b1111 invalid
R/W 5'b0