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S5PC110_UM

3 2BMIPI DSIM

3-25

3.3.1.12 Interrupt Source Register (DSIM_INTSRC, R/W, Address = 0xFA50_002C)

This register identifies interrupt sources.
Internal block error, data transmit interrupt, inter-layer (D_PHY) error, etc.
The bits are set even if they are masked off by DSIM_INTMSK_REG.
Write ‘1’ to clear the Interrupt.

DSIM_INTSRC

Bit

Description

Initial State

PllStable [31]

Indicates

that D-phy PLL is stable.

0

SwRstRelease

[30]

Releases the software reset.

0

SFRFifoEmpty [29]

Specifies

the SFR payload FIFO empty.

0

SyncOverride

[28]

Indicates that other DSI command transfer have overridden
sync timing.

0

Reserved [27:26]

Reserved

-

BusTurnOver

[25]

Indicates when bus grant turns over from DSI slave to DSI
master.

0

FrameDone

[24]

Indicates when MIPI DSIM transfers the whole image
frame.
Note: If Hsync is not received during two line times, internal
timer is timed out and this bit is flagged.

0

Reserved [23:22]

Reserved

-

LpdrTout

[21]

Specifies the LP Rx timeout. See time out register (0x10).

0

TaTout

[20]

Turns around Acknowledge Timeout. See time out register
(0x10).

0

Reserved [19]

Reserved

-

RxDatDone [18]

Completes

receiving

data.

0

RxTE

[17]

Receives TE Rx trigger.

0

RxAck

[16]

Receives ACK Rx trigger.

0

ErrRxECC

[15]

Specifies the ECC multi bit error in LPDR.

0

ErrRxCRC [14]

Specifies

the CRC error in LPDR.

0

ErrEsc3

[13]

Specifies the escape mode entry error lane 3. For more
information, refer to standard D-PHY specification.

0

ErrEsc2

[12]

Specifies the escape mode entry error lane 2. For more
information, refer to standard D-PHY specification.

0

ErrEsc1

[11]

Specifies the escape mode entry error lane 1. For more
information, refer to standard D-PHY specification.

0

ErrEsc0

[10]

Specifies the escape mode entry error lane 0. For more
information, refer to standard D-PHY specification.

0

ErrSync2

[9]

Specifies the LPDT sync error lane 3. For more
information, refer to standard D-PHY specification.

0

ErrSync2

[8]

Specifies the LPDT Sync Error lane2. For more
information, refer to standard D-PHY specification.

0

ErrSync1

[7]

Specifies the LPDT Sync Error lane1. For more
information, refer to standard D-PHY specification.

0

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Summary of Contents for S5PC110

Page 1: ...Rev 0 0 Jan 2009 S5PC110 RISC Microprocessor Revision 1 00 February 2010 U Us se er r s s M Ma an nu ua al l 2010 Samsung Electronics Co Ltd All rights reserved ...

Page 2: ... Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such uni...

Page 3: ...Rev 0 0 Jan 2009 Revision History Revision No Date Description Author s 0 00 February 27 2010 Initial draft S H Yoon ...

Page 4: ...Section 1 OVERVIEW ...

Page 5: ...2 Memory Subsystem 1 5 1 3 3 Multimedia 1 6 1 3 4 Audio Subsystem 1 9 1 3 5 Security Subsystem 1 9 1 3 6 Connectivity 1 10 1 3 7 System Peripheral 1 13 1 4 Conventions 1 15 1 4 1 Register R W Conventions 1 15 1 4 2 Register Value Conventions 1 15 2 Memory Map 2 1 2 1 Memory Address Map 2 1 2 1 1 Device Specific Address Space 2 2 2 1 2 Special Function Register Map 2 4 ...

Page 6: ...List of Figures Figure Title Page Number Number Figure 1 1 S5PC110 Block Diagram 1 2 Figure 2 1 Address Map 2 1 Figure 2 2 Internal Memory Address Map 2 3 ...

Page 7: ...I for NTSC and PAL mode S5PC110 has an interface to external memory that is capable of sustaining heavy memory bandwidths required in high end communication services The memory system has Flash ROM external memory ports for parallel access and DRAM port to meet high bandwidths DRAM controller supports LPDDR1 mobile DDR DDR2 or LPDDR2 Flash ROM port supports NAND Flash NOR Flash OneNAND SRAM and RO...

Page 8: ...Codec H 263 H 264 MPEG4 Decoder MPEG2 VC 1 Divx 2 D VG 3 D Graphics engine NTSC PAL TV out HDMI JPEG Codec SRAM ROM PLL x4 Timer with PWM 4ch Watchdog Timer DMA 24ch Keypad 14x8 TS ADC 12bit 10ch Audio IF IIS x3 PCM x3 1 2 Power Management SPDIF AC97 Storage IF HSMMC SD x4 ATA Connectivity USB Host 2 0 OTG2 0 UART x4 IIC x3 HS SPI x2 GPIO Clock gating Power gating Dynamic Voltage Frequency Scaling...

Page 9: ... Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for un scaled resolution Multi Format Codec provides encoding and decoding of MPEG 4 H 263 H 264 up to 720p 30fps and decoding of MPEG 2 VC1 Divx video up to 720p 30 fps JPEG codec supports up to 80 Mpixels s 3D Graphics Acceleration with Programmable Shader up to 20M triangles s and 1000 Mpixels s 2D Graphics Acceler...

Page 10: ...essor based on ARMv7 architecture With the ability to scale in speed from 600 MHz to 1 GHz or more the ARM CortexTM A8 processor meets the requirements of power optimized mobile devices which require operation in less than 300mW and performance optimized consumer applications require 2000 Dhrystone MIPS Supports first superscalar processor featuring technology from ARM for enhanced code density an...

Page 11: ...dress range support 16 bit o Supports byte and half word access o Supports 2 KB page mode for OneNAND and 4 KB page mode for Flex OneNAND o Supports dedicated DMA NAND Interface o Supports industry standard NAND interface o x8 data bus LPDDR1 Interface o x32 data bus with 400 Mbps pin Double Data Rate DDR o 1 8V interface voltage o Density support up to 4 Gb per port 2CS DDR2 Interface o x32 data ...

Page 12: ...ing supports Baseline Main High Profile Level 4 0 except Flexible Macro block Ordering FMO Arbitrary Slice Ordering ASO and Redundant Slice RS o Encoding supports Baseline Main High Profile except FMO ASO and RS ITU T H 263 Profile level 3 o Decoding supports Profile3 restricted up to SD resolution 30 fps H 263 Annexes to be supported Annex I Advanced Intra Coding Annex J De blocking in loop filte...

Page 13: ...versal Scalable Shader Engine multi threaded engine incorporating Pixel and Vertex Shader functionality Industry standard API support OGL ES 1 1 and 2 0 and OpenVG 1 0 Fine grained task switching load balancing and power management Advanced geometry DMA driven operation for minimum CPU interaction Programmable high quality image anti aliasing Fully virtualized memory addressing for functioning of ...

Page 14: ...ositioning within display area 1 16 pixel resolution Pan and Scan modes Flexible post video processing o Color saturation Brightness Contrast enhancement Edge enhancement o Color space conversion between BT 601 and BT 709 Video input source size up to 1920x1080 Video Mixer The Video Mixer supports Overlapping and blending input video and graphic layers 480i p 576i p 720p and 1080i p display size F...

Page 15: ...CURITY SUBSYSTEM The key features of security subsystem include On chip secure boot ROM 64 KB secure boot ROM for secure boot On chip secure RAM 128 KB secure RAM for security function Hardware Crypto Accelerator Securely integrated DES TDES AES SHA 1 PRNG and PKA Access control Security Domain Manager with the ARM TrustZone Hardware Enables enhanced secure platform for separate secure non secure ...

Page 16: ...nterface Three I2S bus for audio codec interface with DMA based operation Serial 8 16 24 bit per channel data transfers Supports I2S MSB justified and LSB justified data format Supports PCM 5 1 channel Various bit clock frequency and codec clock frequency support o 16 24 32 48 fs of bit clock frequency o 256 384 512 768 fs of codec clock Supports one port for 5 1 channel I2S in Audio Subsystem and...

Page 17: ...the OTG Revision 1 0a supplement to the USB 2 0 Supports high speed up to 480 Mbps On chip USB transceiver USB Host 2 0 Complies with the USB Host 2 0 Supports high speed up to 480 Mbps On chip USB transceiver HS MMC SDIO Interface Multimedia Card Protocol version 4 0 compatible HS MMC SD Memory Card Protocol version 2 0 compatible DMA based or Interrupt based operation 128 word FIFO for Tx Rx Fou...

Page 18: ...ort 3xI2C PWM IEM GPE0 1 13 in out port Camera Interface GPF0 1 2 3 30 in out port LCD Interface GPG0 1 2 3 28 in out port 4xMMC channel Channel 0 and 2 support 4 bit and 8 bit modes but channel 1 and 3 support only 4 bit mode GPH0 1 2 3 32 in out port Key pad External Wake up up to 32 bit HDMI GPI Low power I2S PCM GPJ0 1 2 3 4 35 in out port Modem IF CAMIF CFCON KEYPAD SROM ADDR 22 16 MP0_1 2 3 ...

Page 19: ...with PWM Programmable duty cycle frequency and polarity Dead zone generation Supports external clock source System timer Accurate timer provides exact 1ms tick at any power mode except sleep Interrupt interval can be changed without stopping reference tick timer DMA Micro code programming based DMA The specific instruction set provides flexibility to program DMA transfers Supports linked list DMA ...

Page 20: ...lock gating control for components Various low power modes are available such as Idle Stop Deep Stop Deep Idle and Sleep modes Wake up sources in sleep mode are external interrupts RTC alarm Tick timer and the key interface Stop and Deep Stop mode s wake up sources are MMC Touch screen interface system timer and entire wake up sources of Sleep mode Deep Idle mode s wake up sources are 5 1ch I2S an...

Page 21: ...y writing 1 b0 R WC Read Write to clear The application has permission to read and writes in the Register field The application clears this field by writing 1 b1 A register write of 1 b0 has no effect on this field R WS Read Write to set The application has permission to read and writes in the Register field The application sets this field by writing 1 b1 A register write of 1 b0 has no effect on ...

Page 22: ...M 0 x 0000 _ 0000 0 x 4000 _ 0000 0 x 3 FFF_ FFFF 0 x 8000 _ 0000 0 x 7 FFF_ FFFF 0 xC 000 _ 0000 0 xBFFF _ FFFF 0 xFFFF _ FFFF 0 x 2000 _ 0000 0 x1 FFF _ FFFF 0 x 6000 _ 0000 0 x 5 FFF_ FFFF 0 xA 000 _ 0000 0 x9 FFF _ FFFF 0 xE 000 _ 0000 0 xDFFF _ FFFF 0 x 9000 _ 0000 0 x 8 FFF_ FFFF 0 xB 000 _ 0000 0 xAFFF _ FFFF 0 xD 000 _ 0000 0 xCFFF _ FFFF Reserved Reserved Low Power Audio SRAM SFRS DRAM 1 ...

Page 23: ...0000 0x8FFF_FFFF 128MB SROM Bank 1 0x9000_0000 0x97FF_FFFF 128MB SROM Bank 2 0x9800_0000 0x9FFF_FFFF 128MB SROM Bank 3 0xA000_0000 0xA7FF_FFFF 128MB SROM Bank 4 0xA800_0000 0xAFFF_FFFF 128MB SROM Bank 5 0xB000_0000 0xBFFF_FFFF 256MB OneNAND NAND Controller and SFR 0xC000_0000 0xCFFF_FFFF 256MB MP3_SRAM output buffer 0xD000_0000 0xD000_FFFF 64KB IROM 0xD001_0000 0xD001_FFFF 96KB Reserved 0xD002_000...

Page 24: ...igure 2 2 Internal Memory Address Map NOTE TZPCR0SIZE 5 0 TZPC0 in TZPC SFR 4KByte chunks Recommended value 6 b00_0000 6 b10_0000 if TZPCR0SIZE 5 TZPC0 1 b1 the full address range in iSRAM is configured as secure if TZPCR0SIZE TZPC0 6 b00_0000 there is non secure region in iSRAM 0kB if TZPCR0SIZE TZPC0 6 b00_0001 the minimum secure region size is 4kB if TZPCR0SIZE TZPC0 6 b01_0000 the 64KB from iS...

Page 25: ...EY 0xE0F0_0000 0xE0FF_FFFF ASYNC_AUDIO_PSYS 0xE110_0000 0xE11F_FFFF SPDIF 0xE120_0000 0xE12F_FFFF PCM1 0xE130_0000 0xE13F_FFFF SPI0 0xE140_0000 0xE14F_FFFF SPI1 0xE160_0000 0xE16F_FFFF KEYIF 0xE170_0000 0xE17F_FFFF TSADC 0xE180_0000 0xE18F_FFFF I2C0 general 0xE1A0_0000 0xE1AF_FFFF I2C2 PMIC 0xE1B0_0000 0xE1BF_FFFF HDMI_CEC 0xE1C0_0000 0xE1CF_FFFF TZPC3 0xE1D0_0000 0xE1DF_FFFF AXI_GSYS 0xE1F0_0000 ...

Page 26: ...AUDIO_SS ASS_IBUF0 0xEEB0_0000 0xEEBF_FFFF AUDIO_SS ASS_IBUF1 0xEEC0_0000 0xEECF_FFFF AUDIO_SS ASS_OBUF0 0xEED0_0000 0xEEDF_FFFF AUDIO_SS ASS_OBUF1 0xEEE0_0000 0xEEEF_FFFF AUDIO_SS ASS_APB 0xEEF0_0000 0xEEFF_FFFF AUDIO_SS ASS_ODO 0xF000_0000 0xF00F_FFFF DMC0_SFR 0xF100_0000 0xF10F_FFFF AXI_MSYS 0xF110_0000 0xF11F_FFFF AXI_MSFR 0xF120_0000 0xF12F_FFFF AXI_VSYS 0xF140_0000 0xF14F_FFFF DMC1_SFR 0xF15...

Page 27: ... 0xF920_0000 0xF92F_FFFF MIXER 0xFA00_0000 0xFA0F_FFFF G2D 0xFA10_0000 0xFA1F_FFFF HDMI_LINK 0xFA20_0000 0xFA2F_FFFF SMDMA 0xFA30_0000 0xFA3F_FFFF ROT 0xFA40_0000 0xFA4F_FFFF AXI_LSYS 0xFA50_0000 0xFA5F_FFFF DSIM 0xFA60_0000 0xFA6F_FFFF CSIS 0xFA70_0000 0xFA7F_FFFF AXI_DSYS 0xFA80_0000 0xFA8F_FFFF AXI_DSFR 0xFA90_0000 0xFA9F_FFFF I2C_HDMI_PHY 0xFAA0_0000 0xFAAF_FFFF AXI_TSYS 0xFAB0_0000 0xFABF_FFF...

Page 28: ...Section 2 SYSTEM ...

Page 29: ...p GPF1 Control Register 2 64 2 2 13 Port Group GPF2 Control Register 2 67 2 2 14 Port Group GPF3 Control Register 2 70 2 2 15 Port Group GPG0 Control Register 2 72 2 2 16 Port Group GPG1 Control Register 2 74 2 2 17 Port Group GPG2 Control Register 2 76 2 2 18 Port Group GPG3 Control Register 2 78 2 2 19 Port Group GPI Control Register 2 80 2 2 20 Port Group GPJ0 Control Register 2 82 2 2 21 Port ...

Page 30: ...rol Registers 2 125 2 2 56 Port Group GPH0 Control Register 2 234 2 2 57 Port Group GPH1 Control Register 2 236 2 2 58 Port Group GPH2 Control Register 2 238 2 2 59 Port Group GPH3 Control Register 2 240 2 2 60 External Interrupt Control Registers 2 242 2 2 61 Extern Pin Configuration Registers in Power down Mode 2 262 3 Clock Controller 3 1 3 1 Clock Domains 3 1 3 2 Clock Declaration 3 2 3 2 1 Cl...

Page 31: ...errupts 4 25 4 6 2 RTC Alarm 4 25 4 6 3 System Timer 4 25 4 7 External Power Control 4 26 4 7 1 USB OTG PHY 4 27 4 7 2 HDMI PHY 4 27 4 7 3 MIPI D PHY 4 28 4 7 4 PLL 4 28 4 7 5 DAC 4 29 4 7 6 ADC I O 4 30 4 7 7 POR 4 30 4 8 Internal memory control 4 31 4 8 1 SRAM 4 31 4 8 2 ROM 4 32 4 9 Reset Control 4 33 4 9 1 Reset Types 4 33 4 9 2 Hardware Reset 4 33 4 10 Register Description 4 38 4 10 1 Registe...

Page 32: ...ce 5 17 5 4 I O Description 5 18 5 5 Register Description 5 19 5 5 1 Register Map 5 19 5 5 2 IEC Related Registers 5 22 5 5 3 APC1 Related Registers 5 34 6 BOOTING SEQUENCE 6 1 6 1 Overview of Booting Sequence 6 1 6 2 Scenario Description 6 3 6 2 1 Reset Status 6 3 6 2 2 Booting Sequence Example 6 4 6 2 3 Fixed PLL and Clock Setting 6 6 6 2 4 OM Pin Configuration 6 7 6 2 5 Secure Booting 6 9 ...

Page 33: ...ure 4 3 Cortex A8 Power Mode Transition Diagram 4 22 Figure 4 4 Power ON OFF Reset Sequence 4 34 Figure 5 1 Intelligent Energy Manager Solution 5 1 Figure 5 2 IEM Block Diagram 5 3 Figure 5 3 PowerWise Performance Tracking and Voltage Adjustment 5 6 Figure 5 4 IEM Closed Loop Voltage Generation Flow in HPM and APC1 5 14 Figure 5 5 IEM Closed Loop Control Flow in APC1 HPM Delay 5 15 Figure 5 6 HPM ...

Page 34: ...ving Mode Entering Exiting Condition 4 19 Table 4 5 Cortex A8 Power Control 4 23 Table 4 6 Relationship Among Power Mode Wakeup Sources 4 25 Table 4 7 S5PC110 External Power Control 4 26 Table 4 8 The Status of MPLL and SYSCLK After Wake Up 4 29 Table 4 9 S5PC110 Internal Memory Control 4 31 Table 4 10 Register Initialization Due to Various Resets 4 37 Table 5 1 Example Divider Values for 1600MHz ...

Page 35: ... software SW that sends and receives APB interface signals to the bus system Chip ID is placed on the first address of the SFR region 0xE0000_0000 The product ID register supplies product ID revision number and package information Except product ID electrical fuse ROM e from provides all information bits ...

Page 36: ...Address 0xE000_0000 PRO_ID Bit Description Initial State Product ID 31 12 Product ID The product ID allocated to S5PC110 is 0x43110 0x43110 Reserved 11 8 Reserved bits Rev Number 7 4 Revision Number 0x2 Device ID 3 0 Device ID 0x1 NOTE 1 PRO_ID register 7 0 depends on the e fuse ROM value As power on sequence is progressing the e fuse ROM values are loaded to the registers It can read the loaded c...

Page 37: ...F GPF0 1 2 3 30 in out port LCD I F GPG0 1 2 3 28 in out port 4xMMC channel Channel 0 and 2 support 4 bit and 8 bit mode but channel 1 and channel 3 support only 4 bit mode GPH0 1 2 3 32 in out port Key pad External Wake up up to 32 bit GPH groups are in Alive region GPI Low Power I2S PCM in out port is not used PDN configuration for power down is controlled by AUDIO_SS PDN Register GPJ0 1 2 3 4 3...

Page 38: ...de except GPH0 GPH1 GPH2 and GPH3 GPH pins are alive pads 2 1 2 INPUT OUTPUT CONFIGURATION Configurable Input Output I O is subdivided into Type A and Type B 2 1 3 S5PC110 INPUT OUTPUT TYPES I O Types I O Group Description A GPA0 GPA1 GPC0 GPC1 GPD0 GPD1 GPE0 GPE1 GPF0 GPF1 GPF2 GPF3 GPH0 GPH1 GPH2 GPH3 GPI GPJ0 GPJ1 GPJ2 GPJ3 GPJ4 Normal I O 3 3V I O B GPB GPG0 GPG1 GPG2 GPG3 MP0 Fast I O 3 3V I ...

Page 39: ... 26 12 mA 37 15 mA DS0 1 DS1 0 Isource 17 06 mA 26 14 mA 37 53 mA Isink 30 38 mA 48 52 mA 69 01 mA 3 3V IO DS0 1 DS1 1 Isource 28 44 mA 43 56 mA 62 55 mA VDD 2 5V 0 2V Currents Parameter Driver Type Worst VDD 2 30V T 125 Process Slow Isink at VDD 0 2V Isource at VDD 0 8V Typical VDD 2 50V T 25 Process Nominal Isink at VDD 0 2V Isource at VDD 0 8V Best VDD 2 70V T 40 Process Fast Isink at VDD 0 2V ...

Page 40: ...IO DS0 1 DS1 1 Isource 9 091 mA 15 34 mA 24 32 mA NOTE 1 Isink is measured at 0 2 x VDD NOTE 2 Isource is measured at 0 8 X VDD Mesured point is different from measurement spec of 65nm IO Driver 2 1 4 2 Type B IO Driver Strength VDD 3 3V 0 3V Currents Parameter Driver Type Worst VDD 3 00V T 125 Process Slow Isink at VDD 0 2V Isource at VDD 0 8V Typical VDD 3 30V T 25 Process Nominal Isink at VDD 0...

Page 41: ...7mA 3 3V IO DS0 1 DS1 1 Isource 17 19mA 27 32mA 40 75mA VDD 1 8V 0 15V Currents Parameter Driver Type Worst VDD 1 65V T 12 Process Slow Isink at VDD 0 2V Isource at VDD 0 8V Typical VDD 1 80V T 25 Process Nominal Isink at VDD 0 2V Isource at VDD 0 8V Best VDD 1 95V T 40 Process Fast Isink at VDD 0 2V Isource at VDD 0 8V Isink 0 99mA 1 73mA 2 74mA DS0 0 DS1 0 Isource 0 91mA 1 53mA 2 41mA Isink 3 96...

Page 42: ... 19 59mA 29 24mA 1 8V MDDR IO DS0 1 DS1 1 Isource 11 32mA 18 70mA 28 90mA VDD 1 2V VDDx10 Currents Parameter Driver Type Worst VDD 1 045V T 125 Process Slow Isink at VDD 0 2V Isource at VDD 0 8V Typical VDD 1 1V T 25 Process Nominal Isink at VDD 0 2V Isource at VDD 0 8V Best VDD 1 155V T 25 Process Fast Isink at VDD 0 2V Isource at VDD 0 8V Isink 1 10mA 2 22mA 3 95mA DS0 0 DS1 0 Isource 1 05mA 1 9...

Page 43: ...supplied on sleep mode but in off part it is not the same Therefore the registers in alive part keep their values during sleep mode Alive Part Pad control Interrupt Controller Pad control APB Bus Interrupt Controller Wake up controller Register File Mux control APB Interface External Interrupt Control Async Interface Register File Mux control External Interrupt Control Off Part Figure 2 1 GPIO Blo...

Page 44: ...e power down mode is released by S W ENABLE_UART_IO bit of OTHERS register at PMU A3 Control at power down mode is possible power down mode is released by S W ENABLE_MMC_IO bit of OTHERS register at PMU A4 Control at power down mode is possible power down mode is released by H W automatically A5 Control at power down mode is possible power down mode is released by H W ENABLE_CF_IO bit of OTHERS re...

Page 45: ...MISO GPI PD I L A1 PBIDIRF_G XspiMOSI 0 GPB 3 SPI_0_MOSI GPI PD I L A1 PBIDIRF_G XspiCLK 1 GPB 4 SPI_1_CLK GPI PD I L A1 PBIDIRF_G XspiCSn 1 GPB 5 SPI_1_nSS GPI PD I L A1 PBIDIRF_G XspiMISO 1 GPB 6 SPI_1_MISO GPI PD I L A1 PBIDIRF_G XspiMOSI 1 GPB 7 SPI_1_MOSI GPI PD I L A1 PBIDIRF_G Xi2s1SCLK GPC0 0 I2S_1_SCLK PCM_1_SCLK AC97BITCLK GPI PD I L A1 PBIDIRSE_G Xi2s1CDCLK GPC0 1 I2S_1_CDCLK PCM_1_EXTC...

Page 46: ... 7 GPE1 2 CAM_A_DATA 7 GPI PD I L A1 PBIDIRSE_G XciCLKenb GPE1 3 CAM_A_CLKOUT GPI PD I L A1 PBIDIRSE_G XciFIELD GPE1 4 CAM_A_FIELD GPI PD I L A1 PBIDIRSE_G XvHSYNC GPF0 0 LCD_HSYNC SYS_CS0 VEN_HSYNC GPI PD I L A1 PBIDIRSE_G XvVSYNC GPF0 1 LCD_VSYNC SYS_CS1 VEN_VSYNC GPI PD I L A1 PBIDIRSE_G XvVDEN GPF0 2 LCD_VDEN SYS_RS VEN_HREF GPI PD I L A1 PBIDIRSE_G XvVCLK GPF0 3 LCD_VCLK SYS_WE V601_CLK GPI P...

Page 47: ...PBIDIRSE_G Xmmc0CLK GPG0 0 SD_0_CLK GPI PD I L A3 PBIDIRF_G Xmmc0CMD GPG0 1 SD_0_CMD GPI PD I L A3 PBIDIRF_G Xmmc0CDn GPG0 2 SD_0_CDn GPI PD I L A3 PBIDIRF_G Xmmc0DATA 0 GPG0 3 SD_0_DATA 0 GPI PD I L A3 PBIDIRF_G Xmmc0DATA 1 GPG0 4 SD_0_DATA 1 GPI PD I L A3 PBIDIRF_G Xmmc0DATA 2 GPG0 5 SD_0_DATA 2 GPI PD I L A3 PBIDIRF_G Xmmc0DATA 3 GPG0 6 SD_0_DATA 3 GPI PD I L A3 PBIDIRF_G Xmmc1CLK GPG1 0 SD_1_C...

Page 48: ... GPI PD I L B1 PBIDIR_ALV XEINT 9 GPH1 1 GPI PD I L B1 PBIDIR_ALV XEINT 10 GPH1 2 GPI PD I L B1 PBIDIR_ALV XEINT 11 GPH1 3 GPI PD I L B1 PBIDIR_ALV XEINT 12 GPH1 4 HDMI_CEC GPI PD I L B1 PBIDIR_ALV XEINT 13 GPH1 5 HDMI_HPD GPI PD I L B1 PBIDIR_ALV XEINT 14 GPH1 6 GPI PD I L B1 PBIDIR_ALV XEINT 15 GPH1 7 GPI PD I L B1 PBIDIR_ALV XEINT 16 GPH2 0 KP_COL 0 GPI PD I L B1 PBIDIR_ALV XEINT 17 GPH2 1 KP_C...

Page 49: ...G XmsmADDR 5 GPJ0 5 MSM_ADDR 5 CAM_B_DATA 5 CF_DMARQ TS_DATA GPI PD I L A5 PBIDIRSE_G XmsmADDR 6 GPJ0 6 MSM_ADDR 6 CAM_B_DATA 6 CF_DRESETN TS_ERRO R GPI PD I L A5 PBIDIRSE_G XmsmADDR 7 GPJ0 7 MSM_ADDR 7 CAM_B_DATA 7 CF_DMACKN MHL_D0 GPI PD I L A5 PBIDIRSE_G XmsmADDR 8 GPJ1 0 MSM_ADDR 8 CAM_B_PCLK SROM_ADDR_1 6to22 0 MHL_D1 GPI PD I L A5 PBIDIRSE_G XmsmADDR 9 GPJ1 1 MSM_ADDR 9 CAM_B_VSYNC SROM_ADDR...

Page 50: ...0 MSM_CSn KP_ROW 9 CF_CSn 0 MHL_D23 GPI PD I L A5 PBIDIRSE_G XmsmWEn GPJ4 1 MSM_WEn KP_ROW 10 CF_CSn 1 MHL_HSY NC GPI PD I L A5 PBIDIRSE_G XmsmRn GPJ4 2 MSM_Rn KP_ROW 11 CF_IORN MHL_IDC K GPI PD I L A5 PBIDIRSE_G XmsmIRQn GPJ4 3 MSM_IRQn KP_ROW 12 CF_IOWN MHL_VSY NC GPI PD I L A5 PBIDIRSE_G XmsmADVN GPJ4 4 MSM_ADVN KP_ROW 13 SROM_ADDR_1 6to22 6 MHL_DE GPI PD I L A5 PBIDIRSE_G Xm0CSn 0 MP0_1 0 SROM...

Page 51: ...BIDIRF_G Xm0ADDR 8 MP0_5 0 EBI_ADDR 8 Func0 O L A4 PBIDIRF_G Xm0ADDR 9 MP0_5 1 EBI_ADDR 9 Func0 O L A4 PBIDIRF_G Xm0ADDR 10 MP0_5 2 EBI_ADDR 10 Func0 O L A4 PBIDIRF_G Xm0ADDR 11 MP0_5 3 EBI_ADDR 11 Func0 O L A4 PBIDIRF_G Xm0ADDR 12 MP0_5 4 EBI_ADDR 12 Func0 O L A4 PBIDIRF_G Xm0ADDR 13 MP0_5 5 EBI_ADDR 13 Func0 O L A4 PBIDIRF_G Xm0ADDR 14 MP0_5 6 EBI_ADDR 14 Func0 O L A4 PBIDIRF_G Xm0ADDR 15 MP0_5 ...

Page 52: ...DIR_MDDR Xm1ADDR 11 MP1_1 3 LD0_ADDR 11 Func0 O L A4 PBIDIR_MDDR Xm1ADDR 12 MP1_1 4 LD0_ADDR 12 Func0 O L A4 PBIDIR_MDDR Xm1ADDR 13 MP1_1 5 LD0_ADDR 13 Func0 O L A4 PBIDIR_MDDR Xm1ADDR 14 MP1_1 6 LD0_ADDR 14 Func0 O L A4 PBIDIR_MDDR Xm1ADDR 15 MP1_1 7 LD0_ADDR 15 Func0 O L A4 PBIDIR_MDDR Xm1DATA 0 MP1_2 0 LD0_DATA 0 Func0 I A4 PBIDIR_MDDR Xm1DATA 1 MP1_2 1 LD0_DATA 1 Func0 I A4 PBIDIR_MDDR Xm1DATA...

Page 53: ...ATA 30 Func0 I A4 PBIDIR_MDDR Xm1DATA 31 MP1_5 7 LD0_DATA 31 Func0 I A4 PBIDIR_MDDR Xm1DQS 0 MP1_6 0 LD0_DQS 0 Func0 I A4 PBIDIR_MDDR Xm1DQS 1 MP1_6 1 LD0_DQS 1 Func0 I A4 PBIDIR_MDDR Xm1DQS 2 MP1_6 2 LD0_DQS 2 Func0 I A4 PBIDIR_MDDR Xm1DQS 3 MP1_6 3 LD0_DQS 3 Func0 I A4 PBIDIR_MDDR Xm1DQSn 0 MP1_6 4 LD0_DQSn 0 Func0 I A4 PBIDIR_MDDR Xm1DQSn 1 MP1_6 5 LD0_DQSn 1 Func0 I A4 PBIDIR_MDDR Xm1DQSn 2 MP...

Page 54: ... LD1_ADDR 11 Func0 O L A4 PBIDIR_MDDR Xm2ADDR 12 MP2_1 4 LD1_ADDR 12 Func0 O L A4 PBIDIR_MDDR Xm2ADDR 13 MP2_1 5 LD1_ADDR 13 Func0 O L A4 PBIDIR_MDDR Xm2ADDR 14 MP2_1 6 LD1_ADDR 14 Func0 O L A4 PBIDIR_MDDR Xm2ADDR 15 MP2_1 7 LD1_ADDR 15 Func0 O L A4 PBIDIR_MDDR Xm2DATA 0 MP2_2 0 LD1_DATA 0 Func0 I A4 PBIDIR_MDDR Xm2DATA 1 MP2_2 1 LD1_DATA 1 Func0 I A4 PBIDIR_MDDR Xm2DATA 2 MP2_2 2 LD1_DATA 2 Func0...

Page 55: ...ATA 30 Func0 I A4 PBIDIR_MDDR Xm2DATA 31 MP2_5 7 LD1_DATA 31 Func0 I A4 PBIDIR_MDDR Xm2DQS 0 MP2_6 0 LD1_DQS 0 Func0 I A4 PBIDIR_MDDR Xm2DQS 1 MP2_6 1 LD1_DQS 1 Func0 I A4 PBIDIR_MDDR Xm2DQS 2 MP2_6 2 LD1_DQS 2 Func0 I A4 PBIDIR_MDDR Xm2DQS 3 MP2_6 3 LD1_DQS 3 Func0 I A4 PBIDIR_MDDR Xm2DQSn 0 MP2_6 4 LD1_DQSn 0 Func0 I A4 PBIDIR_MDDR Xm2DQSn 1 MP2_6 5 LD1_DQSn 1 Func0 I A4 PBIDIR_MDDR Xm2DQSn 2 MP...

Page 56: ...OM 4 Func0 I B1 PBIDIRSE_G XOM 5 ETC1 5 XOM 5 Func0 I B1 PBIDIRSE_G XDDR2SEL ETC1 6 XDDR2_SEL Func0 I A1 PBIDIRSE_G XPWRRGTON ETC1 7 XPWRRGTON Func0 O L B1 PBIDIRSE_G XnRESET ETC2 0 XnRESET Func0 I B1 PBIDIRSE_G XCLKOUT ETC2 1 CLKOUT Func0 O L B1 PBIDIRSE_G XnRSTOUT ETC2 2 XnRSTOUT Func0 O L B1 PBIDIRSE_G XnWRESET ETC2 3 XnWRESET Func0 PU I H B1 PBIDIRSE_G XRTCCLKO ETC2 4 RTC_CLKOUT Func0 O L B1 P...

Page 57: ...NALOGS XhdmiTX2P ANALOG HDMI_TX2P Func0 O H B2 PANALOGS XhdmiTX2N ANALOG HDMI_TX2N Func0 O H B2 PANALOGS XhdmiTXCP ANALOG HDMI_TXCP Func0 O H B2 PANALOGS XhdmiTXCN ANALOG HDMI_TXCN Func0 O H B2 PANALOGS XhdmiREXT ANALOG HDMI_REXT Func0 I B2 PANALOGS XhdmiXTI ANALOG HDMI_XI Func0 I B2 POSCP XhdmiXTO ANALOG HDMI_XO Func0 O L B2 POSCP XmipiMDP0 ANALOG MIPI_MDP_0 Func0 I B2 PANALOGS XmipiMDP1 ANALOG M...

Page 58: ...PVHTBR_33_5 T XuotgREXT ANALOG XuotgREXT Func0 I B2 PANALOGS XuotgDM ANALOG XuotgDM Func0 I B2 PVHTBR_33_5 T XuotgANTEST ANALOG XuotgANALOGTE ST Func0 O L B2 PANALOGS XefFSOURCE_0 ANALOG efrom_fsource_0 Func0 I B2 PV_EFUSE XefFSOURCE_1 ANALOG efrom_fsource_1 Func0 I B2 PV_EFUSE XefFSOURCE_2 ANALOG efrom_fsource_2 Func0 I B2 PV_EFUSE XabbNBBG ANALOG XabbNBBG Func0 I B2 PVDRAM XabbPBBG ANALOG XabbPB...

Page 59: ... step strength output PVHTBR_33_5T Wide range I O supply 5V tolerant bi direction path through pad with 3 different paths which have no resistor 50ohm or 200ohm resistor PANALOGS Analog input Note This cell does not support fail safe operation PANALOGSW Analog input Note This cell does not support fail safe operation Pin port wide type POSCP Wide range I O supply programmable and retention oscilla...

Page 60: ...0 GPA0PUDPDN 0xE020_0014 R W Port Group GPA0 Power Down Mode Pull up down Register 0x00 GPA1CON 0xE020_0020 R W Port Group GPA1 Configuration Register 0x00000000 GPA1DAT 0xE020_0024 R W Port Group GPA1 Data Register 0x00 GPA1PUD 0xE020_0028 R W Port Group GPA1 Pull up down Register 0x0055 GPA1DRV 0xE020_002C R W Port Group GPA1 Drive Strength Control Register 0x0000 GPA1CONPDN 0xE020_0030 R W Port...

Page 61: ...er 0x00000000 GPD0DAT 0xE020_00A4 R W Port Group GPD0 Data Register 0x00 GPD0PUD 0xE020_00A8 R W Port Group GPD0 Pull up down Register 0x0055 GPD0DRV 0xE020_00AC R W Port Group GPD0 Drive Strength Control Register 0x0000 GPD0CONPDN 0xE020_00B0 R W Port Group GPD0 Power Down Mode Configuration Register 0x00 GPD0PUDPDN 0xE020_00B4 R W Port Group GPD0 Power Down Mode Pull up down Register 0x00 GPD1CO...

Page 62: ...C R W Port Group GPF0 Drive Strength Control Register 0x0000 GPF0CONPDN 0xE020_0130 R W Port Group GPF0 Power Down Mode Configuration Register 0x00 GPF0PUDPDN 0xE020_0134 R W Port Group GPF0 Power Down Mode Pull up down Register 0x00 GPF1CON 0xE020_0140 R W Port Group GPF1 Configuration Register 0x00000000 GPF1DAT 0xE020_0144 R W Port Group GPF1 Data Register 0x00 GPF1PUD 0xE020_0148 R W Port Grou...

Page 63: ...G0 Power Down Mode Pull up down Register 0x00 GPG1CON 0xE020_01C0 R W Port Group GPG1 Configuration Register 0x00000000 GPG1DAT 0xE020_01C4 R W Port Group GPG1 Data Register 0x00 GPG1PUD 0xE020_01C8 R W Port Group GPG1 Pull up down Register 0x1555 GPG1DRV 0xE020_01CC R W Port Group GPG1 Drive Strength Control Register 0x0000 GPG1CONPDN 0xE020_01D0 R W Port Group GPG1 Power Down Mode Configuration ...

Page 64: ...xE020_0248 R W Port Group GPJ0 Pull up down Register 0x5555 GPJ0DRV 0xE020_024C R W Port Group GPJ0 Drive Strength Control Register 0x0000 GPJ0CONPDN 0xE020_0250 R W Port Group GPJ0 Power Down Mode Configuration Register 0x00 GPJ0PUDPDN 0xE020_0254 R W Port Group GPJ0 Power Down Mode Pull up down Register 0x00 GPJ1CON 0xE020_0260 R W Port Group GPJ1 Configuration Register 0x00000000 GPJ1DAT 0xE020...

Page 65: ...iguration Register 0x00 GPJ4PUDPDN 0xE020_02D4 R W Port Group GPJ4 Power Down Mode Pull up down Register 0x00 MP0_1CON 0xE020_02E0 R W Port Group MP0_1 Configuration Register 0x22553322 MP0_1DAT 0xE020_02E4 R W Port Group MP0_1 Data Register 0x00 MP0_1PUD 0xE020_02E8 R W Port Group MP0_1 Pull up down Register 0x0000 MP0_1DRV 0xE020_02EC R W Port Group MP0_1 Drive Strength Control Register 0xAAAA M...

Page 66: ...x22222222 MP0_5DAT 0xE020_0364 R W Port Group MP0_5 Data Register 0x00 MP0_5PUD 0xE020_0368 R W Port Group MP0_5 Pull up down Register 0x0000 MP0_5DRV 0xE020_036C R W Port Group MP0_5 Drive Strength Control Register 0xAAAA MP0_5CONPDN 0xE020_0370 R W Port Group MP0_5 Power Down Mode Configuration Register 0x00 MP0_5PUDPDN 0xE020_0374 R W Port Group MP0_5 Power Down Mode Pull up down Register 0x00 ...

Page 67: ...PUDPDN 0xE020_03F4 R W Reserved Do not use this register 0x00 MP1_2CON 0xE020_0400 R W Reserved Do not use this register 0x22222222 MP1_2DAT 0xE020_0404 R W Reserved Do not use this register 0x00 MP1_2PUD 0xE020_0408 R W Reserved Do not use this register 0x0000 MP1_2DRV 0xE020_040C R W Port Group MP1_2 Drive Strength Control Register 0xAAAA MP1_2CONPDN 0xE020_0410 R W Reserved Do not use this regi...

Page 68: ... Reserved Do not use this register 0x00 MP1_7PUD 0xE020_04A8 R W Reserved Do not use this register 0x0000 MP1_7DRV 0xE020_04AC R W Port Group MP1_7 Drive Strength Control Register 0xAAAA MP1_7CONPDN 0xE020_04B0 R W Reserved Do not use this register 0x00 MP1_7PUDPDN 0xE020_04B4 R W Reserved Do not use this register 0x00 MP1_8CON 0xE020_04C0 R W Reserved Do not use this register 0x02222222 MP1_8DAT ...

Page 69: ...ister 0xAAAA MP2_3CONPDN 0xE020_0550 R W Reserved Do not use this register 0x00 MP2_3PUDPDN 0xE020_0554 R W Reserved Do not use this register 0x00 MP2_4CON 0xE020_0560 R W Reserved Do not use this register 0x22222222 MP2_4DAT 0xE020_0564 R W Reserved Do not use this register 0x00 MP2_4PUD 0xE020_0568 R W Reserved Do not use this register 0x0000 MP2_4DRV 0xE020_056C R W Port Group MP2_4 Drive Stren...

Page 70: ...ONPDN 0xE020_05F0 R W Reserved Do not use this register 0x00 MP2_8PUDPDN 0xE020_05F4 R W Reserved Do not use this register 0x00 ETC0PUD 0xE020_0608 R W Port Group ETC0 Pull up down Register 0x0000 ETC0DRV 0xE020_060C R W Port Group ETC0 Drive Strength Control Register 0x0000 ETC1PUD 0xE020_0628 R W Port Group ETC1 Pull up down Register 0x0000 ETC1DRV 0xE020_062C R W Port Group ETC1 Drive Strength ...

Page 71: ...ON 0xE020_0740 R W GPIO Interrupt GPG3_INT Configuration Register 0x0 GPJ0_INT_CON 0xE020_0744 R W GPIO Interrupt GPJ0_INT Configuration Register 0x0 GPJ1_INT_CON 0xE020_0748 R W GPIO Interrupt GPJ1_INT Configuration Register 0x0 GPJ2_INT_CON 0xE020_074C R W GPIO Interrupt GPJ2_INT Configuration Register 0x0 GPJ3_INT_CON 0xE020_0750 R W GPIO Interrupt GPJ3_INT Configuration Register 0x0 GPJ4_INT_C...

Page 72: ...r 0 0x0 GPE0_INT_FLTCON1 0xE020_083C R W GPIO Interrupt GPE0_INT Filter Configuration Register 1 0x0 GPE1_INT_FLTCON0 0xE020_0840 R W GPIO Interrupt GPE1_INT Filter Configuration Register 0 0x0 GPE1_INT_FLTCON1 0xE020_0844 R W GPIO Interrupt GPE1_INT Filter Configuration Register 1 0x0 GPF0_INT_FLTCON0 0xE020_0848 R W GPIO Interrupt GPF0_INT Filter Configuration Register 0 0x0 GPF0_INT_FLTCON1 0xE...

Page 73: ...ster 0 0x0 GPJ1_INT_FLTCON1 0xE020_0894 R W GPIO Interrupt GPJ1_INT Filter Configuration Register 1 0x0 GPJ2_INT_FLTCON0 0xE020_0898 R W GPIO Interrupt GPJ2_INT Filter Configuration Register 0 0x0 GPJ2_INT_FLTCON1 0xE020_089C R W GPIO Interrupt GPJ2_INT Filter Configuration Register 1 0x0 GPJ3_INT_FLTCON0 0xE020_08A0 R W GPIO Interrupt GPJ3_INT Filter Configuration Register 0 0x0 GPJ3_INT_FLTCON1 ...

Page 74: ...020_0950 R W GPIO Interrupt GPJ3_INT Mask Register 0x000000FF GPJ4_INT_MASK 0xE020_0954 R W GPIO Interrupt GPJ4_INT Mask Register 0x0000001F GPA0_INT_PEND 0xE020_0A00 R W GPIO Interrupt GPA0_INT Pending Register 0x0 GPA1_INT_PEND 0xE020_0A04 R W GPIO Interrupt GPA1_INT Pending Register 0x0 GPB_INT_PEND 0xE020_0A08 R W GPIO Interrupt GPB_INT Pending Register 0x0 GPC0_INT_PEND 0xE020_0A0C R W GPIO I...

Page 75: ...er 0x00 GPA0_INT_FIXPRI 0xE020_0B14 R W GPIO Interrupt 1 Fixed Priority Control Register 0x00 GPA1_INT_FIXPRI 0xE020_0B18 R W GPIO Interrupt 2 Fixed Priority Control Register 0x00 GPB_INT_FIXPRI 0xE020_0B1C R W GPIO Interrupt 3 Fixed Priority Control Register 0x00 GPC0_INT_FIXPRI 0xE020_0B20 R W GPIO Interrupt 4 Fixed Priority Control Register 0x00 GPC1_INT_FIXPRI 0xE020_0B24 R W GPIO Interrupt 5 ...

Page 76: ...00 GPH0DAT 0xE020_0C04 R W Port Group GPH0 Data Register 0x00 GPH0PUD 0xE020_0C08 R W Port Group GPH0 Pull up down Register 0x5555 GPH0DRV 0xE020_0C0C R W Port Group GPH0 Drive Strength Control Register 0x0000 GPH1CON 0xE020_0C20 R W Port Group GPH1 Configuration Register 0x00000000 GPH1DAT 0xE020_0C24 R W Port Group GPH1 Data Register 0x00 GPH1PUD 0xE020_0C28 R W Port Group GPH1 Pull up down Regi...

Page 77: ...EXT_INT_2_FLTCON1 0xE020_0E94 R W External Interrupt EXT_INT 16 EXT_INT 23 Filter Configuration Register 1 0x80808080 EXT_INT_3_FLTCON0 0xE020_0E98 R W External Interrupt EXT_INT 24 EXT_INT 31 Filter Configuration Register 0 0x80808080 EXT_INT_3_FLTCON1 0xE020_0E9C R W External Interrupt EXT_INT 24 EXT_INT 31 Filter Configuration Register 1 0x80808080 EXT_INT_0_MASK 0xE020_0F00 R W External Interr...

Page 78: ... 0000 Input 0001 Output 0010 UART_1_CTSn 0011 1110 Reserved 1111 GPA0_INT 6 0000 GPA0CON 5 23 20 0000 Input 0001 Output 0010 UART_1_TXD 0011 1110 Reserved 1111 GPA0_INT 5 0000 GPA0CON 4 19 16 0000 Input 0001 Output 0010 UART_1_RXD 0011 1110 Reserved 1111 GPA0_INT 4 0000 GPA0CON 3 15 12 0000 Input 0001 Output 0010 UART_0_RTSn 0011 1110 Reserved 1111 GPA0_INT 3 0000 GPA0CON 2 11 8 0000 Input 0001 Ou...

Page 79: ...it Description Initial State GPA0PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x5555 2 2 2 4 Port Group GPA0 Control Register GPA0DRV R W Address 0xE020_000C GPA0DRV Bit Description Initial State GPA0DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 2 5 Port Group GPA0 Control Register GPA0CONPDN R W Address 0xE020_0010 GPA0CONPDN Bit Descri...

Page 80: ...Bit Description Initial State GPA1CON 3 15 12 0000 Input 0001 Output 0010 UART_3_TXD 0011 UART_2_RTSn 0100 1110 Reserved 1111 GPA1_INT 3 0000 GPA1CON 2 11 8 0000 Input 0001 Output 0010 UART_3_RXD 0011 UART_2_CTSn 0100 1110 Reserved 1111 GPA1_INT 2 0000 GPA1CON 1 7 4 0000 Input 0001 Output 0010 UART_2_TXD 0011 Reserved 0100 UART_AUDIO_TXD 0101 1110 Reserved 1111 GPA1_INT 1 0000 GPA1CON 0 3 0 0000 I...

Page 81: ...it Description Initial State GPA1PUD n 2n 1 2n n 0 3 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0055 2 2 3 4 Port Group GPA1 Control Register GPA1DRV R W Address 0xE020_002C GPA1DRV Bit Description Initial State GPA1DRV n 2n 1 2n n 0 3 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 3 5 Port Group GPA1 Control Register GPA1CONPDN R W Address 0xE020_0030 GPA1CONPDN Bit Descri...

Page 82: ... 24 0000 Input 0001 Output 0010 SPI_1_MISO 0011 1110 Reserved 1111 GPB_INT 6 0000 GPBCON 5 23 20 0000 Input 0001 Output 0010 SPI_1_nSS 0011 1110 Reserved 1111 GPB_INT 5 0000 GPBCON 4 19 16 0000 Input 0001 Output 0010 SPI_1_CLK 0011 1110 Reserved 1111 GPB_INT 4 0000 GPBCON 3 15 12 0000 Input 0001 Output 0010 SPI_0_MOSI 0011 1110 Reserved 1111 GPB_INT 3 0000 GPBCON 2 11 8 0000 Input 0001 Output 0010...

Page 83: ...D Bit Description Initial State GPBPUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x5555 2 2 4 4 Port Group GPB Control Register GPBDRV R W Address 0xE020_004C GPBDRV Bit Description Initial State GPBDRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 4 5 Port Group GPB Control Register GPBCONPDN R W Address 0xE020_0050 GPBCONPDN Bit Description...

Page 84: ... I2S_1_SDO 0011 PCM_1_SOUT 0100 AC97SDO 0101 1110 Reserved 1111 GPC0_INT 4 0000 GPC0CON 3 15 12 0000 Input 0001 Output 0010 I2S_1_SDI 0011 PCM_1_SIN 0100 AC97SDI 0101 1110 Reserved 1111 GPC0_INT 3 0000 GPC0CON 2 11 8 0000 Input 0001 Output 0010 I2S_1_LRCK 0011 PCM_1_FSYNC 0100 AC97SYNC 0101 1110 Reserved 1111 GPC0_INT 2 0000 GPC0CON 1 7 4 0000 Input 0001 Output 0010 I2S_1_CDCLK 0011 PCM_1_EXTCLK 0...

Page 85: ...it Description Initial State GPC0PUD n 2n 1 2n n 0 4 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0155 2 2 5 4 Port Group GPC0 Control Register GPC0DRV R W Address 0xE020_006C GPC0DRV Bit Description Initial State GPC0DRV n 2n 1 2n n 0 4 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 5 5 Port Group GPC0 Control Register GPC0CONPDN R W Address 0xE020_0070 GPC0CONPDN Bit Descri...

Page 86: ...CM_2_SOUT 0011 Reserved 0100 I2S_2_SDO 0101 1110 Reserved 1111 GPC1_INT 4 0000 GPC1CON 3 15 12 0000 Input 0001 Output 0010 PCM_2_SIN 0011 Reserved 0100 I2S_2_SDI 0101 1110 Reserved 1111 GPC1_INT 3 0000 GPC1CON 2 11 8 0000 Input 0001 Output 0010 PCM_2_FSYNC 0011 LCD_FRM 0100 I2S_2_LRCK 0101 1110 Reserved 1111 GPC1_INT 2 0000 GPC1CON 1 7 4 0000 Input 0001 Output 0010 PCM_2_EXTCLK 0011 SPDIF_EXTCLK 0...

Page 87: ...it Description Initial State GPC1PUD n 2n 1 2n n 0 4 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0155 2 2 6 4 Port Group GPC1 Control Register GPC1DRV R W Address 0xE020_008C GPC1DRV Bit Description Initial State GPC1DRV n 2n 1 2n n 0 4 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 6 5 Port Group GPC1 Control Register GPC1CONPDN R W Address 0xE020_0090 GPC1CONPDN Bit Descri...

Page 88: ...tput 0010 TOUT_1 0011 1110 Reserved 1111 GPD0_INT 1 0000 GPD0CON 0 3 0 0000 Input 0001 Output 0010 TOUT_0 0011 1110 Reserved 1111 GPD0_INT 0 0000 2 2 7 2 Port Group GPD0 Control Register GPD0DAT R W Address 0xE020_00A4 GPD0DAT Bit Description Initial State GPD0DAT 3 0 3 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the...

Page 89: ... 2 2 7 5 Port Group GPD0 Control Register GPD0CONPDN R W Address 0xE020_00B0 GPD0CONPDN Bit Description Initial State GPD0 n 2n 1 2n n 0 3 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 7 6 Port Group GPD0 Control Register GPD0PUDPDN R W Address 0xE020_00B4 GPD0PUDPDN Bit Description Initial State GPD0 n 2n 1 2n n 0 3 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11...

Page 90: ...nput 0001 Output 0010 I2C2_SCL 0011 IEM_SPWI 0100 1110 Reserved 1111 GPD1_INT 5 0000 GPD1CON 4 19 16 0000 Input 0001 Output 0010 I2C2_SDA 0011 IEM_SCLK 0100 1110 Reserved 1111 GPD1_INT 4 0000 GPD1CON 3 15 12 0000 Input 0001 Output 0010 I2C1_SCL 0011 1110 Reserved 1111 GPD1_INT 3 0000 GPD1CON 2 11 8 0000 Input 0001 Output 0010 I2C1_SDA 0011 1110 Reserved 1111 GPD1_INT 2 0000 GPD1CON 1 7 4 0000 Inpu...

Page 91: ...it Description Initial State GPD1PUD n 2n 1 2n n 0 5 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0555 2 2 8 4 Port Group GPD1 Control Register GPD1DRV R W Address 0xE020_00CC GPD1DRV Bit Description Initial State GPD1DRV n 2n 1 2n n 0 5 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 8 5 Port Group GPD1 Control Register GPD1CONPDN R W Address 0xE020_00D0 GPD1CONPDN Bit Descri...

Page 92: ...000 Input 0001 Output 0010 CAM_A_DATA 3 0011 1110 Reserved 1111 GPE0_INT 6 0000 GPE0CON 5 23 20 0000 Input 0001 Output 0010 CAM_A_DATA 2 0011 1110 Reserved 1111 GPE0_INT 5 0000 GPE0CON 4 19 16 0000 Input 0001 Output 0010 CAM_A_DATA 1 0011 1110 Reserved 1111 GPE0_INT 4 0000 GPE0CON 3 15 12 0000 Input 0001 Output 0010 CAM_A_DATA 0 0011 1110 Reserved 1111 GPE0_INT 3 0000 GPE0CON 2 11 8 0000 Input 000...

Page 93: ...it Description Initial State GPE0PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x5555 2 2 9 4 Port Group GPE0 Control Register GPE0DRV S W Address 0xE020_00EC GPE0DRV Bit Description Initial State GPE0DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 9 5 Port Group GPE0 Control Register GPE0CONPDN S W Address 0xE020_00F0 GPE0CONPDN Bit Descri...

Page 94: ...Reserved 1111 GPE1_INT 3 0000 GPE1CON 2 11 8 0000 Input 0001 Output 0010 CAM_A_DATA 7 0011 1110 Reserved 1111 GPE1_INT 2 0000 GPE1CON 1 7 4 0000 Input 0001 Output 0010 CAM_A_DATA 6 0011 1110 Reserved 1111 GPE1_INT 1 0000 GPE1CON 0 3 0 0000 Input 0001 Output 0010 CAM_A_DATA 5 0011 1110 Reserved 1111 GPE1_INT 0 0000 2 2 10 2 Port Group GPE1 Control Register GPE1DAT R W Address 0xE020_0104 GPE1DAT Bi...

Page 95: ...ress 0xE020_010C GPE1DRV Bit Description Initial State GPE1DRV n 2n 1 2n n 0 4 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 10 5 Port Group GPE1 Control Register GPE1CONPDN R W Address 0xE020_0110 GPE1CONPDN Bit Description Initial State GPE1 n 2n 1 2n n 0 4 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 10 6 Port Group GPE1 Control Register GPE1PUDPDN R W Address 0xE020_0114 GPE1PUDPDN Bit Des...

Page 96: ...served 1111 GPF0_INT 7 0000 GPF0CON 6 27 24 0000 Input 0001 Output 0010 LCD_VD 2 0011 SYS_VD 2 0100 VEN_DATA 2 0101 1110 Reserved 1111 GPF0_INT 6 0000 GPF0CON 5 23 20 0000 Input 0001 Output 0010 LCD_VD 1 0011 SYS_VD 1 0100 VEN_DATA 1 0101 1110 Reserved 1111 GPF0_INT 5 0000 GPF0CON 4 19 16 0000 Input 0001 Output 0010 LCD_VD 0 0011 SYS_VD 0 0100 VEN_DATA 0 0101 1110 Reserved 1111 GPF0_INT 4 0000 GPF...

Page 97: ... 7 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00 2 2 11 3 Port Group GPF0 Control Register GPF0PUD R W Address 0xE020_0128 GPF0PUD Bit Description Initial State GPF0PUD n 2n 1 2n n 0 7 ...

Page 98: ...NPDN Bit Description Initial State GPF0 n 2n 1 2n n 0 7 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 11 6 Port Group GPF0 Control Register GPF0PUDPDN R W Address 0xE020_0134 GPF0PUDPDN Bit Description Initial State GPF0 n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x00 ...

Page 99: ...d 1111 GPF1_INT 7 0000 GPF1CON 6 27 24 0000 Input 0001 Output 0010 LCD_VD 10 0011 SYS_VD 10 0100 V656_DATA 2 0101 1110 Reserved 1111 GPF1_INT 6 0000 GPF1CON 5 23 20 0000 Input 0001 Output 0010 LCD_VD 9 0011 SYS_VD 9 0100 V656_DATA 1 0101 1110 Reserved 1111 GPF1_INT 5 0000 GPF1CON 4 19 16 0000 Input 0001 Output 0010 LCD_VD 8 0011 SYS_VD 8 0100 V656_DATA 0 0101 1110 Reserved 1111 GPF1_INT 4 0000 GPF...

Page 100: ...0 7 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00 2 2 12 3 Port Group GPF1 Control Register GPF1PUD S W Address 0xE020_0148 GPF1PUD Bit Description Initial State GPF1PUD n 2n 1 2n n 0 7...

Page 101: ...NPDN Bit Description Initial State GPF1 n 2n 1 2n n 0 7 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 12 6 Port Group GPF1 Control Register GPF1PUDPDN S W Address 0xE020_0154 GPF1PUDPDN Bit Description Initial State GPF1 n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x00 ...

Page 102: ...1110 Reserved 1111 GPF2_INT 7 0000 GPF2CON 6 27 24 0000 Input 0001 Output 0010 LCD_VD 18 0011 SYS_VD 18 0100 1110 Reserved 1111 GPF2_INT 6 0000 GPF2CON 5 23 20 0000 Input 0001 Output 0010 LCD_VD 17 0011 SYS_VD 17 0100 1110 Reserved 1111 GPF2_INT 5 0000 GPF2CON 4 19 16 0000 Input 0001 Output 0010 LCD_VD 16 0011 SYS_VD 16 0100 1110 Reserved 1111 GPF2_INT 4 0000 GPF2CON 3 15 12 0000 Input 0001 Output...

Page 103: ... 7 0 7 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00 2 2 13 3 Port Group GPF2 Control Register GPF2PUD R W Address 0xE020_0168 GPF2PUD Bit Description Initial State GPF2PUD n 2n 1 2n n ...

Page 104: ...NPDN Bit Description Initial State GPF2 n 2n 1 2n n 0 7 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 13 6 Port Group GPF2 Control Register GPF2PUDPDN S W Address 0xE020_0174 GPF2PUDPDN Bit Description Initial State GPF2 n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x00 ...

Page 105: ...00 VEN_FIELD 0101 1110 Reserved 1111 GPF3_INT 5 0000 GPF3CON 4 19 16 0000 Input 0001 Output 0010 Reserved 0011 VSYNC_LDI 0100 1110 Reserved 1111 GPF3_INT 4 0000 GPF3CON 3 15 12 0000 Input 0001 Output 0010 LCD_VD 23 0011 SYS_VD 23 0100 V656_CLK 0101 1110 Reserved 1111 GPF3_INT 3 0000 GPF3CON 2 11 8 0000 Input 0001 Output 0010 LCD_VD 22 0011 SYS_VD 22 0100 1110 Reserved 1111 GPF3_INT 2 0000 GPF3CON ...

Page 106: ...it Description Initial State GPF3PUD n 2n 1 2n n 0 5 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0555 2 2 14 4 Port Group GPF3 Control Register GPF3DRV R W Address 0xE020_018C GPF3DRV Bit Description Initial State GPF3DRV n 2n 1 2n n 0 5 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 14 5 Port Group GPF3 Control Register GPF3CONPDN R W Address 0xE020_0190 GPF3CONPDN Bit Desc...

Page 107: ...1 1110 Reserved 1111 GPG0_INT 6 0000 GPG0CON 5 23 20 0000 Input 0001 Output 0010 SD_0_DATA 2 0011 1110 Reserved 1111 GPG0_INT 5 0000 GPG0CON 4 19 16 0000 Input 0001 Output 0010 SD_0_DATA 1 0011 1110 Reserved 1111 GPG0_INT 4 0000 GPG0CON 3 15 12 0000 Input 0001 Output 0010 SD_0_DATA 0 0011 1110 Reserved 1111 GPG0_INT 3 0000 GPG0CON 2 11 8 0000 Input 0001 Output 0010 SD_0_CDn 0011 1110 Reserved 1111...

Page 108: ...it Description Initial State GPG0PUD n 2n 1 2n n 0 6 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x1555 2 2 15 4 Port Group GPG0 Control Register GPG0DRV R W Address 0xE020_01AC GPG0DRV Bit Description Initial State GPG0DRV n 2n 1 2n n 0 6 00 1x 10 2x 01 3x 11 4x 0x2AAA 2 2 15 5 Port Group GPG0 Control Register GPG0CONPDN R W Address 0xE020_01B0 GPG0CONPDN Bit Desc...

Page 109: ...111 GPG1_INT 6 0000 GPG1CON 5 23 20 0000 Input 0001 Output 0010 SD_1_DATA 2 0011 SD_0_DATA 6 0100 1110 Reserved 1111 GPG1_INT 5 0000 GPG1CON 4 19 16 0000 Input 0001 Output 0010 SD_1_DATA 1 0011 SD_0_DATA 5 0100 1110 Reserved 1111 GPG1_INT 4 0000 GPG1CON 3 15 12 0000 Input 0001 Output 0010 SD_1_DATA 0 0011 SD_0_DATA 4 0100 1110 Reserved 1111 GPG1_INT 3 0000 GPG1CON 2 11 8 0000 Input 0001 Output 001...

Page 110: ...it Description Initial State GPG1PUD n 2n 1 2n n 0 6 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x1555 2 2 16 4 Port Group GPG1 Control Register GPG1DRV R W Address 0xE020_01CC GPG1DRV Bit Description Initial State GPG1DRV n 2n 1 2n n 0 6 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 16 5 Port Group GPG1 Control Register GPG1CONPDN R W Address 0xE020_01D0 GPG1CONPDN Bit Desc...

Page 111: ...1 1110 Reserved 1111 GPG2_INT 6 0000 GPG2CON 5 23 20 0000 Input 0001 Output 0010 SD_2_DATA 2 0011 1110 Reserved 1111 GPG2_INT 5 0000 GPG2CON 4 19 16 0000 Input 0001 Output 0010 SD_2_DATA 1 0011 1110 Reserved 1111 GPG2_INT 4 0000 GPG2CON 3 15 12 0000 Input 0001 Output 0010 SD_2_DATA 0 0011 1110 Reserved 1111 GPG2_INT 3 0000 GPG2CON 2 11 8 0000 Input 0001 Output 0010 SD_2_CDn 0011 1110 Reserved 1111...

Page 112: ...it Description Initial State GPG2PUD n 2n 1 2n n 0 6 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x1555 2 2 17 4 Port Group GPG2 Control Register GPG2DRV R W Address 0xE020_01EC GPG2DRV Bit Description Initial State GPG2DRV n 2n 1 2n n 0 6 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 17 5 Port Group GPG2 Control Register GPG2CONPDN R W Address 0xE020_01F0 GPG2CONPDN Bit Desc...

Page 113: ...111 GPG3_INT 6 0000 GPG3CON 5 23 20 0000 Input 0001 Output 0010 SD_3_DATA 2 0011 SD_2_DATA 6 0100 1110 Reserved 1111 GPG3_INT 5 0000 GPG3CON 4 19 16 0000 Input 0001 Output 0010 SD_3_DATA 1 0011 SD_2_DATA 5 0100 1110 Reserved 1111 GPG3_INT 4 0000 GPG3CON 3 15 12 0000 Input 0001 Output 0010 SD_3_DATA 0 0011 SD_2_DATA 4 0100 1110 Reserved 1111 GPG3_INT 3 0000 GPG3CON 2 11 8 0000 Input 0001 Output 001...

Page 114: ...it Description Initial State GPG3PUD n 2n 1 2n n 0 6 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x1555 2 2 18 4 Port Group GPG3 Control Register GPG3DRV R W Address 0xE020_020C GPG3DRV Bit Description Initial State GPG3DRV n 2n 1 2n n 0 6 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 18 5 Port Group GPG3 Control Register GPG3CONPDN R W Address 0xE020_0210 GPG3CONPDN Bit Desc...

Page 115: ...0 0010 I2S_0_SDO 1 0010 GPICON 4 19 16 0010 I2S_0_SDO 0 0011 PCM_0_SOUT 0010 GPICON 3 15 12 0010 I2S_0_SDI 0011 PCM_0_SIN 0010 GPICON 2 11 8 0010 I2S_0_LRCK 0011 PCM_0_FSYNC 0010 GPICON 1 7 4 0010 I2S_0_CDCLK 0011 PCM_0_EXTCLK 0010 GPICON 0 3 0 0010 I2S_0_SCLK 0011 PCM_0_SCLK 0010 2 2 19 2 Port Group GPI Control Register GPIDAT R W Address 0xE020_0224 GPIDAT Bit Description Initial State GPIDAT 6 ...

Page 116: ...ress 0xE020_0230 GPICONPDN Bit Description Initial State GPI n 2n 1 2n n 0 6 Reserved Controlled by PAD_CON_CTRL register at AUDIO_SS 0x00 2 2 19 6 Port Group GPI Control Register GPIPUDPDN R W Address 0xE020_0234 GPIPUDPDN Bit Description Initial State GPI n 2n 1 2n n 0 6 Reserved Controlled by GPIPUD register 0x00 For GPI PDN control in power down mode PAD_PDN_CTRL Register of GPI is at AUDIO_SS...

Page 117: ...Reserved 1111 GPJ0_INT 7 0000 GPJ0CON 6 27 24 0000 Input 0001 Output 0010 MSM_ADDR 6 0011 CAM_B_DATA 6 0100 CF_DRESETN 0101 TS_ERROR 0110 1110 Reserved 1111 GPJ0_INT 6 0000 GPJ0CON 5 23 20 0000 Input 0001 Output 0010 MSM_ADDR 5 0011 CAM_B_DATA 5 0100 CF_DMARQ 0101 TS_DATA 0110 1110 Reserved 1111 GPJ0_INT 5 0000 GPJ0CON 4 19 16 0000 Input 0001 Output 0010 MSM_ADDR 4 0011 CAM_B_DATA 4 0100 CF_INTRQ ...

Page 118: ...ved 1111 GPJ0_INT 0 0000 2 2 20 2 Port Group GPJ0 Control Register GPJ0DAT R W Address 0xE020_0244 GPJ0DAT Bit Description Initial State GPJ0DAT 7 0 7 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will b...

Page 119: ...2 2 20 5 Port Group GPJ0 Control Register GPJ0CONPDN R W Address 0xE020_0250 GPJ0CONPDN Bit Description Initial State GPJ0 n 2n 1 2n n 0 7 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 20 6 Port Group GPJ0 Control Register GPJ0PUDPDN R W Address 0xE020_0254 GPJ0PUDPDN Bit Description Initial State GPJ0 n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 1...

Page 120: ... 0001 Output 0010 MSM_ADDR 12 0011 CAM_B_CLKOUT 0100 SROM_ADDR_16to22 4 0101 MHL_D5 0110 1110 Reserved 1111 GPJ1_INT 4 0000 GPJ1CON 3 15 12 0000 Input 0001 Output 0010 MSM_ADDR 11 0011 CAM_B_FIELD 0100 SROM_ADDR_16to22 3 0101 MHL_D4 0110 1110 Reserved 1111 GPJ1_INT 3 0000 GPJ1CON 2 11 8 0000 Input 0001 Output 0010 MSM_ADDR 10 0011 CAM_B_HREF 0100 SROM_ADDR_16to22 2 0101 MHL_D3 0110 1110 Reserved 1...

Page 121: ...it Description Initial State GPJ1PUD n 2n 1 2n n 0 5 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0555 2 2 21 4 Port Group GPJ1 Control Register GPJ1DRV R W Address 0xE020_026C GPJ1DRV Bit Description Initial State GPJ1DRV n 2n 1 2n n 0 5 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 21 5 Port Group GPJ1 Control Register GPJ1CONPDN R W Address 0xE020_0270 GPJ1CONPDN Bit Desc...

Page 122: ...1110 Reserved 1111 GPJ2_INT 7 0000 GPJ2CON 6 27 24 0000 Input 0001 Output 0010 MSM_DATA 6 0011 KP_COL 7 0100 CF_DATA 6 0101 MHL_D13 0110 1110 Reserved 1111 GPJ2_INT 6 0000 GPJ2CON 5 23 20 0000 Input 0001 Output 0010 MSM_DATA 5 0011 KP_COL 6 0100 CF_DATA 5 0101 MHL_D12 0110 1110 Reserved 1111 GPJ2_INT 5 0000 GPJ2CON 4 19 16 0000 Input 0001 Output 0010 MSM_DATA 4 0011 KP_COL 5 0100 CF_DATA 4 0101 MH...

Page 123: ..._INT 0 0000 2 2 22 2 Port Group GPJ2 Control Register GPJ2DAT R W Address 0xE020_0284 GPJ2DAT Bit Description Initial State GPJ2DAT 7 0 7 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00 2...

Page 124: ...2 2 22 5 Port Group GPJ2 Control Register GPJ2CONPDN R W Address 0xE020_0290 GPJ2CONPDN Bit Description Initial State GPJ2 n 2n 1 2n n 0 7 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 22 6 Port Group GPJ2 Control Register GPJ2PUDPDN R W Address 0xE020_0294 GPJ2PUDPDN Bit Description Initial State GPJ2 n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 1...

Page 125: ... Reserved 1111 GPJ3_INT 7 0000 GPJ3CON 6 27 24 0000 Input 0001 Output 0010 MSM_DATA 14 0011 KP_ROW 7 0100 CF_DATA 14 0101 MHL_D21 0110 1110 Reserved 1111 GPJ3_INT 6 0000 GPJ3CON 5 23 20 0000 Input 0001 Output 0010 MSM_DATA 13 0011 KP_ROW 6 0100 CF_DATA 13 0101 MHL_D20 0110 1110 Reserved 1111 GPJ3_INT 5 0000 GPJ3CON 4 19 16 0000 Input 0001 Output 0010 MSM_DATA 12 0011 KP_ROW 5 0100 CF_DATA 12 0101 ...

Page 126: ...J3_INT 0 0000 2 2 23 2 Port Group GPJ3 Control Register GPJ3DAT R W Address 0xE020_02A4 GPJ3DAT Bit Description Initial State GPJ3DAT 7 0 7 0 When the port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00...

Page 127: ...2 2 23 5 Port Group GPJ3 Control Register GPJ3CONPDN R W Address 0xE020_02B0 GPJ3CONPDN Bit Description Initial State GPJ3 n 2n 1 2n n 0 7 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 23 6 Port Group GPJ3 Control Register GPJ3PUDPDN R W Address 0xE020_02B4 GPJ3PUDPDN Bit Description Initial State GPJ3 n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 1...

Page 128: ...100 SROM_ADDR_16to22 6 0101 MHL_DE 0110 1110 Reserved 1111 GPJ4_INT 4 0000 GPJ4CON 3 15 12 0000 Input 0001 Output 0010 MSM_IRQn 0011 KP_ROW 12 0100 CF_IOWN 0101 MHL_VSYNC 0110 1110 Reserved 1111 GPJ4_INT 3 0000 GPJ4CON 2 11 8 0000 Input 0001 Output 0010 MSM_Rn 0011 KP_ROW 11 0100 CF_IORN 0101 MHL_IDCK 0110 1110 Reserved 1111 GPJ4_INT 2 0000 GPJ4CON 1 7 4 0000 Input 0001 Output 0010 MSM_WEn 0011 KP...

Page 129: ...it Description Initial State GPJ4PUD n 2n 1 2n n 0 4 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0155 2 2 24 4 Port Group GPJ4 Control Register GPJ4DRV R W Address 0xE020_02CC GPJ4DRV Bit Description Initial State GPJ4DRV n 2n 1 2n n 0 4 00 1x 10 2x 01 3x 11 4x 0x0000 2 2 24 5 Port Group GPJ4 Control Register GPJ4CONPDN R W Address 0xE020_02D0 GPJ4CONPDN Bit Desc...

Page 130: ...Reserved 1111 Reserved 0010 MP0_1CON 5 23 20 0000 Input 0001 Output 0010 SROM_CSn 5 0011 NFCSn 3 0100 Reserved 0101 ONANDXL_CSn 1 0110 1110 Reserved 1111 Reserved 0101 MP0_1CON 4 19 16 0000 Input 0001 Output 0010 SROM_CSn 4 0011 NFCSn 2 0100 Reserved 0101 ONANDXL_CSn 0 0110 1110 Reserved 1111 Reserved 0101 MP0_1CON 3 15 12 0000 Input 0001 Output 0010 SROM_CSn 3 0011 NFCSn 1 0100 1110 Reserved 1111...

Page 131: ...Description Initial State MP0_1PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0000 2 2 25 4 Port Group MP0_1 Control Register MP0_1DRV R W Address 0xE020_02EC MP0_1DRV Bit Description Initial State MP0_1DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 25 5 Port Group MP0_1 Control Register MP0_1CONPDN R W Address 0xE020_02F0 MP0_1CONPDN Bit...

Page 132: ... 11 8 0000 Input 0001 Output 0010 SROM_WAITn 0011 1110 Reserved 1111 Reserved 0010 MP0_2CON 1 7 4 0000 Input 0001 Output 0010 EBI_BEn 1 0011 1110 Reserved 1111 Reserved 0010 MP0_2CON 0 3 0 0000 Input 0001 Output 0010 EBI_BEn 0 0011 1110 Reserved 1111 Reserved 0010 2 2 26 2 Port Group MP0_2 Control Register MP0_2DAT R W Address 0xE020_0304 MP0_2DAT Bit Description Initial State MP0_2DAT 3 0 3 0 Whe...

Page 133: ...ss 0xE020_030C MP0_2DRV Bit Description Initial State MP0_2DRV n 2n 1 2n n 0 3 00 1x 10 2x 01 3x 11 4x 0x00AA 2 2 26 5 Port Group MP0_2 Control Register MP0_2CONPDN R W Address 0xE020_0310 MP0_2CONPDN Bit Description Initial State MP0_2 n 2n 1 2n n 0 3 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 26 6 Port Group MP0_2 Control Register MP0_2PUDPDN R W Address 0xE020_0314 MP0_2PUDPDN ...

Page 134: ...3CON 6 27 24 0000 Input 0001 Output 0010 NF_RnB 2 0011 1110 Reserved 1111 Reserved 0010 MP0_3CON 5 23 20 0000 Input 0001 Output 0010 NF_RnB 1 0011 Reserved 0100 Reserved 0101 ONANDXL_INT 1 0110 1110 Reserved 1111 Reserved 0101 MP0_3CON 4 19 16 0000 Input 0001 Output 0010 NF_RnB 0 0011 Reserved 0100 Reserved 0101 ONANDXL_INT 0 0110 1110 Reserved 1111 Reserved 0101 MP0_3CON 3 15 12 0000 Input 0001 O...

Page 135: ...e port is configured as input port the corresponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00 2 2 27 3 Port Group MP0_3 Control Register MP0_3PUD R W Address 0xE020_0328 MP0_3PUD Bit Description Initial State MP0_3PUD n 2n 1 2n n 0 7 00 Pull ...

Page 136: ...PDN Bit Description Initial State MP0_3 n 2n 1 2n n 0 7 00 Output 0 01 Output 1 10 Input 11 Previous state 0x00 2 2 27 6 Port Group MP0_3 Control Register MP0_3PUDPDN R W Address 0xE020_0334 MP0_3PUDPDN Bit Description Initial State MP0_3 n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x00 ...

Page 137: ...ON 1 7 4 0000 Input 0001 Output 0010 EBI_ADDR 1 0011 1110 Reserved 1111 Reserved 0010 MP0_4CON 2 11 8 0000 Input 0001 Output 0010 EBI_ADDR 2 0011 1110 Reserved 1111 Reserved 0010 MP0_4CON 3 15 12 0000 Input 0001 Output 0010 EBI_ADDR 3 0011 1110 Reserved 1111 Reserved 0010 MP0_4CON 4 19 16 0000 Input 0001 Output 0010 EBI_ADDR 4 0011 1110 Reserved 1111 Reserved 0010 MP0_4CON 5 23 20 0000 Input 0001 ...

Page 138: ...Description Initial State MP0_4PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0000 2 2 28 4 Port Group MP0_4 Control Register MP0_4DRV R W Address 0xE020_034C MP0_4DRV Bit Description Initial State MP0_4DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 28 5 Port Group MP0_4 Control Register MP0_4CONPDN R W Address 0xE020_0350 MP0_4CONPDN Bit...

Page 139: ...1 7 4 0000 Input 0001 Output 0010 EBI_ADDR 9 0011 1110 Reserved 1111 Reserved 0010 MP0_5CON 2 11 8 0000 Input 0001 Output 0010 EBI_ADDR 10 0011 1110 Reserved 1111 Reserved 0010 MP0_5CON 3 15 12 0000 Input 0001 Output 0010 EBI_ADDR 11 0011 1110 Reserved 1111 Reserved 0010 MP0_5CON 4 19 16 0000 Input 0001 Output 0010 EBI_ADDR 12 0011 1110 Reserved 1111 Reserved 0010 MP0_5CON 5 23 20 0000 Input 0001 ...

Page 140: ...Description Initial State MP0_5PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0000 2 2 29 4 Port Group MP0_5 Control Register MP0_5DRV R W Address 0xE020_036C MP0_5DRV Bit Description Initial State MP0_5DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 29 5 Port Group MP0_5 Control Register MP0_5CONPDN R W Address 0xE020_0370 MP0_5CONPDN Bit...

Page 141: ...ON 1 7 4 0000 Input 0001 Output 0010 EBI_DATA 1 0011 1110 Reserved 1111 Reserved 0010 MP0_6CON 2 11 8 0000 Input 0001 Output 0010 EBI_DATA 2 0011 1110 Reserved 1111 Reserved 0010 MP0_6CON 3 15 12 0000 Input 0001 Output 0010 EBI_DATA 3 0011 1110 Reserved 1111 Reserved 0010 MP0_6CON 4 19 16 0000 Input 0001 Output 0010 EBI_DATA 4 0011 1110 Reserved 1111 Reserved 0010 MP0_6CON 5 23 20 0000 Input 0001 ...

Page 142: ...Description Initial State MP0_6PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0000 2 2 30 4 Port Group MP0_6 Control Register MP0_6DRV S W Address 0xE020_038C MP0_6DRV Bit Description Initial State MP0_6DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 30 5 Port Group MP0_6 Control Register MP0_6CONPDN S W Address 0xE020_0390 MP0_6CONPDN Bit...

Page 143: ...1 7 4 0000 Input 0001 Output 0010 EBI_DATA 9 0011 1110 Reserved 1111 Reserved 0010 MP0_7CON 2 11 8 0000 Input 0001 Output 0010 EBI_DATA 10 0011 1110 Reserved 1111 Reserved 0010 MP0_7CON 3 15 12 0000 Input 0001 Output 0010 EBI_DATA 11 0011 1110 Reserved 1111 Reserved 0010 MP0_7CON 4 19 16 0000 Input 0001 Output 0010 EBI_DATA 12 0011 1110 Reserved 1111 Reserved 0010 MP0_7CON 5 23 20 0000 Input 0001 ...

Page 144: ...Description Initial State MP0_7PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x0000 2 2 31 4 Port Group MP0_7 Control Register MP0_7DRV R W Address 0xE020_03AC MP0_7DRV Bit Description Initial State MP0_7DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 31 5 Port Group MP0_7 Control Register MP0_7CONPDN R W Address 0xE020_03B0 MP0_7CONPDN Bit...

Page 145: ...UDPDN R W Address 0xE020_03D4 MP1_0DRV Bit Description Initial State MP1_0DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 33 PORT GROUP MP1_1 CONTROL REGISTER There are six control registers namely MP1_1CON MP1_1DAT MP1_1PUD MP1_1DRV MP1_1CONPDN and MP1_1PUDPDN in the Port Group MP1_1 Control Registers MP1_1CON R W Address 0xE020_03E0 MP1_1DAT R W Address 0xE020_03E4 MP1_1PUD R W Address 0x...

Page 146: ...UDPDN R W Address 0xE020_0414 MP1_2DRV Bit Description Initial State MP1_2DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 35 PORT GROUP MP1_3 CONTROL REGISTER There are six control registers namely MP1_3CON MP1_3DAT MP1_3PUD MP1_3DRV MP1_3CONPDN and MP1_3PUDPDN in the Port Group MP1_3 Control Registers MP1_3CON R W Address 0xE020_0420 MP1_3DAT R W Address 0xE020_0424 MP1_3PUD R W Address 0x...

Page 147: ...UDPDN R W Address 0xE020_0454 MP1_4DRV Bit Description Initial State MP1_4DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 37 PORT GROUP MP1_5 CONTROL REGISTER There are six control registers namely MP1_5CON MP1_5DAT MP1_5PUD MP1_5DRV MP1_5CONPDN and MP1_5PUDPDN in the Port Group MP1_5 Control Registers MP1_5CON R W Address 0xE020_0460 MP1_5DAT R W Address 0xE020_0464 MP1_5PUD R W Address 0x...

Page 148: ...UDPDN R W Address 0xE020_0494 MP1_6DRV Bit Description Initial State MP1_6DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 39 PORT GROUP MP1_7 CONTROL REGISTER There are six control registers namely MP1_7CON MP1_7DAT MP1_7PUD MP1_7DRV MP1_7CONPDN and MP1_7PUDPDN in the Port Group MP1_7 Control Registers MP1_7CON R W Address 0xE020_04A0 MP1_7DAT R W Address 0xE020_04A4 MP1_7PUD R W Address 0x...

Page 149: ...UDPDN R W Address 0xE020_04D4 MP1_8DRV Bit Description Initial State MP1_8DRV n 2n 1 2n n 0 6 00 1x 10 2x 01 3x 11 4x 0x2AAA 2 2 41 PORT GROUP MP2_0 CONTROL REGISTER There are six control registers namely MP2_0CON MP2_0DAT MP2_0PUD MP2_0DRV MP2_0CONPDN and MP2_0PUDPDN in the Port Group MP2_0 Control Registers MP2_0CON R W Address 0xE020_04E0 MP2_0DAT R W Address 0xE020_04E4 MP2_0PUD R W Address 0x...

Page 150: ...UDPDN R W Address 0xE020_0514 MP2_1DRV Bit Description Initial State MP2_1DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 43 PORT GROUP MP2_2 CONTROL REGISTER There are six control registers namely MP2_2CON MP2_2DAT MP2_2PUD MP2_2DRV MP2_2CONPDN and MP2_2PUDPDN in the Port Group MP2_2 Control Registers MP2_2CON R W Address 0xE020_0520 MP2_2DAT R W Address 0xE020_0524 MP2_2PUD R W Address 0x...

Page 151: ...UDPDN R W Address 0xE020_0554 MP2_3DRV Bit Description Initial State MP2_3DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 45 PORT GROUP MP2_4 CONTROL REGISTER There are six control registers namely MP2_4CON MP2_4DAT MP2_4PUD MP2_4DRV MP2_4CONPDN and MP2_4PUDPDN in the Port Group MP2_4 Control Registers MP2_4CON R W Address 0xE020_0560 MP2_4DAT R W Address 0xE020_0564 MP2_4PUD R W Address 0x...

Page 152: ...UDPDN R W Address 0xE020_0594 MP2_5DRV Bit Description Initial State MP2_5DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 47 PORT GROUP MP2_6 CONTROL REGISTER There are six control registers namely MP2_6CON MP2_6DAT MP2_6PUD MP2_6DRV MP2_6CONPDN and MP2_6PUDPDN in the Port Group MP2_6 Control Registers MP2_6CON R W Address 0xE020_05A0 MP2_6DAT R W Address 0xE020_05A4 MP2_6PUD R W Address 0x...

Page 153: ...UDPDN R W Address 0xE020_05D4 MP2_7DRV Bit Description Initial State MP2_7DRV n 2n 1 2n n 0 7 00 1x 10 2x 01 3x 11 4x 0xAAAA 2 2 49 PORT GROUP MP2_8 CONTROL REGISTER There are six control registers namely MP2_8CON MP2_8DAT MP2_8PUD MP2_8DRV MP2_8CONPDN and MP2_8PUDPDN in the Port Group MP2_8 Control Registers MP2_8CON R W Address 0xE020_05E0 MP2_8DAT R W Address 0xE020_05E4 MP2_8PUD R W Address 0x...

Page 154: ...0 4 XjTDI JTAG TAP Controller Data Input 0 ETC0 5 XjDBGSEL JTAG selection 0 CORTEXA8 Core JTAG 1 Peripherals JTAG 0 2 2 50 1 Port Group ETC0 Control Register ETC0PUD R W Address 0xE020_0608 ETC0PUD Bit Description Initial State ETC0PUD 2n 1 2n n 4 5 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x00 ETC0PUD m 2m 1 2m m 0 3 Reserved fixed ETC0PUD 0 Pull down ETC0PUD 1...

Page 155: ...ignal 3 0 ETC1 4 XOM 4 Operating Mode control signal 4 0 ETC1 5 XOM 5 Operating Mode control signal 5 0 ETC1 6 XDDR2_SEL Selection DDR type LPDDR1 2 or DDR2 0 ETC1 7 XPWRRGTON Power Regulator enable 0 2 2 51 1 Port Group ETC1 Control Register ETC1PUD R W Address 0xE020_0628 ETC1PUD Bit Description Initial State ETC1PUD n 2n 1 2n n 0 5 Reserved fixed ETC1PUD 0 Disable ETC1PUD 1 Disable ETC1PUD 2 Di...

Page 156: ...C1DRV R W Address 0xE020_062C ETC1DRV Bit Description Initial State ETC1DRV n 2n 1 2n n 0 5 Reserved fixed ETC1DRV 0 01 3x ETC1DRV 1 01 3x ETC1DRV 2 01 3x ETC1DRV 3 01 3x ETC1DRV 4 01 3x ETC1DRV 5 01 3x ETC1DRV 6 13 12 00 1x 10 2x 01 3x 11 4x 0x0 ETC1DRV 7 15 14 Reserved fixed ETC1DRV 7 11 4x ...

Page 157: ...nWRESET System Warm Reset 0 ETC2 4 RTC_CLKOUT RTC Clock out 0 ETC2 5 XuotgDRVVBUS USB OTG charge pump enable 0 ETC2 6 XuhostPWREN USB HOST charge pump enable 0 ETC2 7 XuhostOVERCUR USB HOST oevercurrent flag 0 2 2 52 1 Port Group ETC2 Control Register ETC2PUD R W Address 0xE020_0648 ETC2PUD Bit Description Initial State ETC2PUD n 2n 1 2n n 0 4 Reserved fixed ETC2PUD 0 Disable ETC2PUD 1 Disable ETC...

Page 158: ...TC2DRV R W Address 0xE020_064C ETC2DRV Bit Description Initial State ETC2DRV 0 1 0 Reserved fixed ETC2DRV 0 01 3x ETC2DRV 1 3 2 00 1x 10 2x 01 3x 11 4x 00 ETC2DRV n 2n 1 2n n 2 4 Reserved fixed ETC2DRV 2 11 4x ETC2DRV 3 01 3x ETC2DRV 4 10 2x ETC2DRV m 2m 1 2m m 7 5 00 1x 10 2x 01 3x 11 4x 0x0 ...

Page 159: ... table below ETC4 Pin Name Description Initial State ETC4 0 XrtcXTI 32 KHz crystal input for RTC 0 ETC4 1 XrtcXTO 32 KHz crystal output for RTC 0 ETC4 2 XXTI Crystal input for internal OSC circuit 0 ETC4 3 XXTO Crystal output for internal OSC circuit 0 ETC4 4 XusbXTI Crystal input for internal USB circuit 0 ETC4 5 XusbXTO Crystal output for internal USB circuit 0 ...

Page 160: ... use interrupt function set either delay or digital filter enabled in order to detect interrupt If filter is disabled there is strong probability that system detects all interrupt from successive interrupts Some interrupt detection will be missed To detect all interrupts stably you had better set filter enable GPIO Interrupt cannot use for wake up source For wake up interrupt source you can use Ex...

Page 161: ... GPJ0_INT_CON 0xE020_0744 R W GPIO Interrupt GPJ0_INT Configuration Register 0x0 GPJ1_INT_CON 0xE020_0748 R W GPIO Interrupt GPJ1_INT Configuration Register 0x0 GPJ2_INT_CON 0xE020_074C R W GPIO Interrupt GPJ2_INT Configuration Register 0x0 GPJ3_INT_CON 0xE020_0750 R W GPIO Interrupt GPJ3_INT Configuration Register 0x0 GPJ4_INT_CON 0xE020_0754 R W GPIO Interrupt GPJ4_INT Configuration Register 0x0...

Page 162: ...ter Configuration Register 1 0x0 GPE1_INT_FLTCON0 0xE020_0840 R W GPIO Interrupt GPE1_INT Filter Configuration Register 0 0x0 GPE1_INT_FLTCON1 0xE020_0844 R W GPIO Interrupt GPE1_INT Filter Configuration Register 1 0x0 GPF0_INT_FLTCON0 0xE020_0848 R W GPIO Interrupt GPF0_INT Filter Configuration Register 0 0x0 GPF0_INT_FLTCON1 0xE020_084C R W GPIO Interrupt GPF0_INT Filter Configuration Register 1...

Page 163: ...r Configuration Register 1 0x0 GPJ2_INT_FLTCON0 0xE020_0898 R W GPIO Interrupt GPJ2_INT Filter Configuration Register 0 0x0 GPJ2_INT_FLTCON1 0xE020_089C R W GPIO Interrupt GPJ2_INT Filter Configuration Register 1 0x0 GPJ3_INT_FLTCON0 0xE020_08A0 R W GPIO Interrupt GPJ3_INT Filter Configuration Register 0 0x0 GPJ3_INT_FLTCON1 0xE020_08A4 R W GPIO Interrupt GPJ3_INT Filter Configuration Register 1 0...

Page 164: ...4C R W GPIO Interrupt GPJ2_INT Mask Register 0x000000FF GPJ3_INT_MASK 0xE020_0950 R W GPIO Interrupt GPJ3_INT Mask Register 0x000000FF GPJ4_INT_MASK 0xE020_0954 R W GPIO Interrupt GPJ4_INT Mask Register 0x0000001F GPA0_INT_PEND 0xE020_0A00 R W GPIO Interrupt GPA0_INT Pending Register 0x0 GPA1_INT_PEND 0xE020_0A04 R W GPIO Interrupt GPA1_INT Pending Register 0x0 GPB_INT_PEND 0xE020_0A08 R W GPIO In...

Page 165: ...riority Control Register 0x0 GPIO_INT_PRIORITY 0xE020_0B04 R W GPIO Interrupt Priority Control Register 0x00 GPIO_INT_SERVICE 0xE020_0B08 R Current Service Register 0x00 GPIO_INT_SERVICE_P END 0xE020_0B0C R Current Service Pending Register 0x00 GPIO_INT_GRPFIXPRI 0xE020_0B10 R W GPIO Interrupt Group Fixed Priority Control Register 0x00 GPA0_INT_FIXPRI 0xE020_0B14 R W GPIO Interrupt 1 Fixed Priorit...

Page 166: ... R W GPIO Interrupt 14 Fixed Priority Control Register 0x00 GPG1_INT_FIXPRI 0xE020_0B4C R W GPIO Interrupt 15 Fixed Priority Control Register 0x00 GPG2_INT_FIXPRI 0xE020_0B50 R W GPIO Interrupt 16 Fixed Priority Control Register 0x00 GPG3_INT_FIXPRI 0xE020_0B54 R W GPIO Interrupt 17 Fixed Priority Control Register 0x00 GPJ0_INT_FIXPRI 0xE020_0B58 R W GPIO Interrupt 18 Fixed Priority Control Regist...

Page 167: ...rved 000 Reserved 23 Reserved 0 GPA0_INT_CON 5 22 20 Sets the signaling method of GPA0_INT 5 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPA0_INT_CON 4 18 16 Sets the signaling method of GPA0_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge ...

Page 168: ...NT_CON 1 6 4 Sets the signaling method of GPA0_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 GPA0_INT_CON 0 2 0 Sets the signaling method of GPA0_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 169: ... 11 Reserved 0 GPA1_INT_CON 2 10 8 Sets the signaling method of GPA1_INT 2 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 7 Reserved 0 GPA1_INT_CON 1 6 4 Sets the signaling method of GPA1_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Res...

Page 170: ...erved 23 Reserved 0 GPB_INT_CON 5 22 20 Sets the signaling method of GPB_INT 5 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPB_INT_CON 4 18 16 Sets the signaling method of GPB_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 11...

Page 171: ... Sets the signaling method of GPB_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 GPB_INT_CON 0 2 0 Sets the signaling method of GPB_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 172: ...10 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 11 Reserved 0 GPC0_INT_CON 2 10 8 Sets the signaling method of GPC0_INT 2 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 7 Reserved 0 GPC0_INT_CON 1 6 4 Sets the signaling method of GPC0_INT 1 000 Low leve...

Page 173: ...10 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 11 Reserved 0 GPC1_INT_CON 2 10 8 Sets the signaling method of GPC1_INT 2 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 7 Reserved 0 GPC1_INT_CON 1 6 4 Sets the signaling method of GPC1_INT 1 000 Low leve...

Page 174: ... 11 Reserved 0 GPD0_INT_CON 2 10 8 Sets the signaling method of GPD0_INT 2 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 7 Reserved 0 GPD0_INT_CON 1 6 4 Sets the signaling method of GPD0_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Res...

Page 175: ... 15 Reserved 0 GPD1_INT_CON 3 14 12 Sets the signaling method of GPD1_INT 3 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 11 Reserved 0 GPD1_INT_CON 2 10 8 Sets the signaling method of GPD1_INT 2 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 ...

Page 176: ...d 101 111 Reserved 000 Reserved 23 Reserved 0 GPE0_INT_CON 5 22 20 Sets the signaling method of GPE0_INT 5 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPE0_INT_CON 4 18 16 Sets the signaling method of GPE0_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered ...

Page 177: ...erved 0 GPE0_INT_CON 1 6 4 Sets the signaling method of GPE0_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 GPE0_INT_CON 0 2 0 Sets the signaling method of GPE0_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 00...

Page 178: ...10 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 11 Reserved 0 GPE1_INT_CON 2 10 8 Sets the signaling method of GPE1_INT 2 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 7 Reserved 0 GPE1_INT_CON 1 6 4 Sets the signaling method of GPE1_INT 1 000 Low leve...

Page 179: ...erved 23 Reserved 0 GPF0_INT_CON 5 22 20 Sets the signaling method of GPF0_INT 5 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPF0_INT_CON 4 18 16 Sets the signaling method of GPF0_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 10...

Page 180: ...Sets the signaling method of GPF0_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 GPF0_INT_CON 0 2 0 Sets the signaling method of GPF0_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 181: ...erved 23 Reserved 0 GPF1_INT_CON 5 22 20 Sets the signaling method of GPF1_INT 5 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPF1_INT_CON 4 18 16 Sets the signaling method of GPF1_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 10...

Page 182: ...Sets the signaling method of GPF1_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 GPF1_INT_CON 0 2 0 Sets the signaling method of GPF1_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 183: ...erved 23 Reserved 0 GPF2_INT_CON 5 22 20 Sets the signaling method of GPF2_INT 5 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPF2_INT_CON 4 18 16 Sets the signaling method of GPF2_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 10...

Page 184: ...Sets the signaling method of GPF2_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 GPF2_INT_CON 0 2 0 Sets the signaling method of GPF2_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 185: ... 15 Reserved 0 GPF3_INT_CON 3 14 12 Sets the signaling method of GPF3_INT 3 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 11 Reserved 0 GPF3_INT_CON 2 10 8 Sets the signaling method of GPF3_INT 2 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 ...

Page 186: ...h edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPG0_INT_CON 4 18 16 Sets the signaling method of GPG0_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 15 Reserved 0 GPG0_INT_CON 3 14 12 Sets the signaling method of GPG0_INT 3 000 Low level 001 High level 010 Falling edge triggered 011 Rising ...

Page 187: ...Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved Reserved 3 Reserved 0 GPG0_INT_CON 0 2 0 Sets the signaling method of GPG0_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 188: ...h edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPG1_INT_CON 4 18 16 Sets the signaling method of GPG1_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 15 Reserved 0 GPG1_INT_CON 3 14 12 Sets the signaling method of GPG1_INT 3 000 Low level 001 High level 010 Falling edge triggered 011 Rising ...

Page 189: ...Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved Reserved 3 Reserved 0 GPG1_INT_CON 0 2 0 Sets the signaling method of GPG1_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 190: ...h edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPG2_INT_CON 4 18 16 Sets the signaling method of GPG2_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 15 Reserved 0 GPG2_INT_CON 3 14 12 Sets the signaling method of GPG2_INT 3 000 Low level 001 High level 010 Falling edge triggered 011 Rising ...

Page 191: ...Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved Reserved 3 Reserved 0 GPG2_INT_CON 0 2 0 Sets the signaling method of GPG2_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 192: ...h edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPG3_INT_CON 4 18 16 Sets the signaling method of GPG3_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 15 Reserved 0 GPG3_INT_CON 3 14 12 Sets the signaling method of GPG3_INT 3 000 Low level 001 High level 010 Falling edge triggered 011 Rising ...

Page 193: ...Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved Reserved 3 Reserved 0 GPG3_INT_CON 0 2 0 Sets the signaling method of GPG3_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 194: ...erved 23 Reserved 0 GPJ0_INT_CON 5 22 20 Sets the signaling method of GPJ0_INT 5 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPJ0_INT_CON 4 18 16 Sets the signaling method of GPJ0_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 10...

Page 195: ...Sets the signaling method of GPJ0_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 GPJ0_INT_CON 0 2 0 Sets the signaling method of GPJ0_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 196: ... 15 Reserved 0 GPJ1_INT_CON 3 14 12 Sets the signaling method of GPJ1_INT 3 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 11 Reserved 0 GPJ1_INT_CON 2 10 8 Sets the signaling method of GPJ1_INT 2 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 ...

Page 197: ...erved 23 Reserved 0 GPJ2_INT_CON 5 22 20 Sets the signaling method of GPJ2_INT 5 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPJ2_INT_CON 4 18 16 Sets the signaling method of GPJ2_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 10...

Page 198: ...Sets the signaling method of GPJ2_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 GPJ2_INT_CON 0 2 0 Sets the signaling method of GPJ2_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 199: ...erved 23 Reserved 0 GPJ3_INT_CON 5 22 20 Sets the signaling method of GPJ3_INT 5 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 GPJ3_INT_CON 4 18 16 Sets the signaling method of GPJ3_INT 4 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 10...

Page 200: ...Sets the signaling method of GPJ3_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 GPJ3_INT_CON 0 2 0 Sets the signaling method of GPJ3_INT 0 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 201: ...010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 11 Reserved 0 GPJ4_INT_CON 2 10 8 Sets the signaling method of GPJ4_INT 2 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 7 Reserved 0 GPJ4_INT_CON 1 6 4 Sets the signaling method of GPJ4_INT 1 000 Low lev...

Page 202: ... 3 This value is valid when FLTSEL1is 1 0 FLTEN1 2 23 Filter Enable for GPA0_INT 2 0 Disables 1 Enables 0 FLTWIDTH1 2 22 16 Filtering width of GPA0_INT 2 This value is valid when FLTSEL1is 1 0 FLTEN1 1 15 Filter Enable for GPA0_INT 1 0 Disables 1 Enables 0 FLTWIDTH1 1 14 8 Filtering width of GPA0_INT 1 This value is valid when FLTSEL1is 1 0 FLTEN1 0 7 Filter Enable for GPA0_INT 0 0 Disables 1 Enab...

Page 203: ... 7 This value is valid when FLTSEL1is 1 0 FLTEN1 6 23 Filter Enable for GPA0_INT 6 0 Disables 1 Enables 0 FLTWIDTH1 6 22 16 Filtering width of GPA0_INT 6 This value is valid when FLTSEL1is 1 0 FLTEN1 5 15 Filter Enable for GPA0_INT 5 0 Disables 1 Enables 0 FLTWIDTH1 5 14 8 Filtering width of GPA0_INT 5 This value is valid when FLTSEL1is 1 0 FLTEN1 4 7 Filter Enable for GPA0_INT 4 0 Disables 1 Enab...

Page 204: ...NT 2 0 Disables 1 Enables 0 FLTWIDTH2 2 22 16 Filtering width of GPA1_INT 2 This value is valid when FLTSEL2is 1 0 FLTEN2 1 15 Filter Enable for GPA1_INT 1 0 Disables 1 Enables 0 FLTWIDTH2 1 14 8 Filtering width of GPA1_INT 1 This value is valid when FLTSEL2is 1 0 FLTEN2 0 7 Filter Enable for GPA1_INT 0 0 Disables 1 Enables 0 FLTWIDTH2 0 6 0 Filtering width of GPA1_INT 0 This value is valid when F...

Page 205: ...3 This value is valid when FLTSEL3 is 1 0 FLTEN3 2 23 Filter Enable for GPB_INT 2 0 Disables 1 Enables 0 FLTWIDTH3 2 22 16 Filtering width of GPB_INT 2 This value is valid when FLTSEL3 is 1 0 FLTEN3 1 15 Filter Enable for GPB_INT 1 0 Disables 1 Enables 0 FLTWIDTH3 1 14 8 Filtering width of GPB_INT 1 This value is valid when FLTSEL3 is 1 0 FLTEN3 0 7 Filter Enable for GPB_INT 0 0 Disables 1 Enables...

Page 206: ...7 This value is valid when FLTSEL3 is 1 0 FLTEN3 6 23 Filter Enable for GPB_INT 6 0 Disables 1 Enables 0 FLTWIDTH3 6 22 16 Filtering width of GPB_INT 6 This value is valid when FLTSEL3 is 1 0 FLTEN3 5 15 Filter Enable for GPB_INT 5 0 Disables 1 Enables 0 FLTWIDTH3 5 14 8 Filtering width of GPB_INT 5 This value is valid when FLTSEL3 is 1 0 FLTEN3 4 7 Filter Enable for GPB_INT 4 0 Disables 1 Enables...

Page 207: ...This value is valid when FLTSEL4 is 1 0 FLTEN4 1 15 Filter Enable for GPC0_INT 1 0 Disables 1 Enables 0 FLTWIDTH4 1 14 8 Filtering width of GPC0_INT 1 This value is valid when FLTSEL4 is 1 0 FLTEN4 0 7 Filter Enable for GPC0_INT 0 0 Disables 1 Enables 0 FLTWIDTH4 0 6 0 Filtering width of GPC0_INT 0 This value is valid when FLTSEL4 is 1 0 2 2 55 30 GPIO Interrupt Control Registers GPC0_INT_FLTCON1 ...

Page 208: ...This value is valid when FLTSEL5 is 1 0 FLTEN5 1 15 Filter Enable for GPC1_INT 1 0 Disables 1 Enables 0 FLTWIDTH5 1 14 8 Filtering width of GPC1_INT 1 This value is valid when FLTSEL5 is 1 0 FLTEN5 0 7 Filter Enable for GPC1_INT 0 0 Disables 1 Enables 0 FLTWIDTH5 0 6 0 Filtering width of GPC1_INT 0 This value is valid when FLTSEL5 is 1 0 2 2 55 32 GPIO Interrupt Control Registers GPC1_INT_FLTCON1 ...

Page 209: ...T 2 0 Disables 1 Enables 0 FLTWIDTH6 2 22 16 Filtering width of GPD0_INT 2 This value is valid when FLTSEL6 is 1 0 FLTEN6 1 15 Filter Enable for GPD0_INT 1 0 Disables 1 Enables 0 FLTWIDTH6 1 14 8 Filtering width of GPD0_INT 1 This value is valid when FLTSEL6 is 1 0 FLTEN6 0 7 Filter Enable for GPD0_INT 0 0 Disables 1 Enables 0 FLTWIDTH6 0 6 0 Filtering width of GPD0_INT 0 This value is valid when ...

Page 210: ...INT 1 0 Disables 1 Enables 0 FLTWIDTH7 1 14 8 Filtering width of GPD1_INT 1 This value is valid when FLTSEL7 is 1 0 FLTEN7 0 7 Filter Enable for GPD1_INT 0 0 Disables 1 Enables 0 FLTWIDTH7 0 6 0 Filtering width of GPD1_INT 0 This value is valid when FLTSEL7 is 1 0 2 2 55 36 GPIO Interrupt Control Registers GPD1_INT_FLTCON1 R W Address 0xE020_0834 GPD1_INT_FLTCON1 Bit Description Initial State Rese...

Page 211: ... This value is valid when FLTSEL8 is 1 0 FLTEN8 2 23 Filter Enable for GPE0_INT 2 0 Disables 1 Enables 0 FLTWIDTH8 2 22 16 Filtering width of GPE0_INT 2 This value is valid when FLTSEL8 is 1 0 FLTEN8 1 15 Filter Enable for GPE0_INT 1 0 Disables 1 Enables 0 FLTWIDTH8 1 14 8 Filtering width of GPE0_INT 1 This value is valid when FLTSEL8 is 1 0 FLTEN8 0 7 Filter Enable for GPE0_INT 0 0 Disables 1 Ena...

Page 212: ... This value is valid when FLTSEL8 is 1 0 FLTEN8 6 23 Filter Enable for GPE0_INT 6 0 Disables 1 Enables 0 FLTWIDTH8 6 22 16 Filtering width of GPE0_INT 6 This value is valid when FLTSEL8 is 1 0 FLTEN8 5 15 Filter Enable for GPE0_INT 5 0 Disables 1 Enables 0 FLTWIDTH8 5 14 8 Filtering width of GPE0_INT 5 This value is valid when FLTSEL8is 1 0 FLTEN8 4 7 Filter Enable for GPE0_INT 4 0 Disables 1 Enab...

Page 213: ...This value is valid when FLTSEL9 is 1 0 FLTEN9 1 15 Filter Enable for GPE1_INT 1 0 Disables 1 Enables 0 FLTWIDTH9 1 14 8 Filtering width of GPE1_INT 1 This value is valid when FLTSEL9 is 1 0 FLTEN9 0 7 Filter Enable for GPE1_INT 0 0 Disables 1 Enables 0 FLTWIDTH9 0 6 0 Filtering width of GPE1_INT 0 This value is valid when FLTSEL9 is 1 0 2 2 55 40 GPIO Interrupt Control Registers GPE1_INT_FLTCON1 ...

Page 214: ...s value is valid when FLTSEL10 is 1 0 FLTEN10 2 23 Filter Enable for GPF0_INT 2 0 Disables 1 Enables 0 FLTWIDTH10 2 22 16 Filtering width of GPF0_INT 2 This value is valid when FLTSEL10 is 1 0 FLTEN10 1 15 Filter Enable for GPF0_INT 1 0 Disables 1 Enables 0 FLTWIDTH10 1 14 8 Filtering width of GPF0_INT 1 This value is valid when FLTSEL10 is 1 0 FLTEN10 0 7 Filter Enable for GPF0_INT 0 0 Disables 1...

Page 215: ...s value is valid when FLTSEL10 is 1 0 FLTEN10 6 23 Filter Enable for GPF0_INT 6 0 Disables 1 Enables 0 FLTWIDTH10 6 22 16 Filtering width of GPF0_INT 6 This value is valid when FLTSEL10 is 1 0 FLTEN10 5 15 Filter Enable for GPF0_INT 5 0 Disables 1 Enables 0 FLTWIDTH10 5 14 8 Filtering width of GPF0_INT 5 This value is valid when FLTSEL10 is 1 0 FLTEN10 4 7 Filter Enable for GPF0_INT 4 0 Disables 1...

Page 216: ...s value is valid when FLTSEL11 is 1 0 FLTEN11 2 23 Filter Enable for GPF1_INT 2 0 Disables 1 Enables 0 FLTWIDTH11 2 22 16 Filtering width of GPF1_INT 2 This value is valid when FLTSEL11 is 1 0 FLTEN11 1 15 Filter Enable for GPF1_INT 1 0 Disables 1 Enables 0 FLTWIDTH11 1 14 8 Filtering width of GPF1_INT 1 This value is valid when FLTSEL11 is 1 0 FLTEN11 0 7 Filter Enable for GPF1_INT 0 0 Disables 1...

Page 217: ...s value is valid when FLTSEL11 is 1 0 FLTEN11 6 23 Filter Enable for GPF1_INT 6 0 Disables 1 Enables 0 FLTWIDTH11 6 22 16 Filtering width of GPF1_INT 6 This value is valid when FLTSEL11 is 1 0 FLTEN11 5 15 Filter Enable for GPF1_INT 5 0 Disables 1 Enables 0 FLTWIDTH11 5 14 8 Filtering width of GPF1_INT 5 This value is valid when FLTSEL11 is 1 0 FLTEN11 4 7 Filter Enable for GPF1_INT 4 0 Disables 1...

Page 218: ...s value is valid when FLTSEL12 is 1 0 FLTEN12 2 23 Filter Enable for GPF2_INT 2 0 Disables 1 Enables 0 FLTWIDTH12 2 22 16 Filtering width of GPF2_INT 2 This value is valid when FLTSEL12 is 1 0 FLTEN12 1 15 Filter Enable for GPF2_INT 1 0 Disables 1 Enables 0 FLTWIDTH12 1 14 8 Filtering width of GPF2_INT 1 This value is valid when FLTSEL12 is 1 0 FLTEN12 0 7 Filter Enable for GPF2_INT 0 0 Disables 1...

Page 219: ...s value is valid when FLTSEL12 is 1 0 FLTEN12 6 23 Filter Enable for GPF2_INT 6 0 Disables 1 Enables 0 FLTWIDTH12 6 22 16 Filtering width of GPF2_INT 6 This value is valid when FLTSEL12 is 1 0 FLTEN12 5 15 Filter Enable for GPF2_INT 5 0 Disables 1 Enables 0 FLTWIDTH12 5 14 8 Filtering width of GPF2_INT 5 This value is valid when FLTSEL12 is 1 0 FLTEN12 4 7 Filter Enable for GPF2_INT 4 0 Disables 1...

Page 220: ... 1 0 Disables 1 Enables 0 FLTWIDTH13 1 14 8 Filtering width of GPF3_INT 1 This value is valid when FLTSEL13 is 1 0 FLTEN13 0 7 Filter Enable for GPF3_INT 0 0 Disables 1 Enables 0 FLTWIDTH13 0 6 0 Filtering width of GPF3_INT 0 This value is valid when FLTSEL13 is 1 0 2 2 55 48 GPIO Interrupt Control Registers GPF3_INT_FLTCON1 R W Address 0xE020_0864 GPF3_INT_FLTCON1 Bit Description Initial State Re...

Page 221: ...s value is valid when FLTSEL14 is 1 0 FLTEN14 0 7 Filter Enable for GPG0_INT 0 0 Disables 1 Enables 0 FLTWIDTH14 0 6 0 Filtering width of GPG0_INT 0 This value is valid when FLTSEL14 is 1 0 2 2 55 50 GPIO Interrupt Control Registers GPG0_INT_FLTCON1 R W Address 0xE020_086C GPG0_INT_FLTCON1 Bit Description Initial State Reserved 31 24 Reserved 0 FLTEN14 6 23 Filter Enable for GPG0_INT 6 0 Disables ...

Page 222: ...s value is valid when FLTSEL15 is 1 0 FLTEN15 0 7 Filter Enable for GPG1_INT 0 0 Disables 1 Enables 0 FLTWIDTH15 0 6 0 Filtering width of GPG1_INT 0 This value is valid when FLTSEL15is 1 0 2 2 55 52 GPIO Interrupt Control Registers GPG1_INT_FLTCON1 R W Address 0xE020_0874 GPG1_INT_FLTCON1 Bit Description Initial State Reserved 31 24 Reserved 0 FLTEN15 6 23 Filter Enable for GPG1_INT 6 0 Disables 1...

Page 223: ...s value is valid when FLTSEL16 is 1 0 FLTEN16 0 7 Filter Enable for GPG2_INT 0 0 Disables 1 Enables 0 FLTWIDTH16 0 6 0 Filtering width of GPG2_INT 0 This value is valid when FLTSEL16 is 1 0 2 2 55 54 GPIO Interrupt Control Registers GPG2_INT_FLTCON1 R W Address 0xE020_087C GPG2_INT_FLTCON1 Bit Description Initial State Reserved 31 24 Reserved 0 FLTEN16 6 23 Filter Enable for GPG2_INT 6 0 Disables ...

Page 224: ...s value is valid when FLTSEL17 is 1 0 FLTEN17 0 7 Filter Enable for GPG3_INT 0 0 Disables 1 Enables 0 FLTWIDTH17 0 6 0 Filtering width of GPG3_INT 0 This value is valid when FLTSEL17 is 1 0 2 2 55 56 GPIO Interrupt Control Registers GPG3_INT_FLTCON1 R W Address 0xE020_0884 GPG3_INT_FLTCON1 Bit Description Initial State Reserved 31 24 Reserved 0 FLTEN17 6 23 Filter Enable for GPG3_INT 6 0 Disables ...

Page 225: ...s value is valid when FLTSEL18 is 1 0 FLTEN18 2 23 Filter Enable for GPJ0_INT 2 0 Disables 1 Enables 0 FLTWIDTH18 2 22 16 Filtering width of GPJ0_INT 2 This value is valid when FLTSEL18 is 1 0 FLTEN18 1 15 Filter Enable for GPJ0_INT 1 0 Disables 1 Enables 0 FLTWIDTH18 1 14 8 Filtering width of GPJ0_INT 1 This value is valid when FLTSEL18 is 1 0 FLTEN18 0 7 Filter Enable for GPJ0_INT 0 0 Disables 1...

Page 226: ...s value is valid when FLTSEL18 is 1 0 FLTEN18 6 23 Filter Enable for GPJ0_INT 6 0 Disables 1 Enables 0 FLTWIDTH18 6 22 16 Filtering width of GPJ0_INT 6 This value is valid when FLTSEL18 is 1 0 FLTEN18 5 15 Filter Enable for GPJ0_INT 5 0 Disables 1 Enables 0 FLTWIDTH18 5 14 8 Filtering width of GPJ0_INT 5 This value is valid when FLTSEL18 is 1 0 FLTEN18 4 7 Filter Enable for GPJ0_INT 4 0 Disables 1...

Page 227: ... 0 Disables 1 Enables 0 FLTWIDTH19 1 14 8 Filtering width of GPJ1_INT 1 This value is valid when FLTSEL19 is 1 0 FLTEN19 0 7 Filter Enable for GPJ1_INT 0 0 Disables 1 Enables 0 FLTWIDTH19 0 6 0 Filtering width of GPJ1_INT 0 This value is valid when FLTSEL19 is 1 0 2 2 55 60 GPIO Interrupt Control Registers GPJ1_INT_FLTCON1 R W Address 0xE020_0894 GPJ1_INT_FLTCON1 Bit Description Initial State Rese...

Page 228: ...s value is valid when FLTSEL20 is 1 0 FLTEN20 2 23 Filter Enable for GPJ2_INT 2 0 Disables 1 Enables 0 FLTWIDTH20 2 22 16 Filtering width of GPJ2_INT 2 This value is valid when FLTSEL20 is 1 0 FLTEN20 1 15 Filter Enable for GPJ2_INT 1 0 Disables 1 Enables 0 FLTWIDTH20 1 14 8 Filtering width of GPJ2_INT 1 This value is valid when FLTSEL20 is 1 0 FLTEN20 0 7 Filter Enable for GPJ2_INT 0 0 Disables 1...

Page 229: ...s value is valid when FLTSEL20 is 1 0 FLTEN20 6 23 Filter Enable for GPJ2_INT 6 0 Disables 1 Enables 0 FLTWIDTH20 6 22 16 Filtering width of GPJ2_INT 6 This value is valid when FLTSEL20 is 1 0 FLTEN20 5 15 Filter Enable for GPJ2_INT 5 0 Disables 1 Enables 0 FLTWIDTH20 5 14 8 Filtering width of GPJ2_INT 5 This value is valid when FLTSEL20 is 1 0 FLTEN20 4 7 Filter Enable for GPJ2_INT 4 0 Disables 1...

Page 230: ...s value is valid when FLTSEL21 is 1 0 FLTEN21 2 23 Filter Enable for GPJ3_INT 2 0 Disables 1 Enables 0 FLTWIDTH21 2 22 16 Filtering width of GPJ3_INT 2 This value is valid when FLTSEL21 is 1 0 FLTEN21 1 15 Filter Enable for GPJ3_INT 1 0 Disables 1 Enables 0 FLTWIDTH21 1 14 8 Filtering width of GPJ3_INT 1 This value is valid when FLTSEL21 is 1 0 FLTEN21 0 7 Filter Enable for GPJ3_INT 0 0 Disables 1...

Page 231: ...s value is valid when FLTSEL21 is 1 0 FLTEN21 6 23 Filter Enable for GPJ3_INT 6 0 Disables 1 Enables 0 FLTWIDTH21 6 22 16 Filtering width of GPJ3_INT 6 This value is valid when FLTSEL21 is 1 0 FLTEN21 5 15 Filter Enable for GPJ3_INT 5 0 Disables 1 Enables 0 FLTWIDTH21 5 14 8 Filtering width of GPJ3_INT 5 This value is valid when FLTSEL21 is 1 0 FLTEN21 4 7 Filter Enable for GPJ3_INT 4 0 Disables 1...

Page 232: ...is value is valid when FLTSEL22 is 1 0 FLTEN22 1 15 Filter Enable for GPJ4_INT 1 0 Disables 1 Enables 0 FLTWIDTH22 1 14 8 Filtering width of GPJ4_INT 1 This value is valid when FLTSEL22 is 1 0 FLTEN22 0 7 Filter Enable for GPJ4_INT 0 0 Disables 1 Enables 0 FLTWIDTH22 0 6 0 Filtering width of GPJ4_INT 0 This value is valid when FLTSEL22 is 1 0 2 2 55 66 GPIO Interrupt Control Registers GPJ4_INT_FLT...

Page 233: ...ables Interrupt 1 Masked 1 GPA0_INT_MASK 3 3 0 Enables Interrupt 1 Masked 1 GPA0_INT_MASK 2 2 0 Enables Interrupt 1 Masked 1 GPA0_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPA0_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 55 68 GPIO Interrupt Control Registers GPA1_INT_MASK R W Address 0xE020_0904 GPA1_INT_MASK Bit Description Initial State Reserved 31 4 Reserved 0 GPA1_INT_MASK 3 3 0 Enables...

Page 234: ...rved 0 GPB_INT_MASK 7 7 0 Enables Interrupt 1 Masked 1 GPB_INT_MASK 6 6 0 Enables Interrupt 1 Masked 1 GPB_INT_MASK 5 5 0 Enables Interrupt 1 Masked 1 GPB_INT_MASK 4 4 0 Enables Interrupt 1 Masked 1 GPB_INT_MASK 3 3 0 Enables Interrupt 1 Masked 1 GPB_INT_MASK 2 2 0 Enables Interrupt 1 Masked 1 GPB_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPB_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 ...

Page 235: ...ables Interrupt 1 Masked 1 GPC0_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPC0_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 55 71 GPIO Interrupt Control Registers GPC1_INT_MASK R W Address 0xE020_0910 GPC1_INT_MASK Bit Description Initial State Reserved 31 5 Reserved 0 GPC1_INT_MASK 4 4 0 Enables Interrupt 1 Masked 1 GPC1_INT_MASK 3 3 0 Enables Interrupt 1 Masked 1 GPC1_INT_MASK 2 2 0 Enables...

Page 236: ...ables Interrupt 1 Masked 1 GPD0_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 55 73 GPIO Interrupt Control Registers GPD1_INT_MASK R W Address 0xE020_0918 GPD1_INT_MASK Bit Description Initial State Reserved 31 6 Reserved 0 GPD1_INT_MASK 5 5 0 Enables Interrupt 1 Masked 1 GPD1_INT_MASK 4 4 0 Enables Interrupt 1 Masked 1 GPD1_INT_MASK 3 3 0 Enables Interrupt 1 Masked 1 GPD1_INT_MASK 2 2 0 Enables...

Page 237: ... 1 GPE0_INT_MASK 3 3 0 Enables Interrupt 1 Masked 1 GPE0_INT_MASK 2 2 0 Enables Interrupt 1 Masked 1 GPE0_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPE0_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 55 75 GPIO Interrupt Control Registers GPE1_INT_MASK R W Address 0xE020_0920 GPE1_INT_MASK Bit Description Initial State Reserved 31 5 Reserved 0 GPE1_INT_MASK 4 4 0 Enables Interrupt 1 Masked 1 GP...

Page 238: ...ables Interrupt 1 Masked 1 GPF0_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPF0_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 55 77 GPIO Interrupt Control Registers GPF1_INT_MASK R W Address 0xE020_0928 GPF1_INT_MASK Bit Description Initial State Reserved 31 8 Reserved 0 GPF1_INT_MASK 7 7 0 Enables Interrupt 1 Masked 1 GPF1_INT_MASK 6 6 0 Enables Interrupt 1 Masked 1 GPF1_INT_MASK 5 5 0 Enables...

Page 239: ...nables Interrupt 1 Masked 1 GPF2_INT_MASK 2 2 0 Enables Interrupt 1 Masked 1 GPF2_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPF2_INT_MASK 0 0 0 Enable Interrupt 1 Masked 1 2 2 55 79 GPIO Interrupt Control Registers GPF3_INT_MASK R W Address 0xE020_0930 GPF3_INT_MASK Bit Description Initial State Reserved 31 6 Reserved 0 GPF3_INT_MASK 5 5 0 Enables Interrupt 1 Masked 1 GPF3_INT_MASK 4 4 0 Enables...

Page 240: ...ables Interrupt 1 Masked 1 GPG0_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPG0_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 55 81 GPIO Interrupt Control Registers GPG1_INT_MASK R W Address 0xE020_0938 GPG1_INT_MASK Bit Description Initial State Reserved 31 7 Reserved 0 GPG1_INT_MASK 6 6 0 Enables Interrupt 1 Masked 1 GPG1_INT_MASK 5 5 0 Enables Interrupt 1 Masked 1 GPG1_INT_MASK 4 4 0 Enables...

Page 241: ...ables Interrupt 1 Masked 1 GPG2_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPG2_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 55 83 GPIO Interrupt Control Registers GPG3_INT_MASK R W Address 0xE020_0940 GPG3_INT_MASK Bit Description Initial State Reserved 31 7 Reserved 0 GPG3_INT_MASK 6 6 0 Enables Interrupt 1 Masked 1 GPG3_INT_MASK 5 5 0 Enables Interrupt 1 Masked 1 GPG3_INT_MASK 4 4 0 Enables...

Page 242: ...ables Interrupt 1 Masked 1 GPJ0_INT_MASK 2 2 0 Enables Interrupt 1 Masked 1 GPJ0_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPJ0_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 55 85 GPIO Interrupt Control Registers GPJ1_INT_MASK R W Address 0xE020_0948 GPJ1_INT_MASK Bit Description Initial State Reserved 31 6 Reserved 0 GPJ1_INT_MASK 5 5 0 Enables Interrupt 1 Masked 1 GPJ1_INT_MASK 4 4 0 Enables...

Page 243: ...ables Interrupt 1 Masked 1 GPJ2_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPJ2_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 55 87 GPIO Interrupt Control Registers GPJ3_INT_MASK R W Address 0xE020_0950 GPJ3_INT_MASK Bit Description Initial State Reserved 31 8 Reserved 0 GPJ3_INT_MASK 7 7 0 Enables Interrupt 1 Masked 1 GPJ3_INT_MASK 6 6 0 Enables Interrupt 1 Masked 1 GPJ3_INT_MASK 5 5 0 Enables...

Page 244: ...020_0954 GPJ4_INT_MASK Bit Description Initial State Reserved 31 5 Reserved 0 GPJ4_INT_MASK 4 4 0 Enables Interrupt 1 Masked 1 GPJ4_INT_MASK 3 3 0 Enables Interrupt 1 Masked 1 GPJ4_INT_MASK 2 2 0 Enables Interrupt 1 Masked 1 GPJ4_INT_MASK 1 1 0 Enables Interrupt 1 Masked 1 GPJ4_INT_MASK 0 0 0 Enables Interrupt 1 Masked 1 ...

Page 245: ...ccur 1 Occur interrupt 0 GPA0_INT_PEND 3 3 0 Not occur 1 Occur interrupt 0 GPA0_INT_PEND 2 2 0 Not occur 1 Occur interrupt 0 GPA0_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPA0_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 90 GPIO Interrupt Control Registers GPA1_INT_PEND R W Address 0xE020_0A04 GPA1_INT_PEND Bit Description Initial State Reserved 31 4 Reserved 0 GPA1_INT_PEND 3 3 0 Not o...

Page 246: ... 0 GPB_INT_PEND 7 7 0 Not occur 1 Occur interrupt 0 GPB_INT_PEND 6 6 0 Not occur 1 Occur interrupt 0 GPB_INT_PEND 5 5 0 Not occur 1 Occur interrupt 0 GPB_INT_PEND 4 4 0 Not occur 1 Occur interrupt 0 GPB_INT_PEND 3 3 0 Not occur 1 Occur interrupt 0 GPB_INT_PEND 2 2 0 Not occur 1 Occur interrupt 0 GPB_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPB_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 ...

Page 247: ...ccur 1 Occur interrupt 0 GPC0_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPC0_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 93 GPIO Interrupt Control Registers GPC1_INT_PEND R W Address 0xE020_0A10 GPC1_INT_PEND Bit Description Initial State Reserved 31 5 Reserved 0 GPC1_INT_PEND 4 4 0 Not occur 1 Occur interrupt 0 GPC1_INT_PEND 3 3 0 Not occur 1 Occur interrupt 0 GPC1_INT_PEND 2 2 0 Not o...

Page 248: ...ccur 1 Occur interrupt 0 GPD0_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 95 GPIO Interrupt Control Registers GPD1_INT_PEND R W Address 0xE020_0A18 GPD1_INT_PEND Bit Description Initial State Reserved 31 6 Reserved 0 GPD1_INT_PEND 5 5 0 Not occur 1 Occur interrupt 0 GPD1_INT_PEND 4 4 0 Not occur 1 Occur interrupt 0 GPD1_INT_PEND 3 3 0 Not occur 1 Occur interrupt 0 GPD1_INT_PEND 2 2 0 Not o...

Page 249: ...GPE0_INT_PEND 3 3 0 Not occur 1 Occur interrupt 0 GPE0_INT_PEND 2 2 0 Not occur 1 Occur interrupt 0 GPE0_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPE0_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 97 GPIO Interrupt Control Registers GPE1_INT_PEND R W Address 0xE020_0A20 GPE1_INT_PEND Bit Description Initial State Reserved 31 5 Reserved 0 GPE1_INT_PEND 4 4 0 Not occur 1 Occur interrupt 0 ...

Page 250: ...cur 1 Occur interrupt 0 GPF0_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPF0_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 99 GPIO Interrupt Control Registers GPF1_INT_PEND R W Address 0xE020_0A28 GPF1_INT_PEND Bit Description Initial State Reserved 31 8 Reserved 0 GPF1_INT_PEND 7 7 0 Not occur 1 Occur interrupt 0 GPF1_INT_PEND 6 6 0 Not occur 1 Occur interrupt 0 GPF1_INT_PEND 5 5 0 Not oc...

Page 251: ...cur 1 Occur interrupt 0 GPF2_INT_PEND 2 2 0 Not occur 1 Occur interrupt 0 GPF2_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPF2_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 101 GPIO Interrupt Control Registers GPF3_INT_PEND R W Address 0xE020_0A30 GPF3_INT_PEND Bit Description Initial State Reserved 31 6 Reserved 0 GPF3_INT_PEND 5 5 0 Not occur 1 Occur interrupt 0 GPF3_INT_PEND 4 4 0 Not o...

Page 252: ...cur 1 Occur interrupt 0 GPG0_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPG0_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 103 GPIO Interrupt Control Registers GPG1_INT_PEND R W Address 0xE020_0A38 GPG1_INT_PEND Bit Description Initial State Reserved 31 7 Reserved 0 GPG1_INT_PEND 6 6 0 Not occur 1 Occur interrupt 0 GPG1_INT_PEND 5 5 0 Not occur 1 Occur interrupt 0 GPG1_INT_PEND 4 4 0 Not o...

Page 253: ...ccur 1 Occur interrupt 0 GPG2_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPG2_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 105 GPIO Interrupt Control Registers GPG3_INT_PEND R W Address 0xE020_0A40 GPG3_INT_PEND Bit Description Initial State Reserved 31 7 Reserved 0 GPG3_INT_PEND 6 6 0 Not occur 1 Occur interrupt 0 GPG3_INT_PEND 5 5 0 Not occur 1 Occur interrupt 0 GPG3_INT_PEND 4 4 0 Not ...

Page 254: ...ccur 1 Occur interrupt 0 GPJ0_INT_PEND 2 2 0 Not occur 1 Occur interrupt 0 GPJ0_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPJ0_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 107 GPIO Interrupt Control Registers GPJ1_INT_PEND R W Address 0xE020_0A48 GPJ1_INT_PEND Bit Description Initial State Reserved 31 6 Reserved 0 GPJ1_INT_PEND 5 5 0 Not occur 1 Occur interrupt 0 GPJ1_INT_PEND 4 4 0 Not ...

Page 255: ...ccur 1 Occur interrupt 0 GPJ2_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPJ2_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 55 109 GPIO Interrupt Control Registers GPJ3_INT_PEND R W Address 0xE020_0A50 GPJ3_INT_PEND Bit Description Initial State Reserved 31 8 Reserved 0 GPJ3_INT_PEND 7 7 0 Not occur 1 Occur interrupt 0 GPJ3_INT_PEND 6 6 0 Not occur 1 Occur interrupt 0 GPJ3_INT_PEND 5 5 0 Not ...

Page 256: ...0_0A54 GPJ4_INT_PEND Bit Description Initial State Reserved 31 5 Reserved 0 GPJ4_INT_PEND 4 4 0 Not occur 1 Occur interrupt 0 GPJ4_INT_PEND 3 3 0 Not occur 1 Occur interrupt 0 GPJ4_INT_PEND 2 2 0 Not occur 1 Occur interrupt 0 GPJ4_INT_PEND 1 1 0 Not occur 1 Occur interrupt 0 GPJ4_INT_PEND 0 0 0 Not occur 1 Occur interrupt 0 ...

Page 257: ...t rotate Fixed 0 GPJ0_INT_PRI 17 GPJ0_INT priority rotate enable 0 Not rotate Fixed 0 GPG3_INT_PRI 16 GPG3_INT priority rotate enable 0 Not rotate Fixed 0 GPG2_INT_PRI 15 GPG2_INT priority rotate enable 0 Not rotate Fixed 0 GPG1_INT_PRI 14 GPG1_INT priority rotate enable 0 Not rotate Fixed 0 GPG0_INT_PRI 13 GPG0_INT priority rotate enable 0 Not rotate Fixed 0 GPF3_INT_PRI 12 GPF3_INT priority rota...

Page 258: ...INT priority rotate enable 0 Not rotate Fixed 0 GPC0_INT_PRI 3 GPC0_INT priority rotate enable 0 Not rotate Fixed 0 GPB_INT_PRI 2 GPB_INT priority rotate enable 0 Not rotate Fixed 0 GPA1_INT_PRI 1 GPA1_INT priority rotate enable 0 Not rotate Fixed 0 GPA0_INT_PRI 0 GPA0_INT priority rotate enable 0 Not rotate Fixed 0 ...

Page 259: ...NT 00000 0x0 GPA0_INT 00001 0x1 GPA1_INT 00010 0x2 GPB_INT 00011 0x3 GPC0_INT 00100 0x4 GPC1_INT 00101 0x5 GPD0_INT 00110 0x6 GPD1_INT 00111 0x7 GPE0_INT 01000 0x8 GPE1_INT 01001 0x9 GPF0_INT 01010 0xA GPF1_INT 01011 0xB GPF2_INT 01100 0xC GPF3_INT 01101 0xD GPG0_INT 01110 0xE GPG1_INT 01111 0xF GPG2_INT 10000 0x10 GPG3_INT 10001 0x11 GPJ0_INT 10010 0x12 GPJ1_INT 10011 0x13 GPJ2_INT 10100 0x14 GPJ...

Page 260: ..._0B0C GPIO_INT_SERVICE_PEND Bit Description Initial State Reserved 31 8 Reserved 0 SVC_PEND_Num 7 0 GPIO Interrupt Service Interrupt number 0 Not occur 1 Occur interrupt 0 7bit 0bit 0000_0001 0x1 1bit 0000_0010 0x2 2bit 0000_0100 0x4 3bit 0000_1000 0x8 4bit 0001_0000 0x10 5bit 0010_0000 0x20 6bit 0100_0000 0x40 7bit 1000_0000 0x80 0 ...

Page 261: ...1_INT 01001 0x9 GPF0_INT 01010 0xA GPF1_INT 01011 0xB GPF2_INT 01100 0xC GPF3_INT 01101 0xD GPG0_INT 01110 0xE GPG1_INT 01111 0xF GPG2_INT 10000 0x10 GPG3_INT 10001 0x11 GPJ0_INT 10010 0x12 GPJ1_INT 10011 0x13 GPJ2_INT 10100 0x14 GPJ3_INT 10101 0x15 GPJ4_INT 10110 0x16 For Example if GPC0_INT is highest priority next priority group is GPC1_INT not GPA0_INT 0 2 2 55 116 GPIO Interrupt Control Regis...

Page 262: ...ghest priority in GPA1_INT when fixed priority mode 0 7 For Example if 3 is high priority next priority interrupt is 4 not 0 0 2 2 55 118 GPIO Interrupt Control Registers GPB_INT_FIXPRI R W Address 0xE020_0B1C GPB_INT_FIXPRI Bit Description Initial State Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in GPB_INT when fixed priority mode 0 7 For Example if 3 i...

Page 263: ...ters GPC1_INT_FIXPRI R W Address 0xE020_0B24 GPC1_INT_FIXPRI Bit Description Initial State Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in GPC1_INT when fixed priority mode 0 7 For Example if 3 is high priority next priority interrupt is 4 not 0 0 2 2 55 121 GPIO Interrupt Control Registers GPD0_INT_FIXPRI R W Address 0xE020_0B28 GPD0_INT_FIXPRI Bit Descri...

Page 264: ...ters GPE0_INT_FIXPRI R W Address 0xE020_0B30 GPE0_INT_FIXPRI Bit Description Initial State Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in GPE0_INT when fixed priority mode 0 7 For Example if 3 is high priority next priority interrupt is 4 not 0 0 2 2 55 124 GPIO Interrupt Control Registers GPE1_INT_FIXPRI R W Address 0xE020_0B34 GPE1_INT_FIXPRI Bit Descri...

Page 265: ...ters GPF1_INT_FIXPRI R W Address 0xE020_0B3C GPF1_INT_FIXPRI Bit Description Initial State Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in GPF1_INT when fixed priority mode 0 7 For Example if 3 is high priority next priority interrupt is 4 not 0 0 2 2 55 127 GPIO Interrupt Control Registers GPF2_INT_FIXPRI R W Address 0xE020_0B40 GPF2_INT_FIXPRI Bit Descri...

Page 266: ...ters GPG0_INT_FIXPRI R W Address 0xE020_0B48 GPG0_INT_FIXPRI Bit Description Initial State Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in GPG0_INT when fixed priority mode 0 7 For Example if 3 is high priority next priority interrupt is 4 not 0 0 2 2 55 130 GPIO Interrupt Control Registers GPG1_INT_FIXPRI R W Address 0xE020_0B4C GPG1_INT_FIXPRI Bit Descri...

Page 267: ...ters GPG3_INT_FIXPRI R W Address 0xE020_0B54 GPG3_INT_FIXPRI Bit Description Initial State Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in GPG3_INT when fixed priority mode 0 7 For Example if 3 is high priority next priority interrupt is 4 not 0 0 2 2 55 133 GPIO Interrupt Control Registers GPJ0_INT_FIXPRI R W Address 0xE020_0B58 GPJ0_INT_FIXPRI Bit Descri...

Page 268: ...est priority in GPJ2_INT when fixed priority mode 0 7 For Example if 3 is high priority next priority interrupt is 4 not 0 0 2 2 55 136 GPIO Interrupt Control Registers GPJ3_INT_FIXPRI R W Address 0xE020_0B64 GPJ3_INT_FIXPRI Bit Description Initial State Reserved 31 3 Reserved 0 Highest_EINT_NUM 2 0 Interrupt number of the highest priority in GPJ3_INT when fixed priority mode 0 7 For Example if 3 ...

Page 269: ...ut 0010 1110 Reserved 1111 EXT_INT 0 0000 GPH0CON 1 7 4 0000 Input 0001 Output 0010 1110 Reserved 1111 EXT_INT 1 0000 GPH0CON 2 11 8 0000 Input 0001 Output 0010 1110 Reserved 1111 EXT_INT 2 0000 GPH0CON 3 15 12 0000 Input 0001 Output 0010 1110 Reserved 1111 EXT_INT 3 0000 GPH0CON 4 19 16 0000 Input 0001 Output 0010 1110 Reserved 1111 EXT_INT 4 0000 GPH0CON 5 23 20 0000 Input 0001 Output 0010 1110 ...

Page 270: ...ate is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00 2 2 56 3 Port Group GPH0 Control Register GPH0PUD R W Address 0xE020_0C08 GPH0PUD Bit Description Initial State GPH0PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x5555 2 2 56 4 Port Group GPH0 Control Register GPH0DRV R W A...

Page 271: ... 0000 GPH1CON 1 7 4 0000 Input 0001 Output 0010 1110 Reserved 1111 EXT_INT 9 0000 GPH1CON 2 11 8 0000 Input 0001 Output 0010 1110 Reserved 1111 EXT_INT 10 0000 GPH1CON 3 15 12 0000 Input 0001 Output 0010 1110 Reserved 1111 EXT_INT 11 0000 GPH1CON 4 19 16 0000 Input 0001 Output 0010 0011 Reserved 0100 HDMI_CEC 0100 1110 Reserved 1111 EXT_INT 12 0000 GPH1CON 5 23 20 0000 Input 0001 Output 0010 0011 ...

Page 272: ...ate is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00 2 2 57 3 Port Group GPH1 Control Register GPH1PUD R W Address 0xE020_0C28 GPH1PUD Bit Description Initial State GPH1PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up enabled 11 Reserved 0x5555 2 2 57 4 Port Group GPH1 Control Register GPH1DRV R W A...

Page 273: ...XT_INT 16 0000 GPH2CON 1 7 4 0000 Input 0001 Output 0010 Reserved 0011 KP_COL 1 0011 1110 Reserved 1111 EXT_INT 17 0000 GPH2CON 2 11 8 0000 Input 0001 Output 0010 Reserved 0011 KP_COL 2 0011 1110 Reserved 1111 EXT_INT 18 0000 GPH2CON 3 15 12 0000 Input 0001 Output 0010 Reserved 0011 KP_COL 3 0011 1110 Reserved 1111 EXT_INT 19 0000 GPH2CON 4 19 16 0000 Input 0001 Output 0010 Reserved 0011 KP_COL 4 ...

Page 274: ...ponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00 2 2 58 3 Port Group GPH2 Control Register GPH2PUD R W Address 0xE020_0C48 GPH2PUD Bit Description Initial State GPH2PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up ...

Page 275: ..._INT 24 0000 GPH3CON 1 7 4 0000 Input 0001 Output 0010 Reserved 0011 KP_ROW 1 0011 1110 Reserved 1111 EXT_INT 25 0000 GPH3CON 2 11 8 0000 Input 0001 Output 0010 Reserved 0011 KP_ROW 2 0011 1110 Reserved 1111 EXT_INT 26 0000 GPH3CON 3 15 12 0000 Input 0001 Output 0010 Reserved 0011 KP_ROW 3 0011 1110 Reserved 1111 EXT_INT 27 0000 GPH3CON 4 19 16 0000 Input 0001 Output 0010 Reserved 0011 KP_ROW 4 00...

Page 276: ...ponding bit is the pin state When the port is configured as output port the pin state is the same as the corresponding bit When the port is configured as functional pin the undefined value will be read 0x00 2 2 59 3 Port Group GPH3 Control Register GPH3PUD R W Address 0xE020_0C68 GPH3PUD Bit Description Initial State GPH3PUD n 2n 1 2n n 0 7 00 Pull up down disabled 01 Pull down enabled 10 Pull up ...

Page 277: ... of EXT_INT 7 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 27 Reserved 0 EXT_INT_0_CON 6 26 24 Sets the signaling method of EXT_INT 6 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 23 Reserved 0 EXT_INT_0_CON 5 22 20 Set...

Page 278: ...ling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 7 Reserved 0 EXT_INT_0_CON 1 6 4 Sets the signaling method of EXT_INT 1 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 EXT_INT_0_CON 0 2 0 Sets the signaling method of EXT_INT 0 000 Low level 001 Hi...

Page 279: ...served 23 Reserved 0 EXT_INT_1_CON 5 22 20 Sets the signaling method of EXT_INT 13 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 EXT_INT_1_CON 4 18 16 Sets the signaling method of EXT_INT 12 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered...

Page 280: ...4 Sets the signaling method of EXT_INT 9 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 EXT_INT_1_CON 0 2 0 Sets the signaling method of EXT_INT 8 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 281: ...served 23 Reserved 0 EXT_INT_2_CON 5 22 20 Sets the signaling method of EXT_INT 21 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 EXT_INT_2_CON 4 18 16 Sets the signaling method of EXT_INT 20 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered...

Page 282: ... Sets the signaling method of EXT_INT 17 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 EXT_INT_2_CON 0 2 0 Sets the signaling method of EXT_INT 16 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 283: ...served 23 Reserved 0 EXT_INT_3_CON 5 22 20 Sets the signaling method of EXT_INT 29 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 19 Reserved 0 EXT_INT_3_CON 4 18 16 Sets the signaling method of EXT_INT 28 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered...

Page 284: ... Sets the signaling method of EXT_INT 25 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 Reserved 3 Reserved 0 EXT_INT_3_CON 0 2 0 Sets the signaling method of EXT_INT 24 000 Low level 001 High level 010 Falling edge triggered 011 Rising edge triggered 100 Both edge triggered 101 111 Reserved 000 ...

Page 285: ...les 1 Enables 1 FLTSEL_0 2 22 Filter Selection for EXT_INT 2 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_0 2 21 16 Filtering width of EXT_INT 2 This value is valid when FLTSEL30 is 1 0 FLTEN_0 1 15 Filter Enable for EXT_INT 1 0 Disables 1 Enables 1 FLTSEL_0 1 14 Filter Selection for EXT_INT 1 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_0 1 13 8 Filtering width of EXT_INT 1 Th...

Page 286: ...les 1 Enables 1 FLTSEL_0 6 22 Filter Selection for EXT_INT 6 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_0 6 21 16 Filtering width of EXT_INT 6 This value is valid when FLTSEL30 is 1 0 FLTEN_0 5 15 Filter Enable for EXT_INT 5 0 Disables 1 Enables 1 FLTSEL_0 5 14 Filter Selection for EXT_INT 5 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_0 5 13 8 Filtering width of EXT_INT 5 Th...

Page 287: ...bles 1 Enables 1 FLTSEL_1 2 22 Filter Selection for EXT_INT 10 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_1 2 21 16 Filtering width of EXT_INT 10 This value is valid when FLTSEL31 is 1 0 FLTEN_1 1 15 Filter Enable for EXT_INT 9 0 Disables 1 Enables 1 FLTSEL_1 1 14 Filter Selection for EXT_INT 9 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_1 1 13 8 Filtering width of EXT_INT 9...

Page 288: ...s 1 Enables 1 FLTSEL_1 6 22 Filter Selection for EXT_INT 14 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_1 6 21 16 Filtering width of EXT_INT 14 This value is valid when FLTSEL31 is 1 0 FLTEN_1 5 15 Filter Enable for EXT_INT 13 0 Disables 1 Enables 1 FLTSEL_1 5 14 Filter Selection for EXT_INT 13 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_1 5 13 8 Filtering width of EXT_INT 13...

Page 289: ...s 1 Enables 1 FLTSEL_2 2 22 Filter Selection for EXT_INT 18 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_2 2 21 16 Filtering width of EXT_INT 18 This value is valid when FLTSEL32 is 1 0 FLTEN_2 1 15 Filter Enable for EXT_INT 17 0 Disables 1 Enables 1 FLTSEL_2 1 14 Filter Selection for EXT_INT 17 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_2 1 13 8 Filtering width of EXT_INT 17...

Page 290: ...es 1 Enables 1 FLTSEL_2 6 22 Filter Selection for EXT_INT 22 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_2 6 21 16 Filtering width of EXT_INT 22 This value is valid when FLTSEL32 is 1 0 FLTEN_2 5 15 Filter Enable for EXT_INT 21 0 Disables 1 Enables 1 FLTSEL_2 5 14 Filter Selection for EXT_INT 21 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_2 5 13 8 Filtering width of EXT_INT 2...

Page 291: ...s 1 Enables 1 FLTSEL_3 2 22 Filter Selection for EXT_INT 26 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_3 2 21 16 Filtering width of EXT_INT 26 This value is valid when FLTSEL33 is 1 0 FLTEN_3 1 15 Filter Enable for EXT_INT 25 0 Disables 1 Enables 1 FLTSEL_3 1 14 Filter Selection for EXT_INT 25 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_3 1 13 8 Filtering width of EXT_INT 25...

Page 292: ...s 1 Enables 1 FLTSEL_3 6 22 Filter Selection for EXT_INT 30 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_3 6 21 16 Filtering width of EXT_INT 30 This value is valid when FLTSEL33 is 1 0 FLTEN_3 5 15 Filter Enable for EXT_INT 29 0 Disables 1 Enables 1 FLTSEL_3 5 14 Filter Selection for EXT_INT 29 0 Delay filter 1 Digital filter clock count 0 FLTWIDTH_3 5 13 8 Filtering width of EXT_INT 29...

Page 293: ...les Interrupt 1 Masked 1 EXT_INT_0_MASK 1 1 0 Enables Interrupt 1 Masked 1 EXT_INT_0_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 60 14 External Interrupt Control Registers EXT_INT_1_MASK R W Address 0xE020_0F04 EXT_INT_1_MASK Bit Description Initial State Reserved 31 8 Reserved 0 EXT_INT_1_MASK 7 7 0 Enables Interrupt 1 Masked 1 EXT_INT_1_MASK 6 6 0 Enables Interrupt 1 Masked 1 EXT_INT_1_MASK 5 5 ...

Page 294: ...les Interrupt 1 Masked 1 EXT_INT_2_MASK 1 1 0 Enables Interrupt 1 Masked 1 EXT_INT_2_MASK 0 0 0 Enables Interrupt 1 Masked 1 2 2 60 16 External Interrupt Control Registers EXT_INT_3_MASK R W Address 0xE020_0F0C EXT_INT_3_MASK Bit Description Initial State Reserved 31 8 Reserved 0 EXT_INT_3_MASK 7 7 0 Enables Interrupt 1 Masked 1 EXT_INT_3_MASK 6 6 0 Enables Interrupt 1 Masked 1 EXT_INT_3_MASK 5 5 ...

Page 295: ...ur 1 Occur interrupt 0 EXT_INT_0_PEND 1 1 0 Not occur 1 Occur interrupt 0 EXT_INT_0_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 60 18 External Interrupt Control Registers EXT_INT_1_PEND R W Address 0xE020_0F44 EXT_INT_1_PEND Bit Description Initial State Reserved 31 8 Reserved 0 EXT_INT_1_PEND 7 7 0 Not occur 1 Occur interrupt 0 EXT_INT_1_PEND 6 6 0 Not occur 1 Occur interrupt 0 EXT_INT_1_PEND 5 ...

Page 296: ...ur 1 Occur interrupt 0 EXT_INT_2_PEND 1 1 0 Not occur 1 Occur interrupt 0 EXT_INT_2_PEND 0 0 0 Not occur 1 Occur interrupt 0 2 2 60 20 External Interrupt Control Registers EXT_INT_3_PEND R W Address 0xE020_0F4C EXT_INT_3_PEND Bit Description Initial State Reserved 31 8 Reserved 0 EXT_INT_3_PEND 7 7 0 Not occur 1 Occur interrupt 0 EXT_INT_3_PEND 6 6 0 Not occur 1 Occur interrupt 0 EXT_INT_3_PEND 5 ...

Page 297: ...t Description Initial State Reserved 7 2 Reserved 0 PDNEN_CFG 1 0 Automatically by power down mode 1 by PDNEN bit 0 PDNEN 0 Power down mode pad state enable register 1 PADs Controlled by Power Down mode control registers 0 PADs Controlled by normal mode This bit is set to 1 automaticially when system enters into Power down mode and can be cleared by writing 0 to this bit or cold reset After wake u...

Page 298: ...y controllers DMC0 and DMC1 3D internal SRAM IRAM and IROM INTC and configuration interface SPERI Cortex A8 supports only synchronous mode and therefore it must operate synchronously with 200MHz AXI buses DSYS domain comprises display related modules including FIMC FIMD JPEG and multimedia IPs all other IPs mentioned in X L and T blocks as shown in Figure 3 1 PSYS domain is used for security I O p...

Page 299: ...XRTCXTO pins RTC uses this clock as the source of a real time clock XXTI Specifies a clock from crystal pad with XXTI and XXTO pins When USB PHY is not used in commercial set CMU and PLL use this clock to generate other clocks to modules APLL MPLL VPLL and EPLL The input frequency ranges from 12 50 MHz XUSBXTI Specifies a clock from a crystal pad with XUSBXTI and XUSBXTO pins This clock is supplie...

Page 300: ...ernal clocks with intermediate frequencies using clocks from the clock pads that is XRTCXTI XXTI XUSBXTI and XHDMIXTI four PLLs that is APLL MPLL EPLL and VPLL and USB_OTG PHY clock Some of these clocks can be selected pre scaled and provided to the corresponding modules It is recommended to use 24MHz input clock source for APLL MPLL and EPLL and 27MHz input clock source for VPLL To generate inter...

Page 301: ...ck domain freq PCLK_DSYS freq HCLK_DSYS n where n 1 8 PSYS clock domain freq PCLK_PSYS freq HCLK_PSYS n where n 1 8 freq SCLK_ONENAND freq HCLK_PSYS n where n 1 8 freq SCLK_ONENANPSYS freq SCLK_ONENAND 2 Values for the high performance operation freq ARMCLK 800 MHz freq HCLK_MSYS 200 MHz freq HCLK_IMEM 100 MHz freq PCLK_MSYS 100 MHz freq HCLKSECSS 83 MHz freq HCLK_DSYS 166 MHz freq PCLK_DSYS 83 MH...

Page 302: ...Hz and 40 60 duty ratio EPLL is mainly used to generate audio clock VPLL is mainly used to generate video system operating clock 54 MHz Typically APLL drives MSYS domain and MPLL drives DSYS domain 3 3 1 RECOMMENDED PLL PMS VALUE FOR APLL Table 3 1 APLL PMS Value FIN MHz Target FOUT MHz P M S AFC_ENB AFC FVCO MHz FOUT MHz 24 800 6 200 1 0 0 1600 000 800 000 24 1000 6 250 1 0 0 2000 000 1000 000 ...

Page 303: ...Value FIN MHz Target FOUT MHz VSEL P M S K FVCO MHz FOUT MHz 24 48 0000 0 3 48 3 0 384 000 48 000 24 96 0000 0 3 48 2 0 384 000 96 000 24 144 0000 1 3 72 2 0 576 000 144 000 24 192 0000 0 3 48 1 0 384 000 192 000 24 288 0000 1 3 72 1 0 576 000 288 000 24 84 0000 0 3 42 2 0 336 000 84 000 24 50 0000 0 3 50 3 0 400 000 50 000 24 80 0000 1 3 80 3 0 640 000 80 000 24 32 7680 1 3 65 4 35127 524 28796 3...

Page 304: ... 296 7033 1 6 132 1 594 000 297 000 370 8791 0 11 151 0 370 636 370 636 445 0549 0 6 99 0 445 500 445 500 27 519 2308 1 9 173 0 519 000 519 000 54 000 0 6 108 3 432 000 54 000 108 000 0 6 108 2 432 000 108 000 74 250 1 8 198 3 594 000 74 250 148 500 1 8 198 2 594 000 148 500 222 750 0 16 297 1 445 500 222 750 397 000 0 24 397 0 397 000 397 000 371 250 0 24 371 0 371 000 371 000 445 500 0 16 297 0 ...

Page 305: ...aranteed that both of clock sources are running when clock selection is changed from one to the other If that s not the case clock changing is not finished fully and resulting clock output can have unknown states For non glitch free clock mux it is possible to have a glitch when clock selections are changed To prevent the glitch signals it is recommended to disable output of non glitch free muxes ...

Page 306: ...DMIPHY SCLKMPLL SCLKE PLL SCLKV PLL XXTI XusbXTI SCLK_HDMI 27M SCLK_ USBPHY 0 SCLK_ USBPHY 1 SCLK_ HDMIPHY SCLKMPLL SCLKE PLL SCLKV PLL XXTI PCMCDCLK 0 SCLK_HDMI 27M SCLK_ USBPHY 0 SCLK_ USBPHY 1 SCLK_ HDMIPHY SCLKMPLL SCLKE PLL SCLKV PLL I2 SCDCLK 1 PCMCDCLK 1 SCLK_HDMI 27M SCLK_ USBPHY 0 SCLK_ USBPHY 1 SCLK_ HDMIPHY SCLKMPLL SCLKE PLL SCLKV PLL I2 SCDCLK 2 PCMCDCLK 2 SCLK_HDMI 27M SCLK_ USBPHY 0...

Page 307: ...AXI_MEM MSYS 100 MHz IRAM IROM TZPC0 166 MHz FIMC0 FIMC1 FIMC2 FIMD DSIM CSIS JPEG Rotator VP MIXER TVENC HDMI MDMA G2D DSYS 83 MHz DSIM CSIS I2C_HDMI_PHY I2C_HDMI_DDC 133 MHz CSSYS SECJTAG HOST I F MODEM I F CFCON NFCON SROMC ONE NANDxl PDMA0 PDMA1 SECSS HSMMC0 HSMM1 HSMMC2 USB OTG USB HOST PSYS 66MHz SYSCON GPIO CHIPID APC IEC TZPC1 SPI0 SPI1 I2S1 I2S2 PCM0 PCM1 AC97 SPDIF I2C0 I2C2 KEYIF TSADC ...

Page 308: ...LL output clock instead of input reference clock after PLL output clock is stabilized Refer to 0 4 8 12th bit of CLK_SRC0 SFR Turn OFF a PLL A M E V PLL_SEL 0 De select the output of a PLL A M E V PLL_CON 31 0 Power OFF the PLL Change PLL s PMS values Set PMS values Set PDIV MDIV and SDIV values Refer to A M E V PLL_CON SFR Change the system clock divider values CLK_DIV0 31 0 target value0 Change ...

Page 309: ...lock All possible clock sources SCLK_PIXEL HDMI PIXEL clock All possible clock sources SCLK_SPDIF SPDIF operating clock SCLK_AUDIO0 2 SCLK_MMC0 1 2 HSMMC operating clock All possible clock sources SCLK_USB_OHCI USB OTG clock 48MHz USB PHY SCLK_USB_PHY USB OTG clock 30MHz USB PHY SCLK_AUDIO0 1 2 AUDIO operating clock PCM I2S All possible clock sources SCLK_PWI IEM APC operating clock All possible c...

Page 310: ...lock SCLKMPLL SCLKEPLL and SCLKVPLL mean output clock of MPLL EPLL and EPLL respectively Table 3 7 I O Clocks in S5PC110 Name I O PAD Type Description IOCLK_CFCON CFCON I O clock to receive data IOCLK_AC97 IN Muxed AC97 bit clock IOCLK_I2S0 1 2 IN Muxed I2S CODEC clock IOCLK_PCM0 1 2 IN Muxed PCM CODEC clock IOCLK_SPDIF0 1 2 IN Muxed SPDIF input clock IOCLK_PWM IN Muxed PWM input clock ...

Page 311: ... output frequency for APLL 0x00C8_0301 APLL_CON1 0xE010_0104 R W Control PLL AFC Adaptive Frequency Calibrator 0x0000_0000 MPLL_CON 0xE010_0108 R W Control PLL output frequency for MPLL 0x014D_0301 Reserved 0xE010_010C Reserved EPLL_CON0 0xE010_0110 R W Control PLL output frequency for EPLL 0x0885_0302 EPLL_CON1 0xE010_0114 R W Control PLL output frequency for EPLL 0x0000_0000 Reserved 0xE010_0118...

Page 312: ...rol IP clock gating 0xFFFF_FFFF CLK_GATE_IP1 0xE010_0464 R W Control IP clock gating 0xFFFF_FFFF CLK_GATE_IP2 0xE010_0468 R W Control IP clock gating 0xFFFF_FFFF CLK_GATE_IP3 0xE010_046C R W Control IP clock gating 0xFFFF_FFFF CLK_GATE_IP4 0xE010_0470 R W Control IP clock gating 0xFFFF_FFFF Reserved 0xE010_0474 0xE010_047C Reserved CLK_GATE_BLOCK 0xE010_0480 R W Control block clock gating 0xFFFF_F...

Page 313: ...0xE010_30FC Reserved APLL_CON0_L8 0xE010_3100 R W APLL control performance level 8 0x00C8_0301 APLL_CON0_L7 0xE010_3104 R W APLL control performance level 7 0x00C8_0301 APLL_CON0_L6 0xE010_3108 R W APLL control performance level 6 0x00C8_0301 APLL_CON0_L5 0xE010_310C R W APLL control performance level 5 0x00C8_0301 APLL_CON0_L4 0xE010_3110 R W APLL control performance level 4 0x00C8_0301 APLL_CON0...

Page 314: ...vel 4 0x0000_0000 APLL_CON1_L3 0xE010_3314 R W Control PLL AFC performance level 3 0x0000_0000 APLL_CON1_L2 0xE010_3318 R W Control PLL AFC performance level 2 0x0000_0000 APLL_CON1_L1 0xE010_331C R W Control PLL AFC performance level 1 0x0000_0000 Reserved 0xE010_3320 0xE010_7004 Reserved DISPLAY_CONTROL 0xE010_7008 R W Display output path selection 0x0000_0000 AUDIO_ENDIAN 0xE010_700C R W Endian...

Page 315: ...CK R W Address 0xE010_0008 EPLL_LOCK R W Address 0xE010_0010 VPLL_LOCK R W Address 0xE010_0020 A PLL requires locking period when input frequency is changed or frequency division multiplication values are changed PLL_LOCK register specifies this locking period which is based on PLL s source clock During this period output will be masked 0 APLL_LOCK MPLL_LOCK EPLL_LOCK VPLL_LOCK Bit Description Ini...

Page 316: ...1 Locked Read Only 0 Reserved 28 26 Reserved 0x0 MDIV 25 16 PLL M divide value 0xC8 Reserved 15 14 Reserved 0 PDIV 13 8 PLL P divide value 0x3 Reserved 7 3 Reserved 0 SDIV 2 0 PLL S divide value 0x1 The reset value of APLL_CON0 generates 800 MHz output clock if the input clock frequency is 24 MHz Equation to calculate the output frequency FOUT MDIV X FIN PDIV 2SDIV 1 where MDIV PDIV SDIV for APLL ...

Page 317: ...ects adaptive frequency curve of VCO for wide range high phase noise or jitter and fast lock time LOW AFC is enabled HIGH AFC is disabled Users should refer to 3 3 1 on whether to use AFC for a given P M S values 0x0 Reserved 30 5 Reserved 0x0 AFC 4 0 AFC value Users should refer to 3 3 1 on the recommended AFC value for a given scenario 0x0 ...

Page 318: ...alue of APLL_CON0 and MPLL_CON generates 800 MHz and 667 MHz output clock respectively if the input clock frequency is 24 MHz Equation to calculate the output frequency FOUT MDIV X FIN PDIV X 2SDIV where MDIV PDIV SDIV for APLL and MPLL must meet the following conditions PDIV 1 PDIV 63 MDIV 16 MDIV 511 SDIV 0 SDIV 5 Fref FIN PDIV 1MHz Fref 10MHz FVCO MDIV X FIN PDIV 1000MHz FVCO 1400MHz when VSEL ...

Page 319: ...SDIV 2 0 PLL S divide value 0x2 EPLL_CON1 Bit Description Initial State Reserved 31 16 Reserved 0x0 K 15 0 PLL K value K value is used to fine tune M divider value to meet FOUT requirement exactly For this purpose MDIV K 65536 is used for M divider value Also called as DSM Delta Sigma Modulator 0x0 The reset value of EPLL_CON and VPLL_CON generates 133 MHz and 54 MHz output clock respectively if t...

Page 320: ...MHz FOUT 660MHz Refer to 3 3 3 Recommended PLL PMS Value for EPLL for recommended PMS values Caution EPLL should be turned on before entering following low power modes Deep idle stop deep stop sleep mode EPLL will be automatically turned off while entering those low power modes ...

Page 321: ... The reset value of EPLL_CON and VPLL_CON generates 133 MHz and 54 MHz output clock respectively if the input clock frequency is 24 MHz Equation to calculate the output frequency FOUT MDIV X FIN PDIV X 2SDIV where MDIV PDIV SDIV for PLLs must meet the following conditions PDIV 1 PDIV 63 MDIV 16 MDIV 511 SDIV 0 SDIV 5 Fref FIN PDIV 2MHz Fref 6MHz FVCO MDIV X FIN PDIV 330MHz FVCO 460MHz when VSEL LO...

Page 322: ... ONENAND_SEL 28 Control MUXFLASH 0 HCLK_PSYS 1 HCLK_DSYS 0 Reserved 27 25 Reserved 0x0 MUX_PSYS_SEL 24 Control MUX_PSYS 0 SCLKMPLL 1 SCLKA2M 0 Reserved 23 21 Reserved 0x0 MUX_DSYS_SEL 20 Control MUX_DSYS 0 SCLKMPLL 1 SCLKA2M 0 Reserved 19 17 Reserved 0x0 MUX_MSYS_SEL 16 Control MUX_MSYS 0 SCLKAPLL 1 SCLKMPLL 0 Reserved 15 13 Reserved 0x0 VPLL_SEL 12 Control MUXVPLL 0 FINVPLL 1 FOUTVPLL 0 Reserved ...

Page 323: ...0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL OTHERS reserved 0x0 CAM1_SEL 19 16 Control MUXCAM1 which is the source clock of CAM0 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI27M 0011 SCLK_USBPHY0 0100 SCLK_USBPH1 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL OTHERS reserved 0x0 CAM0_SEL 15 12 Control MUXCAM0 which is the source clock of CAM0 0000 XXTI 0001 XusbXTI 0010 SCLK_HDMI27M 0011 SCLK_U...

Page 324: ...Control MUXG2D which is the source clock of G2D core 00 SCLKA2M 01 SCLKMPLL 10 SCLKEPLL 11 SCLKVPLL 0x0 Reserved 7 6 Reserved 0x0 MFC_SEL 5 4 Control MUXMFC which is the source clock of MFC core 00 SCLKA2M 01 SCLKMPLL 10 SCLKEPLL 11 SCLKVPLL 0x0 Reserved 3 2 Reserved 0x0 G3D_SEL 1 0 Control MUXG3D which is the source clock of G3D core 00 SCLKA2M 01 SCLKMPLL 10 SCLKEPLL 11 SCLKVPLL 0x0 ...

Page 325: ...FIMC_LCLK_SEL 23 20 Control MUXFIMC_LCLK which is the source clock of FIMC2 local clock 0000 XXTI 0001 XUSBXTI 0010 SCLK_HDMI27M 0011 SCLK_USBPHY0 0100 SCLK_USBPH1 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL OTHERS reserved 0x0 F1 19 16 Should have same value as FIMC_LCLK_SEL 0x0 F0 15 12 Should have same value as FIMC_LCLK_SEL 0x0 Reserved 11 0 Reserved 0x0 ...

Page 326: ... the source clock of UART0 0000 XXTI 0001 XUSBXTI 0010 SCLK_HDMI27M 0011 SCLK_USBPHY0 0100 SCLK_USBPH1 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL OTHERS reserved 0x0 MMC3_SEL 15 12 Control MUXMMC3 which is the source clock of MMC3 0000 XXTI 0001 XUSBXTI 0010 SCLK_HDMI27M 0011 SCLK_USBPHY0 0100 SCLK_USBPH1 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL OTHERS reserved ...

Page 327: ...HY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL OTHERS reserved 0x0 Reserved 11 8 Reserved 0x0 SPI1_SEL 7 4 Control MUXSPI1 which is the source clock of SPI1 0000 XXTI 0001 XUSBXTI 0010 SCLK_HDMI27M 0011 SCLK_USBPHY0 0100 SCLK_USBPH1 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL OTHERS reserved 0x0 SPI0_SEL 3 0 Control MUXSPI0 which is the source clock of SPI0 0000 XXTI 0001 XUSBXTI 001...

Page 328: ...d 15 14 Reserved 0x0 SPDIF_SEL 13 12 Control MUXSPDIF which is the source clock of SPDIF 00 SCLK_AUDIO0 01 SCLK_AUDIO1 1x SCLK_AUDIO2 0x0 AUDIO2_SEL 11 8 Control MUXAUDIO2 which is the source clock of AUDIO2 0000 I2SCDCLK2 0001 PCMCDCLK2 0010 SCLK_HDMI27M 0011 SCLK_USBPHY0 0100 SCLK_USBPHY1 0101 SCLK_HDMIPHY 0110 SCLKMPLL 0111 SCLKEPLL 1000 SCLKVPLL OTHERS rerved 0x0 AUDIO1_SEL 7 4 Control MUXAUDI...

Page 329: ...output clock of MUXUART3 0 disable 1 enable 1 UART2_MASK 14 Mask output clock of MUXUART2 0 disable 1 enable 1 UART1_MASK 13 Mask output clock of MUXUART1 0 disable 1 enable 1 UART0_MASK 12 Mask output clock of MUXUART0 0 disable 1 enable 1 MMC3_MASK 11 Mask output clock of MUXMMC3 0 disable 1 enable 1 MMC2_MASK 10 Mask output clock of MUXMMC2 0 disable 1 enable 1 MMC1_MASK 9 Mask output clock of ...

Page 330: ...ress R W 0xE010_0284 CLK_SRC_MASK1 Bit Description Initial State Reserved 31 7 Reserved 0x7FF_FFFF FIMC_LCLK_MASK 4 Mask output clock of MUXFIMC_LCLK 0 disable 1 enable 1 F1 3 Should have same value as FIMC_LCLK_MASK 1 F0 2 Should have same value as FIMC_LCLK_MASK 1 Reserved 1 0 Reserved 0x3 ...

Page 331: ...er finishes changing to a new dividing value before it s output is used by other modules 3 7 4 1 Clock Divider Control Register CLK_DIV0 R W Address 0xE010_0300 CLK_DIV0 Bit Description Initial State Reserved 31 Reserved 0 PCLK_PSYS_RATIO 30 28 DIVPCLKP clock divider ratio PCLK_PSYS HCLK_PSYS PCLK_PSYS_RATIO 1 0x0 HCLK_PSYS_RATIO 27 24 DIVHCLKP clock divider ratio HCLK_PSYS MOUT_PSYS HCLK_PSYS_RAT...

Page 332: ...K_CAM1 MOUTCAM1 CAM1_RATIO 1 0x0 CAM0_RATIO 15 12 DIVCAM0 clock divider ratio SCLK_CAM0 MOUTCAM0 CAM0_RATIO 1 0x0 Reserved 11 4 Reserved 0x0 TBLK_RATIO 3 0 DIVTBLK clock divider ratio SCLK_PIXEL SCLKVPLL TBLK_RATIO 1 0x0 3 7 4 3 Clock Divider Control Register CLK_DIV2 R W Address 0xE010_0308 CLK_DIV2 Bit Description Initial State Reserved 31 12 Reserved 0x00_0000 G2D_RATIO 11 8 DIVG2D clock divide...

Page 333: ...V4 Bit Description Initial State UART3_RATIO 31 28 DIVUART3 clock divider ratio SCLK_UART3 MOUTUART3 UART3_RATIO 1 0x0 UART2_RATIO 27 24 DIVUART2 clock divider ratio SCLK_UART2 MOUTUART2 UART2_RATIO 1 0x0 UART1_RATIO 23 20 DIVUART1 clock divider ratio SCLK_UART1 MOUTUART1 UART1_RATIO 1 0x0 UART0_RATIO 19 16 DIVUART0 clock divider ratio SCLK_UART0 MOUTUART0 UART0_RATIO 1 0x0 MMC3_RATIO 15 12 DIVMMC...

Page 334: ...e DMC0_RATIO 31 28 DIVDMC0 clock divider ratio SCLK_DMC0 MOUTDMC0 DMC0_RATIO 1 0x0 PWI_RATIO 27 24 DIVPWI clock divider ratio SCLK_PWI MOUTPWI PWI_RATIO 1 0x0 Reserved 23 Reserved 0 HPM_RATIO 22 20 DIVHPM clock divider ratio SCLK_HPM DOUTCOPY IEM_RATIO 1 0x0 Reserved 19 Reserved 0 COPY_RATIO 18 16 DIVCOPY clock divider ratio DOUTCOPY MOUTHPM COPY_RATIO 1 0x0 Reserved 15 Reserved 0x0 ONENAND_RATIO ...

Page 335: ...f DIVDPM clock divider is PCLK for IEM_IEC DPM_RATIO decides how often DPM channel increments for IEM_IEC Refer to Figure 3 3 0x0 Reserved 7 Reserved 0 DVSEM_RATIO 6 0 CLK_DVSEM clock divider ratio Source of DIVDVSEM clock divider is PCLK for IEM_IEC DVSEM_RATIO decides how often PWM frame time slot is advanced when IEM_IEC is in DVS emulation mode It should be guaranteed DIVDVSEM clock runs at 1M...

Page 336: ... Should be one for all bit Reserved 0x1F 3 7 5 2 Clock Gating Control Register CLK_GATE_IP0 R W Address 0xE010_0460 CLK_GATE_IP0 Bit Description Gated Clock Name Initial State CLK_CSIS 31 Gating all clocks for CSIS PCLK_CSIS SCLK_CSIS 1 Reserved 30 Reserved Reserved 1 CLK_ROTATOR 29 Gating all clocks for ROTATOR 0 mask 1 pass ACLK_ROTATOR 1 CLK_JPEG 28 Gating all clocks for JPEG 0 mask 1 pass ACLK...

Page 337: ...K_IMEM 5 Gating all clocks for IMEM 0 mask 1 pass ACLK_IMEM 1 CLK_PDMA1 4 Gating all clocks for PDMA1 0 mask 1 pass ACLK_PDMA1 PCLK_PDMA1 1 CLK_PDMA0 3 Gating all clocks for PDMA0 0 mask 1 pass ACLK_PDMA0 PCLK_PDMA0 1 CLK_MDMA 2 Gating all clocks for MDMA 0 mask 1 pass ACLK_MDMA PCLK_MDMA 1 CLK_DMC1 1 Gating all clocks for DMC1 0 mask 1 pass ACLK_DMC1 PCLK_DMC1 1 CLK_DMC0 0 Gating all clocks for D...

Page 338: ..._NANDXL 1 Reserved 23 18 Reserved 0x3F CLK_USBHOST 17 Gating all clocks for USB HOST 0 mask 1 pass ACLK_USBHOST 1 CLK_USBOTG 16 Gating all clocks for USB OTG 0 mask 1 pass ACLK_USBOTG 1 Reserved 15 12 Reserved 0xF CLK_HDMI 11 Gating all clocks for HDMI link 0 mask 1 pass PCLK_HDMI SCLK_HDMI 1 CLK_TVENC 10 Gating all clocks for TVENC 0 mask 1 pass ACLK_TVENC SCLK_TVENC SCLK_DAC 1 CLK_MIXER 9 Gating...

Page 339: ...s ACLK_VIC1 1 CLK_VIC0 24 Gating all clocks for VIC0 0 mask 1 pass ACLK_VIC0 1 Reserved 23 21 Reserved 0x7 CLK_TSI 20 Gating all clocks for TSI 0 mask 1 pass ACLK_TSI 1 CLK_HSMMC3 19 Gating all clocks for HSMMC3 0 mask 1 pass ACLK_HSMMC3 SCLK_MMC3 1 CLK_HSMMC2 18 Gating all clocks for HSMMC2 0 mask 1 pass ACLK_HSMMC2 SCLK_MMC2 1 CLK_HSMMC1 17 Gating all clocks for HSMMC1 0 mask 1 pass ACLK_HSMMC1 ...

Page 340: ...tial State Reserved 7 2 Reserved 0x3F CLK_SDM 1 Gating all clocks for SDM 0 mask 1 pass ACLK_SDM PCLK_SDM 1 CLK_SECSS 0 Gating all clocks for SECSS 0 mask 1 pass ACLK_SECSS 1 Caution Is should be guaranteed that S W does not access IPs whose clock is gated This can cause system failure ...

Page 341: ...eserved 25 Reserved 1 CLK_TSADC 24 Gating all clocks for TSADC 0 mask 1 pass PCLK_TSADC 1 CLK_PWM 23 Gating all clocks for PWM 0 mask 1 pass PCLK_PWM SCLK_PWM 1 CLK_WDT 22 Gating all clocks for WDT 0 mask 1 pass PCLK_WDT 1 CLK_KEYIF 21 Gating all clocks for KEYIF 0 mask 1 pass PCLK_KEYIF 1 CLK_UART3 20 Gating all clocks for UART3 0 mask 1 pass PCLK_UART3 SCLK_UART3 1 CLK_UART2 19 Gating all clocks...

Page 342: ...eserved 8 Reserved 1 CLK_I2C0 7 Gating all clocks for I2C0 0 mask 1 pass PCLK_I2C0 1 CLK_I2S2 6 Gating all clocks for I2S2 0 mask 1 pass DO NOT mask when SPDIF is used PCLK_I2S2 SCLK_AUDIO2 1 CLK_I2S1 5 Gating all clocks for I2S1 0 mask 1 pass DO NOT mask when PCM1 or SPDIF is used PCLK_I2S1 SCLK_AUDIO1 1 CLK_I2S0 4 Gating all clocks for I2S0 0 mask 1 pass DO NOT mask when PCM0 or SPDIF is used SC...

Page 343: ... TZPC2 0 mask 1 pass PCLK_TZPC2 1 CLK_TZPC1 6 Gating all clocks for TZPC1 0 mask 1 pass PCLK_TZPC1 1 CLK_TZPC0 5 Gating all clocks for TZPC0 0 mask 1 pass PCLK_TZPC0 1 Reserved 4 Reserved 1 CLK_SECKEY 3 Gating all clocks for SECKEY 0 mask 1 pass PCLK_SECKEY 1 CLK_IEM_APC 2 Gating all clocks for IEM APC 0 mask 1 pass PCLK_IEM_APC SCLK_PWI 1 CLK_IEM_IEC 1 Gating all clocks for IEM IEC 0 mask 1 pass ...

Page 344: ...K_HSMMC0 1 2 3 1 CLK_DEBUG 8 Gating all clocks for block DEBUG MODEM I F HOST I F CSSYS SECJTAG 0 mask 1 pass ACLK_CSSYS ACLK_MODEM ACLK_HOSTIF ACLK_AHB_GSFR ACLK_AHB_GSYS PCLK_CSSYS PCLK_SECJTAG 1 CLK_SECURITY 7 Gating all clocks for block SECURITY Security Subsystem 0 mask 1 pass ACLK_SECSS ACLK_AHB_ESYS0 1 ACLK_AHB_ESFR 1 CLK_MEMORY 6 Gating all clocks for block MEMORY OneNAND XL CFCON SROMC On...

Page 345: ...LK_AHB_LSFR ACLK_AXI_LSYS PCLK_DSIM PCLK_AXI_LSYS SCLK_FIMD SCLK_FIMC_LCLK1 ACLK_G2D SCLK_G2D 1 CLK_IMG 2 Gating all clocks for block IMG FIMC0 1 2 JPEG ROTATOR 0 mask 1 pass ACLK_FIMC0 1 2 ACLK_JPEG ACLK_ROTATOR ACLK_AHB_XSFR ACLK_AXI_XSYS PCLK_CSIS PCLK_AXI_XSYS SCLK_CAM0 1 SCLK_CSIS SCLK_FIMC_LCLK 1 CLK_MFC 1 Gating all clocks for block MFC MFC 0 mask 1 pass PCLK_MFC SCLK_MFC 1 CLK_G3D 0 Gating...

Page 346: ...Register CLK_GATE_IP5 R W Address 0xE010_0484 CLK_GATE_IP5 Bit Description Gated Clock Name Initial State Reserved 31 30 Should be one for all bit 0x3 CLK_JPEG 29 Gating all clocks for JPEG 0 mask 1 pass ACLK_JPEG 1 Reserved 28 0 Should be one for all bit 0x1FFFFFFF ...

Page 347: ..._GATE_IP3 0 for SPDIF CLK_GATE_IP3 4 for I2S0 CLK_GATE_IP3 28 for PCM0 SCLK_AUDIO1 is gated when all of the following register fields are cleared to LOW This guarantees SCLK_AUDIO1 is running when any of the load is running CLK_GATE_IP3 0 for SPDIF CLK_GATE_IP3 5 for I2S1 CLK_GATE_IP3 29 for PCM1 SCLK_AUDIO2 is gated when all of the following register fields are cleared to LOW This guarantees SCLK...

Page 348: ...23 20 Divide ratio Divide ratio DIVVAL 1 0x0 Reserved 19 17 Reserved 0x000 00000 FOUTAPLL 4 00001 FOUTMPLL 2 00010 FOUTEPLL 00011 FOUTVPLL 00100 SCLK_USBPHY0 00101 SCLK_USBPHY1 00110 SCLK_HDMIPHY 00111 RTC 01000 RTC_TICK_SRC 01001 HCLK_MSYS 01010 PCLK_MSYS 01011 HCLK_DSYS 01100 PCLK_DSYS 01101 HCLK_PSYS 01110 PCLK_PSYS 01111 ARMCLK 4 10000 SCLK_HPM 10001 XXTI 10010 XUSBXTI CLKSEL 16 12 10011 DCLK ...

Page 349: ...lect DCLK source clock 000 XXTI 001 XUSBXTI 010 SCLK_HDMI27M 011 SCLK_USBPHY0 100 SCLK_USBPH1 101 SCLK_HDMIPHY 110 FOUTMPLL 2 111 SCLKEPLL 0 DCLKEN 0 Enable DCLK 0 disable 1 enable 0 CLKOUT frequency CLKIN selected by CLKSEL frequency DIVVAL 1 Figure 3 4 CLKOUT Waveform with DCLK Divider ...

Page 350: ...status 0 stable 1 divider is changing 0 DIV_G3D 16 DIVG3D status 0 stable 1 divider is changing 0 DIV_CSIS 15 DIVCSIS status 0 stable 1 divider is changing 0 Reserved 14 Reserved 0 DIV_FIMD 13 DIVFIMD status 0 stable 1 divider is changing 0 DIV_CAM1 12 DIVCAM1 status 0 stable 1 divider is changing 0 DIV_CAM0 11 DIVCAM0 status 0 stable 1 divider is changing 0 DIV_FIMC 10 DIVFIMC status 0 stable 1 d...

Page 351: ..._PWI 14 DIVPWI status 0 stable 1 divider is changing 0 DIV_HPM 13 DIVHPM status 0 stable 1 divider is changing 0 DIV_COPY 12 DIVCOPY status 0 stable 1 divider is changing 0 DIV_ONENAND 11 DIVFLASH status 0 stable 1 divider is changing 0 DIV_AUDIO2 10 DIVAUDIO2 status 0 stable 1 divider is changing 0 DIV_AUDIO1 9 DIVAUDIO1 status 0 stable 1 divider is changing 0 DIV_AUDIO0 8 DIVAUDIO0 status 0 stab...

Page 352: ...al status of MUX_PSYS 001 SCLKMPLL 010 SCLKA2M 1xx On changing 0x1 Reserved 23 Reserved 0 MUX_DSYS_SEL 22 20 Selection signal status of MUX_DSYS 001 SCLKMPLL 010 SCLKA2M 1xx On changing 0x1 Reserved 19 Reserved 0 MUX_MSYS_SEL 18 16 Selection signal status of MUX_MSYS 001 SCLKAPLL 010 SCLKMPLL 1xx On changing 0x1 Reserved 15 Reserved 0 VPLL_SEL 14 12 Selection signal status of MUXVPLL 001 FINVPLL 0...

Page 353: ...n signal status of MUXG2D 00x0 SCLKA2M 00x1 SCLKMPLL 010x SCLKEPLL 011x SCLKVPLL 1xxx On changing 0x0 Reserved 23 19 Reserved 0x0 HPM_SEL 18 16 Selection signal status of MUXHPM 001 SCLKAPLL 010 SCLKMPLL 1xx On changing 0x1 Reserved 15 8 Reserved 0x0 MFC_SEL 7 4 Selection signal status of MUXMFC 00x0 SCLKA2M 00x1 SCLKMPLL 010x SCLKEPLL 011x SCLKVPLL 1xxx On changing 0x0 G3D_SEL 3 0 Selection signa...

Page 354: ... Description Initial State DCGIDX_MAP0 31 0 IEC configuration for DCG index map 31 0 0xFFFF_FFFF 3 7 10 2 IEM Control SFRs DCGIDX_MAP1 R W Address 0xE010_3004 DCGIDX_MAP1 Bit Description Initial State DCGIDX_MAP1 31 0 IEC configuration for DCG index map 63 32 0xFFFF_FFFF 3 7 10 3 IEM Control SFRs DCGIDX_MAP2 R W Address 0xE010_3008 DCGIDX_MAP2 Bit Description Initial State DCGIDX_MAP2 31 0 IEC con...

Page 355: ...010_3024 DCGPERF_MAP1 Bit Description Initial State DCGPERF_MAP1 31 0 DCG performance map 63 32 0xFFFF_FFFF DCGPERF_MAP0 1 are mapped to IECCFGDCGPERFMAP 63 0 of IEM_IEC input port 3 7 10 6 IEM Control SFRs DVCIDX_MAP_MAP0 R W Address 0xE010_3040 DVCIDX_MAP Bit Description Initial State Reserved 31 24 Reserved 0x00 DCGPERF_MAP0 23 0 IEC configuration for DVC index map 23 0 0xFF_FFFF DVCIDX_MAP is ...

Page 356: ...cy 0x00_4E20 24 MSYS20_000 200 000KHz 20MHz 0x03_A980 24 PSYS40_000 240 000KHz 240MHz 0x00_03E8 24 MSYS01_000 1 000KHz 1MHz 3 7 10 8 IEM Control SFRs FREQ_DPM R W Address 0xE010_3064 FREQ_DPM Bit Description Initial State Reserved 31 24 Reserved 0x00 FREQ_DPM 23 0 Maximum frequency of DPM accumulators 0x00_0000 The register is related to IECCFGFREQDPM 23 0 of IEM_IEC input port FREQ_DPM 23 0 is th...

Page 357: ...k enable 0 The register is related to IECDVSEMCLKEN of IEM_IEC input port DVSEMCLK_EN means the enable for advancing the PWM frame time slots when in DVS emulation mode The signal must be pulsed at a frequency of 1 MHz 3 7 10 10 IEM Control SFRs MAXPERF R W Address 0xE010_3084 MAXPERF Bit Description Initial State Reserved 31 1 Reserved 0x0000_0000 MAXPERF_EN 0 MAX performance enable 0 disable 1 e...

Page 358: ...L_CON1_L3 R W Address 0xE010_3314 APLL_CON1_L2 R W Address 0xE010_3318 APLL_CON1_L1 R W Address 0xE010_331C APLL_CON0_L1 8 Bit Description Initial State Reserved 31 26 Reserved 0x00 MDIV 25 16 APLL M divide value 0x0C8 Reserved 15 14 Reserved 0 PDIV 13 8 APLL P divide value 0x3 Reserved 7 3 Reserved 0 SDIV 2 0 APLL S divide value 0x1 Each register of APLL_CON0_L1 7 configures P M S VCO_FREQ values...

Page 359: ...ed 0x000 HPM_RATIO 22 20 DIVIEM clock divider ratio DIVIEM DIVCOPY RATIO RATIO IEM_RATIO 1 0x0 Reserved 19 Reserved 0 COPY_RATIO 18 16 DIVCOPY clock divider ratio DIVCOPY MUXIEM RATIO RATIO COPY_RATIO 1 0x0 Reserved 15 11 Reserved 0x00 HCLK_MSYS_RATIO 10 8 DIVHCLKM clock divider ratio HCLK_MSYS ARMCLK RATIO RATIO HCLK_MSYS_RATIO 1 0x0 Reserved 7 3 Reserved 0x0 APLL_RATIO 2 0 DIVAPLL clock divider ...

Page 360: ... 11 RGB FIMD I80 FIMD ITU FIMD 3 7 11 2 Miscellaneous SFRs AUDIO_ENDIAN R W Address 0xE010_700C AUDIO_ENDIAN Bit Description Initial State Reserved 31 4 Reserved 0x0000_0000 RP_R_ENDIAN 3 Endian selection for RP read channel 0 little endian 1 big endian 0 RP_W_ENDIAN 2 Endian selection for RP write channel channel 0 little endian 1 big endian 0 ARM_R_ENDIAN 1 Endian selection for ARM read channel ...

Page 361: ...top In this mode the S5PC110 is clock gated except RTC module Therefore application programming stops and waits for wakeup event to resume its operation Also the CPU core clock is disabled Note The power gated block in Normal mode is still power gated in Stop mode Deep stop In this mode the CPU core and remaining parts of the chip are power gated except TOP RTC and ALIVE modules The TOP module can...

Page 362: ... power can be reduced by frequency scaling Clock gating means that the clock to a specific Intellectual Property IP module is disabled using clock gating cells in SYSCON To control these clock gating cells set registers CLK_GATE_IP0 4 and CLK_GATE_BLOCK in SYSCON Clock gating technique is also applied in synthesis phase of chip development flow where gate level netlist is generated from RTL code b...

Page 363: ...need to operate and can be power gated for minimum static power consumption S5PC110 internal modules are grouped into 11 power domains based on their functions as shown in Table 4 2 S5PC110 Power Domains of Internal Logic and eight power domains except System Timer ALIVE and RTC can be power gated by turning OFF the Current Cut off Switch CCS which connects the current path between real VDD and vi...

Page 364: ...core is minimized There are three options in DEEP IDLE mode The first option is that the remaining parts of the chip keep their operations in NORMAL mode The second option is that the remaining parts of the chip keep their states in NORMAL mode The third option is that for low power MP3 playback that is TOP and SUB blocks are also power gated but only Audio block is still power on These three opti...

Page 365: ...Clock gating KEEP power state in NORMAL mode KEEP power state in NORMAL mode Power gating5 Clock gating Power on Power gating Power off ALIVE Power on PLL Selectively Disabled Selectively Disabled Disabled Power off OSC Selectively Disabled Selectively Disabled Selectively Disabled Selectively Disabled I O Power on Power on Power on internal power16 off alive power17 on OSC enabled 1us7 1us 1us8 o...

Page 366: ... TOP block OFF maximum 300us for PLL 100 us for ARM reset de assertion 6ms for regulator ON 100us for ARM reset de assertion 1ms for OSC max 300us for PLL 50 us for ARM clock supply For TOP block OFF 1ms for OSC max 300us for PLL 100 us for ARM reset de assertion 6ms for regulator ON 1ms for OSC 100us for ARM reset de assertion Internal power is connected to all internal logic except CPU ALIVE and...

Page 367: ...the corresponding bits in NORMAL_CFG register to perform power gating in one or more blocks The IP blocks that can be power gated in NORMAL mode are MFC G3D IMG sub system LCD sub system and TV sub system Refer to Table 4 2 Power gating of a block will disconnect the current path to the logic gates The power domain can also be powered ON by setting the corresponding bit in NORMAL_CFG register Chan...

Page 368: ...up time is composed of the logic power up time and the memory power up time These are determined by the oscillator frequency number of memories and count values given in the OSC_FREQ registers The count value depends on the size of the logic gates and number of memories System Timer domain has no memory and therefore memory power up time is not necessary The second technique is as follows The logi...

Page 369: ...operate and to reduce CPU power the power to Cortex A8 core can be gated internally This saves the static leakage consumption To save the static leakage consumption set the register IDLE_CFG in SYSCON and execute a Wait For Interrupt instruction There are three options in DEEP IDLE mode namely 1 The remaining parts of the chip keep their operations in NORMAL mode 2 The remaining parts of the chip ...

Page 370: ...gnored by the processor and user should call wfi instruction again The SYSCON performs the following sequence to enter DEEP IDLE mode TOP_LOGIC 2 b01 1 Complete all active bus transactions 2 Complete all active memory controller transactions 3 Allow external DRAM to enter self refresh mode to preserve DRAM contents 4 Mask clock input using internal signal in SYSCON 5 Disable all PLLs except for EP...

Page 371: ...d of OTHERS to 1 b1 7 Execute Wait For Interrupt instruction WFI If SYSCON_INT_DISABLE field of OTHERS is still 1 b1 after calling wfi instruction this indicates wfi instruction is ignored by the processor and user should call wfi instruction again The SYSCON performs the following sequence to enter STOP mode 1 Complete all active bus transactions 2 Complete all active memory controller transactio...

Page 372: ...P mode 1 Enable the OSC pads if disabled and wait for the OSC stabilization around 1ms 2 Enable the PLLs and wait for locking about 300us 3 Unmask clock input to clock on blocks 4 Let DRAMs exit from self refresh mode OSC stabilization time is determined by the external clock frequency and counter value specified in the OSC_STABLE register PLL locking time is set in PLL_LOCK registers ...

Page 373: ...on the users requirements 5 Set CFG_STANDBYWFI field of PWR_CFG to 2 b10 6 Set SYSCON_INT_DISABLE field of OTHERS to 1 b1 7 Execute Wait For Interrupt instruction WFI If SYSCON_INT_DISABLE field of OTHERS is still 1 b1 after calling wfi instruction this indicates wfi instruction is ignored by the processor and user should call wfi instruction again The SYSCON performs the following sequence to ent...

Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...

Page 375: ...al DRAM enter self refresh mode to preserve DRAM contents 4 Disable all PLLs 5 Selectively disable OSCs except 32 768 KHz 6 XPWRRGTON becomes low to power off external voltage regulator To exit the SLEEP mode wake up sources referred in section TODO Wakeup Sources Then the SYSCON performs the following sequence to exit from SLEEP mode 1 Assert wake up reset to low 2 XPWRRGTON becomes high to power...

Page 376: ... power mode To make sure the processor does not ignore wfi instruction it is recommended to make a loop statement around the wfi instruction The loop repeatedly calls wfi instruciton until SYSCON_INT_DISABLE field of OTHERS register to become LOW which indicates low power mode entering sequence is completed ...

Page 377: ...ommand A R M c o m m a n d ARM command A R M c o m m a n d ARM command IDLE wake up sources I D L E w a k e u p s o u r c e s STOP wake up sources S T O P w a k e u p s o u r c e s SLEEP wake up sources System Reset Figure 4 1 State Transition Diagram of Power Mode The wakeup sources described in Figure 4 1 are summarized in Table 4 4 The detail operation is shown Figure 4 2 ...

Page 378: ...isolation cells ISO_EN Change GPIO selection D STOP LOGIC ON Power up sub blocks Change PLL FOUT Enable all clocks Enable DRAM Enable BUS operation Unmask ARMCLK Reset ARM D IDLE LOGIC RET SLEEP SLEEP D IDLE D STOP LOGIC ON D IDLE D STOP LOGIC ON D IDLE LOGIC RET SLEEP IDLE STOP Operation enable disable sequece S W enable disable sequece D IDLE LOGIC ON DIS_ARMCLK EN_ARMCLK STOP_BUS RUN _BUS STOP_...

Page 379: ...I2S in audio sub block wake up event 8 System Timer event 9 CEC wake up event DEEP IDLE TOP block off Set CFG_DIDLE field of IDLE_CFG to 0x1 Set TOP_LOGIC field of IDLE_CFG to 0x1 Set other fields of IDLE_CFG for users need Set CFG_STANDBYWFI field of PWR_CFG to 2 b01 Set SYSCON_INT_DISABLE field of OTHERS to 1 b1 Execute WFI 1 External Interrupt1 2 RTC Alarm 3 RTC TICK 4 Key Pad Press event 5 MMC...

Page 380: ... 20 1 External Interrupt includes OneDRAM Interrupt 2 Depends on their interrupt mask bits Power mode exit condition is met when one of various wakeup sources occurs For more information on wakeup sources refer to 4 6 Wakeup Sources ...

Page 381: ...e In DEEP IDLE and DEEP STOP mode Cortex A8 enters L2RETENTION or POWER OFF mode depending on the selection of L2 retention mode that is IDLE_CFG 27 26 for DEEP IDLE mode and STOP_CFG 27 26 for DEEP STOP mode In SLEEP mode Cortex A8 automatically enters POWER OFF mode Before entry into SLEEP mode state of Cortex A8 must be saved in external memory Figure 4 3 shows the state transition diagram of C...

Page 382: ... POWER OFF STANDBY NORMAL IDLE STOP DEEP IDLE DEEP STOP DEEP IDLE DEEP STOP SLEEP S5PC110 power mode WFI instruction WFI instruction Wakeup event WFI instruction Wakeupevent Wakeup event Cortex A8 power Figure 4 3 Cortex A8 Power Mode Transition Diagram ...

Page 383: ...dby N A Standby N A N A RUN Æ L2RETENTION By register setting and WFI command SYSCON N A L2RETENTION N A L2RETENTION N A RUN Æ POWER OFF By register setting and WFI command SYSCON N A POWER OFF N A POWER OFF POWER OFF STANDBY Æ RUN N A Wakeup by interrupt N A Wakeup by interrupt N A N A L2RETENTION Æ RUN N A N A Wakeup by interrupt N A Wakeup by interrupt N A POWER OFF Æ RUN N A N A Wakeup by inte...

Page 384: ...tes before and after those modes An example of state save and restore is described below Before entering SLEEP mode 1 Save the status of necessary modules 2 Save resume address MMU Memory Management Unit and registers for each Cortex A8 mode SVC FIQ IRQ ABT etc 3 Create and save checksum for security 4 Flush cache if L2 cache is power gated After wake up 1 Proceed to normal system initialization s...

Page 385: ... the system and sets the RTL_ALARM field of WAKEUP_STAT register to 1 After the wake up Cortex A8 can refer the WAKEUP_STAT register to find out the cause of wake up 4 6 3 SYSTEM TIMER System Timer is newly introduced module in S5PC110 It supplements PWM timer which suffers from accumulation of time deviation when operated in variable tick mode On the contrary System Timer is free from such deviat...

Page 386: ...state in NORMAL Power down Should be externally powered off 3 MIPI D PHY MIPI link Run LP ULPS Keep operation or power state in NORMAL LP ULPS Should be externally powered off 4 PLL SYSCON Run Power down Keep operation or power state in NORMAL Power down Should be externally powered off 5 DAC TV Encoder logic Run Power down Keep operation or power state in NORMAL Power down Should be externally po...

Page 387: ...N USB OTG PHY keeps its operation or power state in NORMAL Before entry to DEEP IDLE mode where TOP block is OFF STOP DEEP STOP and SLEEP mode it is recommended that USB OTG PHY enter into Suspend mode 4 7 2 HDMI PHY HDMI PHY has two power modes namely Run and Power down mode In Run mode HDMI PHY sends and receives data normally In Power down mode all power to HDMI PHY is OFF internally In NORMAL ...

Page 388: ...that MIPI D PHY enter into ULPS mode For more details about LP and ULPS mode refer to MIPI D PHY user s manual 4 7 4 PLL PLL has two power modes namely Run and Power down mode In Run mode PLL sends and receives data normally Iop max 2mA 4502A max 1mA 4500B In Power down mode all power to PLL is OFF internally Ipd max 80uA In NORMAL mode both power modes can be used If you want to use PLL then you ...

Page 389: ...L on off after wake up SYSCLK after wake up and before the lock time SYSCLK after the lock time by internal logic IDLE unchanged PLL Output PLL Output DEEP IDLE off on PLL Output PLL Output STOP off on PLL reference clock PLL Output DEEP STOP off on PLL reference clock PLL Output SLEEP off off PLL reference clock PLL reference clock 4 7 5 DAC DAC has two power modes namely Run and Power down mode ...

Page 390: ...to 1 b0 to power off the block RTO is 3 3V signal and becomes 3 3V via level shifter Alive I O also keeps its driving value from power off region before entering DEEP IDLE DEEP STOP mode SYSCON generates the retention control signal CPGI In SLEEP mode internal power to normal I O is OFF and I O power to normal I O is still ON SYSCON generates the retention control signal RTO and CPGI while enterin...

Page 391: ...peripheral circuitry is OFF internally In Power down mode all power to core and peripheral circuitry is OFF In NORMAL mode run or stand by mode can be used Run mode is used when there is read and write access while stand by mode is used when there is no read and write access The change between these two modes can be done by module that has SRAM In IDLE mode and DEEP IDLE mode where TOP block is ON...

Page 392: ... mode is used when there is no read access The decision to move from one mode to another is made by the internal ROM controller If ROM is not in use then it can enter into Power down mode Set the IROM field of NORMAL_CFG register in SYSCON for Entry to and exit from Power down mode In IDLE mode and DEEP IDLE mode where TOP block is ON ROM keeps its operation or power state in NORMAL In DEEP IDLE m...

Page 393: ...ng priorities Hardware Reset Watchdog Reset Warm Reset Software Reset Wakeup Reset 4 9 2 HARDWARE RESET Hardware reset is asserted when the XnRESET pin is driven to low and all units in the system except RTC function module are reset to known states During the hardware reset the following actions take place All internal registers and Cortex A8 go into their pre defined reset state All pins get the...

Page 394: ...gures the PLL with a new frequency value SYSCLK is configured to be PLL output MPLL_CLK immediately after lock time The user should be aware that the crystal oscillator settle down time is not explicitly added by the hardware during the power up sequence The S5PC110 assumes that the crystal oscillation is settled during the power supply settle down period However to ensure the proper operation dur...

Page 395: ... asserted then the following sequence occurs 1 WDT generate time out signal 2 SYSCON invokes reset signals and initialize internal IPs 3 The reset including nRSTOUT will be asserted until the reset counter RST_STABLE is expired 4 9 2 2 Software Reset Software reset is asserted when CPU write 1 to SWRESET register in NORMAL mode During the software reset the following actions occur All units except...

Page 396: ...are deasserted 4 9 2 4 Wakeup Reset Wakeup reset is asserted when a module that has normal F Fs is powered down and the module is powered up again by wakeup events Note that if the module has only retention F Fs wakeup reset is not asserted However in sleep mode wakeup reset is generated to all modules that were powered off regardless of normal F F or retention F F Therefore wakeup reset can be as...

Page 397: ...ON PMU RST_STAT PS_HOLD_CONTROL X X O O SYSCON PMU OSC_CON PWR_CFG EINT_WAKEUP_MASK WAKEUP_MASK PWR_MODE NORMAL_CFG IDLE_CFG STOP_CFG STOP_MEM_CFG SLEEP_CFG OSC_FREQ OSC_STABLE PWR_STABLE MTC_STABLE CLAMP_STABLE WAKEUP_STAT BLK_PWR_STAT OTHERS HDMI_CONTROL USB_PHY_CONTROL MIPI_DPHY_CONTROL ADC_CONTROL DAC_CONTROL INFORM0 6 X O O O RTC RTCCON TICCNT RTCALM ALMSEC ALMMIN ALMHOUR ALMDAY ALMMON ALMYEA...

Page 398: ...AL_CFG 0xE010_C010 R W Configure power manager at NORMAL mode 0xFFFF_FFBF Reserved 0xE010_C014 0xE010_C01C Reserved 0x0000_0000 IDLE_CFG 0xE010_C020 R W Configure power manager at IDLE mode 0x6000_0000 Reserved 0xE010_C024 0xE010_C02C Reserved 0x0000_0000 STOP_CFG 0xE010_C030 R W Configure power manager at STOP mode 0x9600_0000 STOP_MEM_CFG 0xE010_C034 R W Configure memory power at STOP mode 0x000...

Page 399: ...HY_CONTROL 0xE010_E814 R W MIPI DPHY control register 0x0000_0000 ADC_CONTROL 0xE010_E818 R W TS ADC control register 0x0000_0000 PS_HOLD_CONTROL 0xE010_E81C R W PS_HOLD control register 0x0000_5200 Reserved 0xE010_E81C 0xE010_EFFC Reserved 0x0000_0000 INFORM0 0xE010_F000 R W Information register0 0x0000_0000 INFORM1 0xE010_F004 R W Information register1 0x0000_0000 INFORM2 0xE010_F008 R W Informa...

Page 400: ...or can be controlled independently When oscillator pad is disabled oscillation stops and no clock is generated further 4 10 2 1 Clock Control Register OSC_CON R W Address 0xE010_8000 OSC_CON Bit Description Initial State Reserved 31 2 Reserved 0x0000_0000 OSCUSB_EN 1 Control X tal oscillator pad for USB 0 disable 1 enable 1 OSC_EN 0 Control X tal oscillator pad for main oscillator 0 disable 1 enab...

Page 401: ... Reserved 31 20 Reserved 0x000 DIDLE_WAKEUP 19 ARM reset from DEEP IDLE 0 DSTOP_WAKEUP 18 ARM reset from DEEP STOP 0 Reserved 17 Reserved 0 SLEEP_WAKEUP 16 Reset by SLEEP mode wake up 0 Reserved 15 4 Reserved 0x000 SWRESET 3 Software reset by SWRESET 0 nWDTRESET 2 Watch dog timer reset by WDTRST 0 nWRESET 1 Warm reset by XnWRESET 0 nRESET 0 External reset by XnRESET 1 ...

Page 402: ...TANDBYWFI signal is activated by the Cortex A8 00 Ignore 01 Enter IDLE mode 10 Enter STOP mode 11 Enter SLEEP mode 0x0 Reserved 7 0 Reserved 0x00 4 10 4 2 Power Management Register EINT_WAKEUP_MASK R W Address 0xE010_C004 EINT_WAKEUP_MASK Bit Description Initial State EINT_WAKEUP_MASK 31 0 External interrupt wake up mask EINT 31 0 The field affects on NORMAL mode Therefore this field must clear wh...

Page 403: ... up mask for MMC0 0 pass 1 mask 0 Reserved 8 Reserved 0 Reserved 7 Reserved 0 Reserved 6 Reserved 0 KEY 5 Wake up mask for KEY I F 0 pass 1 mask 0 TS1 4 Wake up mask for TSADC1 0 pass 1 mask 0 TS0 3 Wake up mask for TSADC0 0 pass 1 mask 0 RTC_TICK 2 Wake up mask for RTC TICK 0 pass 1 mask 0 RTC_ALARM 1 Wake up mask for RTC Alarm 0 pass 1 mask 0 Reserved 0 Reserved 0 4 10 4 4 Power Mode Register PW...

Page 404: ...rved 6 Reserved 1 CAM 5 Power gating control for X block 0 LP mode OFF 1 Active mode ON 1 TV 4 Power gating control for T block 0 LP mode OFF 1 Active mode ON 1 LCD 3 Power gating control for L block 0 LP mode OFF 1 Active mode ON 1 G3D 2 Power gating control for G3D block 0 LP mode OFF 1 Active mode ON 1 MFC 1 Power gating control for F block 0 LP mode OFF 1 Active mode ON 1 Reserved 0 Reserved 1...

Page 405: ... 01 Retention 10 ON Other Reserved 0x1 TOP_MEMORY 29 28 Configure TOP memory state 01 Retention 10 ON Other Reserved 0x1 ARM_L2CACHE 27 26 Configure ARM L2 cache state in DEEP IDLE mode 00 OFF 01 Retention Other Reserved 0x0 Reserved 25 1 Reserved 0x000_0000 CFG_DIDLE 0 Configure DEEP IDLE setting for Cortex A8 core 0 No DEEP Cortex A8 core power on 1 DEEP Cortex A8 core power off 0 ...

Page 406: ... Configure TOP memory state DO NOT CHANGE 01 OFF Retention According to STOP_MFM_CFG Other Reserved 0x1 ARM_L2CACHE 27 26 Configure ARM L2 cache state in STOP mode When ARM_LOGIC is ON L2CACHE is always ON regardless of this field setting 00 OFF 01 Retention Other Reserved 0x1 ARM_LOGIC 25 24 Configure ARM logic state in STOP D STOP mode 00 OFF D STOP mode 10 ON STOP mode Other Reserved 0x2 Reserv...

Page 407: ...IF 7 Memory retention control for MODEM I F 0 OFF 1 Retention 1 Reserved 6 Reserved 1 USBOTG 5 Memory retention control for USB OTG 0 OFF 1 Retention 1 HSMMC 4 Memory retention control for HSMMC 0 OFF 1 Retention 1 CSSYS 3 Memory retention control for CoreSight 0 OFF 1 Retention 1 SECSS 2 Memory retention control for security sub system 0 OFF 1 Retention 1 IRAM 1 Memory retention control for inter...

Page 408: ...ster SLEEP_CFG R W Address 0xE010_C040 SLEEP_CFG Bit Description Initial State Reserved 31 2 Reserved 0x0000_0000 OSCUSB_EN 1 Control USB X tal Oscillator pad in SLEEP mode 0 disable 1 enable 0 OSC_EN 0 Control X tal oscillator pad in SLEEP mode 0 Disable 1 Enable 0 ...

Page 409: ...10_C108 PWR_STABLE Bit Description Initial State Reserved 31 20 Reserved 0x000 PWR_CNT_VALUE 19 0 20 bit power stable counter value It sets required period of time for external power regulator to be stabilized Whenever external power regulator is turned on corresponding counter increments from zero until it gets 16 times as big as this field value The reference clock for the counter is external os...

Page 410: ...S5PC110_UM 4 POWER MANAGEMENT 4 50 MTC_STABLE counter indicates time required for power supplies to be stabilized when sub block power is turned ON Unless commented use the default values ...

Page 411: ...00 CEC 15 Wake up by HDMI CEC This is cleared by writing 1 0 ST 14 Wake up by system timer This is cleared by writing 1 0 I2S 13 Wake up by I2S within Audio sub system This is cleared by writing 1 0 MMC3 12 Wake up by MMC3 This is cleared by writing 1 0 MMC2 11 Wake up by MMC2 This is cleared by writing 1 0 MMC1 10 Wake up by MMC1 This is cleared by writing 1 0 MMC0 9 Wake up by MMC2 This is clear...

Page 412: ...al State Reserved 31 8 Reserved 0x0 AUDIO 7 Audio block power ready 0 OFF 1 ON 1 Reserved 6 Reserved 0 CAM 5 X block power ready 0 OFF 1 ON 1 TV 4 T block power ready 0 OFF 1 ON 1 LCD 3 L block power ready 0 OFF 1 ON 1 G3D 2 G3D block power ready 0 OFF 1 ON 1 MFC 1 F block power ready 0 OFF 1 ON 1 TOP 0 TOP power ready 0 OFF 1 ON 1 ...

Page 413: ...then set HIGH on this register field to that corresponding PAD starts to work 0 Auto clear 1 RELEASE_RET_GPIO For more information on list of PADs belonging to normal I O pad refer to Section 4 2 PIN SUMMARY of GPIO manual 0 RELEASE_RET_CF_IO 30 RELEASE_RET_CF_IO_IO is retention control signal to CF I O pad If you want to disable RELEASE_RET_CF_IO_IO set to 1 After RELEASE_RET_CF_IO_IO becomes OFF...

Page 414: ...before entering SLEEP mode And then set HIGH on this register field to that corresponding PAD starts to work 0 Auto clear 1 RELEASE_RET_MMC_IO For more information on list of PADs belonging to MMC I O pad refer to Section 4 2 PIN SUMMARY of GPIO manual 0 RELEASE_RET_UART_IO 28 RELEASE_RET_UART_IO is retention control signal to UART I O pad If you want to disable RELEASE_RET_UART_IO set to 1 After ...

Page 415: ...s and sleep mode 00 Clock out signal from SYSCON by CLK_OUT SFR of CMU 01 Reserved 10 XXTI Main X tal input 11 XUSBXTI USB X tal input 0x0 Reserved 7 2 Reserved 0x00 CLEAR_DBGACK 1 Clear DBGACK signal when this field has value 1 Cortex A8 asserts DBGACK signal to indicate the system has entered DEBUG state If DBGACK is asserted this state is stored in PMU until software clears it using this field ...

Page 416: ...AC IP enable selection This bit must be set to 1 at the system initialization step before data access from to DAC begins Caution If DAC is not used in your system do not touch this field 0 disable 1 enable 0 4 10 5 6 MISC Register MIPI_DPHY_CONTROL R W Address 0xE010_E814 MIPI_DPHY_CONTROL Bit Description Initial State Reserved 31 1 Reserved 0x0000_0000 M_RESETN 2 Isolate Connect MIPI_PHY Master L...

Page 417: ...T_EN 0 XEINT 0 pad is controlled by this register values and values of control registers for XEINT 0 of GPIO chapter is ignored when this field is 1 0 disable 1 enable 0 PS_HOLD muxed with XEINT 0 pin value is kept up in any power mode This register is in alive region and reset by XnRESET or power off only 4 10 5 9 MISC Register INFORM0 R W 0xE010_F000 INFORM1 R W 0xE010_F004 INFORM2 R W 0xE010_F0...

Page 418: ... a high level block diagram of a complete IEM solution Power Supply Unit Off chip ARM processor Applications OS Intelligent Energy Manager Software Intelligent Energy Controller Advanced Power Controller Hardware Performance Monitor Clock Management Unit Performance Communication Interface Vdd HPM clock ARM Core clock Power Management Unit System on Chip SoC Figure 5 1 Intelligent Energy Manager S...

Page 419: ...tem event occurs that might influence the optimum performance level The IEM software records information about the events that occur and the related tasks The policies that are a part of the IEM software analyze this information to determine the optimum performance level Whenever the optimum performance level changes the IEM software uses the performance scaling hardware to set the new level 5 1 1...

Page 420: ...ck Power Management Unit AMBA APB Bus Current Voltage Index Target Voltage Index Power request Hardware Performance Monitor ConfigurationInformation Current Voltage Index Target Voltage Index Power Request Maximumperformance request Interrupts Acknowledge Current Frequency Index Target Frequency Index Current Frequency Index Target Frequency Index Interrupts Figure 5 2 IEM Block Diagram ...

Page 421: ...ct platform scaling hardware and to achieve desired system performance Battery life is extended by lowering the operating frequency and voltage of SoC components such as the processor and consequently reducing energy consumption The IEC provides an abstracted view of the SoC specific performance scaling hardware It is responsible for translating the performance prediction made by the IEM software ...

Page 422: ...or efficient control and monitoring Implementation independent fractional performance setting interface to support performance prediction algorithms without hard coded frequencies Implementation independent interrogation of performance level quantization mapping levels to enable performance prediction software to adapt to the processor clock frequencies provided SoC specific configuration interrog...

Page 423: ...and to send out current performance level updates indicating voltage readiness Together with the HPM the APC1 tracks the system timing in real time and sends voltage commands to the EMU to request the adjustment of voltage level The flowchart in Figure 5 3 shows how the adaptive voltage control is processed to find optimum voltage level Figure 5 3 PowerWise Performance Tracking and Voltage Adjustm...

Page 424: ...WI 5 2 1 3 Hardware Performance Monitor The Hardware Performance Monitor HPM is designed for reuse and easy implementation Although it is a separate entity in physical partition the HPM is an integral part of the APC1 for an AVS power management system The HPM is not a memory mapped device An HPM is required for closed loop control but not for an open loop control system The HPM tracks the system ...

Page 425: ...sary clocks for the CPU for example Processor clock Peripheral clocks AMBA clock Additionally for a more efficient design the CMU must be capable to generate the different performance levels as indicated by the IEC The CMU can also be a memory mapped AMBA peripheral and can contain both control and status registers The design of the CMU must meet the requirements set by the IEC and the Advanced Po...

Page 426: ... code in the control component loads the Comms driver that it uses to communicate with the IEM kernel The OS then configures the IEM kernel by issuing commands to the control component The control component encodes these commands as messages and uses the Comms driver to send them to the IEM kernel These control messages Start the policies so that they are ready to use Optionally Configure the IEM ...

Page 427: ...ched out A Task Schedule In system event for the next task that is being switched in The User Input hook is called whenever a task receives user input This hook generates a User Input system event for the task that is receiving input When a kernel hook generates an system event it determines whether any event handlers recognize the system event If so it Creates a structure describing the system ev...

Page 428: ...d requesting that performance level The fast event handler might recognize A specific task such as a movie player A type of task such as real time tasks or tasks that are receiving user input If necessary the fast event handler can get further information about the task by making calls to the OS layer API Storing policy specific information about the current state of the task or the system for lat...

Page 429: ...clude The system event structure describing the event The IEM block describing the task that triggered the system event The standard event handler then processes the event analyzing the data in the IEM kernel data structures and any data that was stored by the fast event handler to determine the optimum performance level The analysis that the standard event handler performs is usually very differe...

Page 430: ...MHz ARM Core Clock Frequency MHz HPM Clock Frequency MHz AXI Bus Clock Frequency MHz ARM Clock Ratio fPLL fARM HPM Clock Ratio fARM fHPM AXI Bus Clock Ratio fPLL fAXI Performance mapping 800 0 100 0 2 100 0 533 3 66 7 3 66 7 400 0 50 0 4 50 0 320 0 40 0 5 40 0 266 7 33 3 6 33 3 228 6 28 6 7 28 6 200 0 25 0 8 25 0 177 8 22 2 9 22 2 1600 160 0 20 0 160 0 10 8 10 20 0 There are divider values for ARM...

Page 431: ...um A B 1_1111 sd_low 1 0 vdd_stable A B slack_reg 5 0 ext_slack 15 0 Sign extender A 5 2 4 hF A 5 2 4 h0 APC_SS_GAIN_EN vdd_stable loop_gain APC_GAIN_SEL APC_SAT_GAIN_EN sd_saturation step_upward APC_IGAIN3 APC_UP_GAIN_EN step_upward APC_IGAIN2 APC_LOW_GAIN_EN sd_low APC_IGAIN4 Default APC_IGAIN1 Sign extender integral integral_reg integral Shifter tgained_slack 22 0 rst_filterq integral 22 h1F_C0...

Page 432: ...tegral is less than or equal to noise_limit_int 4 0 2 Above reference Integral is negative Voltage over supplied Absolute value of Integral is less than APC_OVSHT_LMT 7 0 Low_VDD_timeout Too much time taken to increase voltage step_upward 1 when Integral is positive and step_int_dir 1 APC_UNSHT_NOISE 5 4 00 5 h00 01 5 h10 10 5 h04 11 5 h1F noise_limit_int Undershoot condition 1 Positive slack Volt...

Page 433: ...2X1 cells and each delay tap gives 0 184ns delay Delay tap structure is as shown in Figure 5 6 Figure 5 6 HPM Delay Tap structure in S5PC110 HPM has a predelay module that includes 32 delay tap like delay elements and a delayline module that includes 32 delay taps To correlate with ARM core 14 th tap should be selected with setting predelay_sel 2 0 of HPM 3 b000 when HPM clock ratio is equal to 1 ...

Page 434: ...TIALIZATION SEQUENCE 1 Initialize the index map all other IEM APC mapping values 2 If IEM will use overdrive level then programs Max performance mapping index value in IECDPCCR register with proper values smaller than 3 b111 3 Enables voltage scaling feature in the APC by setting APC_VDD_UD bit in APC_CONTROL register as 1 4 If IEM will use closed loop mode then programs APC_HPM_EN bit APC_LOOP_MO...

Page 435: ...PTION Signal I O Description Pad Type IEM_SCLK Bidirectional PWI clock IEM_SCLK dedicated IEM_SPWI Bidirectional PWI serial data IEM_SPWI dedicated NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals ...

Page 436: ...ation Fractional Index Map64 From PMU IECCFGDVCIDXMAP 0xE080_004C R Configuration DVC Index Map Register From PMU IECCFGDCGPERFMAP0 0xE080_0060 R Configuration Performance Map 0 From PMU IECCFGDCGPERFMAP4 0xE080_0064 R Configuration Performance Map 4 From PMU IECDPMCR 0xE080_0100 R W DPM Command Register 0x000 IECDPM2RATE 0xE080_0108 R W DPM Channel 2 Rate Register 0x80 IECDPM3RATE 0xE080_010C R W...

Page 437: ... IECID2 0xE080_0FF8 R IEC Identification Register 2 0x05 IECID3 0xE080_0FFC R IEC Identification Register 3 0xB1 APC APC_PWICMD 0xE070_0000 R W PWI Command Register 0x00 APC_PWIDATAWR 0xE070_0004 R W PWI Write Data Register 0x00 APC_PWIDATARD 0xE070_0008 R PWI Read Data Register 0x00 APC_CONTROL 0xE070_0010 R W APC Control Register 0x00 APC_STATUS 0xE070_0014 R APC Status Register 0x00 APC_MINVDD_...

Page 438: ...L4_CALCODE 0xE070_008C R W Calibration Code 4 Register 0x1F APC_PL5_CALCODE 0xE070_0090 R W Calibration Code 5 Register 0x1F APC_PL6_CALCODE 0xE070_0094 R W Calibration Code 6 Register 0x1F APC_PL7_CALCODE 0xE070_0098 R W Calibration Code 7 Register 0x1F APC_PL8_CALCODE 0xE070_009C R W Calibration Code 8 Register 0x1F APC_PL1_COREVDD 0xE070_00A0 R W Open loop VDD Core Register 1 0x7F APC_PL2_COREV...

Page 439: ...e Debug Emulation 3 Control to debug performance scaling 0 IEC performance scaling software debug disabled also the reset value 1 IEC performance scaling software debug enabled When this bit is seta the performance level driven out of the IECTGTDVCIDX is set to maximum regardless of the software request The performance level changes are only visible on IECTGTDCGIDX 0 IEC Max Perf Enable 2 Enable d...

Page 440: ...he target fractional performance level At system reset the value 0x80 100 0x80 5 5 2 4 DPC Current Performance Register IECDPCCRNTPERF R Address 0xE080_000C IECDPCCRNTPERF Bit Description Initial State Reserved 31 8 Reserved read undefined do not modify 0 IECDPCCRNTPERF 7 0 Returns the current performance level as indicated to the IEC by the DCG on the IECCRNTDCGIDX inputs System Dependent 5 5 2 5...

Page 441: ...sked Interrupt Status CSMIS 1 Gives the masked interrupt state after masking of the IECCPUSLPINT interrupt The reset value is 0 0 CPU Wake up Masked Interrupt Status CWMIS 0 Gives the masked interrupt state after masking of the IECCPUWUINT interrupt The reset value is 0 0 5 5 2 8 Interrupt Clear Register IECICR W Address 0xE080_001C IECICR Bit Description Initial State Reserved 31 2 Reserved read ...

Page 442: ...MAP 63 32 From PMU 5 5 2 13 Configuration Fractional Index Map32 Register IECCFGDCGIDXMAP64 R Address 0xE080_0048 IECCFGDCGIDXMAP64 Bit Description Initial State IECCFGDCGIDXMAP64 31 0 State of IECCFGDCGIDXMAP 95 64 From PMU 5 5 2 14 Configuration DVC Index Map Register IECCFRDVCIDXMAP R Address 0xE080_004C IECCFGDVCIDXMAP Bit Description Initial State 31 24 Reserved read undefined do not modify 0...

Page 443: ...scription Initial State 31 8 Reserved read undefined do not modify 0 IECDPM2RATE 7 0 The fractional rate that DPM channel 2 counts The reset value of this register is 0x80 that is 100 0x80 5 5 2 19 DPM Channel Rate Registers IECDPM3RATE R W Address 0xE080_010C IECDPM3RATE Bit Description Initial State 31 8 Reserved read undefined do not modify 0 IECDPM3RATE 7 0 The fractional rate that DPM channel...

Page 444: ...ECDPM2HI Bit Description Initial State IECDPM2HI 31 0 High 32 bits of DPM channel 2 The reset value is 0x00000000 0x00000000 5 5 2 24 DPM Channel Registers IECDPM3LO R Address 0xE080_0190 IECDPM3LO Bit Description Initial State IECDPM3LO 31 0 Low 32 bits of DPM channel 3 The reset value is 0x00000000 0x00000000 5 5 2 25 DPM Channel Registers IECDPM3HI R Address 0xE080_0194 IECDPM3HI Bit Descriptio...

Page 445: ...or programmed rate This reduces the testing time required to ensure that all bits of the counters toggle correctly 0 DVS Emulation Slot Counter Test 1 Enable or disable test mode for the bus V slotcounter 0 DVS emulation slot counter test mode disabled also reset value 1 DVS emulation slot counter test mode enabled When this bit is set the 10 bit DVS emulation slot timing counter is split up into ...

Page 446: ... return the value of the IECDPMCLKEN input at the output of the test multiplexer The reset value is 0 0 IECDVSEMCLKEN 2 Intra chip input Writes to this bit set the value to be driven onto the input IECDVSEMCLKEN in the integration test mode Reads return the value of the IECDVSEMCLKEN input at the output of the test multiplexer The reset value is 0 0 IECCPUWFIACK 1 Intra chip input Writes to this b...

Page 447: ...value is 0x00 0x00 5 5 2 30 Integration Test Output Read or Set Registers IECITOP1 R W Address 0xE080_0F20 IECITOP1 Bit Description Initial State 31 4 Reserved read undefined do not modify 0 IECSYNCMODEREQ 3 Intra chip output Writes to this bit set the value to be driven onto the IECSYNCMODEREQ output in integration test mode Reads return the value of IECSYNCMODEREQ at the output of the test multi...

Page 448: ...set the value to be driven onto the IECTGTDVCIDX 7 0 outputs in integration test mode Reads return the value of IECTGTDVCIDX 7 0 at the output of the test multiplexer The reset value is 0x00 0x00 5 5 2 33 Peripheral Identification Register 0 IECPeriphID0 R Address 0xE080_0FE0 IECPeriphID0 Bit Description Initial State Reserved 31 8 Reserved read undefined do not modify X Partnumber0 7 0 These bits...

Page 449: ... are read back as 0x3 0x3 5 5 2 38 Peripheral Identification Register 5 IECPeriphID5 R Address 0xE080_0FD4 IECPeriphID5 Bit Description Initial State Reserved 31 8 Reserved read undefined do not modify X Configuration 3 7 0 Number of DVS slots in a frame These bits read back as 0x08 0x08 5 5 2 39 Peripheral Identification Register 6 IECPeriphID6 R Address 0xE080_0FD8 IECPeriphID6 Bit Description I...

Page 450: ...CID1 Bit Description Initial State 31 8 Reserved read undefined do not modify X IECID1 7 0 These bits read back as 0xF0 0xF0 5 5 2 43 IEC Identification Register 2 IECID2 R Address 0xE080_0FF8 IECID2 Bit Description Initial State 31 8 Reserved read undefined do not modify X IECID2 7 0 These bits read back as 0x05 0x05 5 5 2 44 IEC Identification Register 3 IECID3 R Address 0xE080_0FFC IECID3 Bit D...

Page 451: ...ticate 4 b0010 Register read 4 b0011 Register write 4 b0100 Wakeup 4 b0101 Sleep 4 b0110 Shutdown 4 b1001 Synchronize Unused command patterns result in a No Operation NOP at the PWI interface 0x0 5 5 3 2 PWI Write Data Register APC_PWIDATAWR R W Address 0xE070_0004 APC_PWIDATAWR Bit Description Initial State PWI Slave Write Data 7 0 Data is written to the PWI slave 0x00 5 5 3 3 PWI Read Data Regis...

Page 452: ...sabling closed loop mode when pll is unstable 0 APC_LOOP_MODE 1 Enable bit for the closed loop or the open loop mode defaults to the open loop mode setting this bit enables the closed loop mode The voltage scaling in the open loop or the closed loop mode is enabled only after setting the APC_VDD_UD bit of the APC_CONTROL Register 0 APC_VDD_UD 0 Enables voltage scaling feature in the APC1 defaults ...

Page 453: ...hkd counter 0x00 5 5 3 9 VDD Pre delay Select Register APC_PREDYSEL R W Address 0xE070_0024 APC_PREDYSEL Bit Description Initial State Reserved 7 3 Read undefined Write as zero 0 Pre delay 2 0 Selects the predelay value for the HPM 0x7 5 5 3 10 APC Interrupt Mask Register APC_IMASK R W Address 0xE070_0028 APC_IMASK Bit Description Initial State Reserved 7 Read undefined Write as zero 0 APB Write D...

Page 454: ...osed loop mode indicating that the dynamic compensator is not able to increase the voltage to the required level for the new higher performance level within the maximum time period set by the hardware 0 Undershoot Interrupt 0 In the closed loop AVS operation for a performance level change after reaching the optimum voltage the APC1 asserts an interrupt if the voltage correction continues and resul...

Page 455: ...e threshold level for the detection of voltage undershoot interrupt on the voltage slew The value programmed is the amount of eHPM ve allowed after reaching the optimum core voltage for the safe SoC operation 0x0 5 5 3 14 Wakeup Delay Register APC_WKUP_DLY R W Address 0xE070_0038 APC_WKUP_DLY Bit Description Initial State Wakeup Delay 7 0 Count for the wakeup delay 0x00 5 5 3 15 Slack Sample Count...

Page 456: ...APC_GAIN2 term for the dynamic compensator This gain term is selected during voltage upward slew 0 APC_LOW_GAIN_EN 1 Enables the APC_GAIN4 term for the dynamic compensator This gain term is selected when the slack or eHPM value is between 3 to 3 0 APC_SAT_GAIN_EN 0 Enables the APC_GAIN3 term for the dynamic compensator This gain term is selected when the PC value is saturated and the voltage is st...

Page 457: ...erm are one to ten Rest of the values are treated as zero in the closed loop AVS operations 0x0 5 5 3 22 Integrator s Gain Registers APC_IGAIN3 R W Address 0xE070_0068 APC_IGAIN3 Bit Description Initial State Reserved 7 4 Read undefined Write as zero 0 Gain 3 3 0 Dynamic compensator uses this gain term for the saturated HPM output when enabled The programmable values for this gain term are one to ...

Page 458: ...3 25 Integration Test Input Read or Set Registers APC_ITSTIP1 R W Address 0xE070_0070 APC_ITSTIP1 Bit Description Initial State Reserved 7 Undefined Write as zero 0 HPM_DELAY _CODE 4 0 6 2 In integration test mode write drives the hpm_delay_code inputs to the design read returns the register content In normal mode write updates the register read returns the data from the hpm_delay_code primary inp...

Page 459: ...074 APC_ITSTIP2 Bit Description Initial State Reserved 7 N Read undefined Write as zero 0 APC_TARGET_INDEX N 1 0 In integration test mode write drives the apc_target_index inputs to the design read returns the register content In normal mode write updates the register read returns the data from the apc_target_index primary inputs 0x00 ...

Page 460: ...ode write drives the apc_clamp_reqprimary output read returns the register content In normal mode write updates the register read returns the data from the apc_clamp_req signal of the design 0 APC_INTERRUPT 2 In integration test mode write drives the apc_interruptprimary output read returns the register content In normal mode write updates the register read returns the data from the apc_interrupt ...

Page 461: ...ster content In normal mode write updates the register read returns the data from the apc_current_index signals of the design 0x00 5 5 3 29 Integration Test Output Read or Set Registers APC_ITSTOP3 R W Address 0xE070_00C4 APC_ITSTOP3 Bit Description Initial State Reserved 7 1 Read undefined Write as zero 0 APC_HPM_AUTH_SET 0 In integration test mode write drives the apc_hpm_auth_set primary output...

Page 462: ...gisters are eight 5 bit registers Their names are APC_PL1_CALCODE APC_PL8_CALCODE They give delay information target for closed loop operation APC_PL _CALCODE Bit Description Initial State Reserved 7 5 Read undefined Write as zero X Reference Calibrated Code 1 4 0 The RCC for performance level 0x1F Open loop VDD Core Registers APC_PL1_COREVDD R W Address 0xE070_00A0 Open loop VDD Core Registers AP...

Page 463: ...on voltage level for performance level zero 0x00 5 5 3 32 Debug Performance Registers APC_DBG_DLYCODE R Address 0xE070_00E0 APC_DBG_DLYCODE Bit Description Initial State Reserved 7 5 Read undefined 0 Performance Code 4 0 The PC of the HPM 0x00 5 5 3 33 Revision Number Registers APC_REV R Address 0xE070_00FC APC_REV Bit Description Initial State Revision Number 7 0 Holds the APC1 revision number 0x...

Page 464: ...erted not only on booting time but also on wakeup from low power modes Therefore the iROM code must execute appropriate process according to the reset status refer to Table 6 1 The boot loader is largely composed of iROM first and second boot loaders The characteristics of these boot loaders are iROM code Contains small and simple code which is platform independent and stored in internal memory Fi...

Page 465: ...roller After initializing DRAM controller it loads OS image from the booting device to DRAM According to the secure boot key values the second boot loader can do an integrity check on the OS image After the booting completes the second boot loader jumps to the operating system The iROM code reads the OM pins to find the booting device The OM register provides the OM pin and other information requi...

Page 466: ...group0 Since the contents of DRAM memory are preserved in the SLEEP mode it does not require loading the OS image to DRAM However SoC internal power is not supplied to internal logic during SLEEP mode and all contents in internal SRAM are not preserved Therefore the first boot loader and the second boot loader should be loaded again This reset status is classified as reset group1 At the time of so...

Page 467: ...S5PC110_UM 6 BOOTING SEQUENCE 6 4 6 2 2 BOOTING SEQUENCE EXAMPLE Figure 6 2 shows the flow chart related to total booting code sequence Figure 6 2 Total Booting Code Sequence Flow Chart ...

Page 468: ...y check 8 If integrity check passes then jump to the first boot loader in iRAM 0xD002_0010 The booting sequence in internal SRAM is as follows 1 Load the second boot loader from boot device to iRAM 2 If secure booting is successful execute integrity check 3 If integrity check passes then jump to the second boot loader in iRAM The jumping address depends on user s software 4 If integrity check fail...

Page 469: ...IV X 2 SDIV 1 800MHz MPLL M 667 P 12 S 1 FOUT MDIV X FIN PDIV X 2SDIV 667MHz EPLL M 80 P 3 S 3 K 0 FOUT MDIV KDIV X FIN PDIV X 2SDIV 80MHz Table 6 2 shows the system clock frequencies for various external crystals after initialization of the PLL by first boot loader Table 6 2 First Boot Loader s Clock Speed at 24 MHz External Crystal ARMCLK ACLK200 HCLK200 PCLK100 HCLK100 HCLK166 PCLK83 SCLK_FIMC ...

Page 470: ...udi X TAL USB 1 b0 X TAL 1 b0 1 b1 1 b1 OnenandDemux Audi X TAL USB 1 b0 X TAL 1 b0 1 b1 SD MMC X TAL USB 1 b0 X TAL 1 b0 1 b1 1 b1 1 b1 1 b1 eMMC 4 bit X TAL USB 1 b0 X TAL 1 b1 1 b1 NAND 2 KB 5cycle 16 bit bus 4 bit ECC X TAL USB 1 b0 X TAL 1 b0 1 b1 1 b1 NAND 2 KB 4cycle NAND 8 bit ECC X TAL USB 1 b0 X TAL 1 b0 1 b1 iROM NOR boot X TAL USB 1 b0 X TAL 1 b0 1 b1 1 b0 1 b1 1 b1 1 b1 I ROM eMMC 8 b...

Page 471: ...L 1 b1 1 b1 1 b1 eMMC 4 bit X TAL USB NOTE The first boot loader tries to negotiate UART first If it fails then it tries to drive the USB device Hence you have to disconnect the UART device if you want to boot using USB device The hardware logic decides address mapping and the software routine decides other booting options The value of OM pin can be read from OM register which is described in Chap...

Page 472: ...gion Then first boot loader verifies the integrity of the second boot loader the second boot loader verifies the integrity of the OS image Figure 6 3 shows the secure booting diagram The secure booting sequence is as follows The iROM code 1 Checks the integrity of RSA public key using E fuse RSA key hash value 2 Loads the first boot loader to iRAM 3 Checks the integrity of first boot loader using ...

Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...

Page 474: ...Section 3 BUS ...

Page 475: ... 1 1 About Coresight Systems Generals 2 1 2 1 2 Key Features of Coresight 2 2 2 2 Debug Access Port 2 7 2 2 1 About Debug Access Port 2 7 2 3 ETB 2 9 2 3 1 About the ETB 2 9 2 3 2 About the ECT 2 10 3 Access Controller TZPC 3 1 3 1 Overview of Access Controller TZPC 3 1 3 1 1 Key Features of Access Controller TZPC 3 1 3 1 2 Block Diagram of Access Controller TZPC 3 1 3 2 Functional Description 3 2...

Page 476: ...tion of LRG Arbitration Scheme 1 5 Figure 2 1 DAP Connections Inside a SoC Cross Triggering 2 3 Figure 2 2 S5PC110 Coresight Structure 2 4 Figure 2 3 Debugger Register Map of S5PC110 2 5 Figure 2 4 Structure of the Coresight DAP Components 2 8 Figure 2 5 ETB Block Diagram ECT CTI CTM 2 9 Figure 2 6 Coresight CTI and CTM Block Diagram 2 10 Figure 3 1 Block Diagram of Access Controller TZPC 3 1 ...

Page 477: ...List of Tables Table Title Page Number Number Table 2 1 Authentication Signal Rule 2 6 Table 3 1 TZPC Table 3 3 Table 3 2 TZPC Transfer Attribute 3 4 Table 3 3 TZPC Registers 3 5 ...

Page 478: ... is reached it permits transactions from specified masters only This scheme only provides support for slaves that have a combined acceptance capability such as the Dynamic Memory Controller DMC The QoS scheme has no effect until the AXI interconnect matrix calculates the following At a particular Master Interface MI there are a number of outstanding transactions equal to the value stored in QoS ti...

Page 479: ...ad and write transactions from different SIs The arbitration policy is decided by the values of SFRs An arbitration decision taken in the current cycle does not affect the current cycle If no SIs are active the arbiter adopts default arbitration that is the highest priority SI If default arbitration occurs and the highest priority SI becomes active in the same cycle as or before any other SI then ...

Page 480: ...re rotated so that the slot in the highest priority position becomes the lowest and all other slots move to a higher priority but maintain their relative order as shown in Figure 1 2 This means that if an SI is the highest priority active SI but is not the highest priority interface then it continues to win the arbitration until it becomes the highest priority interface and then the lowest priorit...

Page 481: ...vent other masters in its group from accessing the slave If you configure all master priorities to different levels the arbiter implements a fixed priority scheme This occurs because in this case each master is in a group of its own and therefore masters maintain their ordering If all master priorities are the same then an LRG scheme is implemented The reason all master priorities behave as LRG is...

Page 482: ...nchronizer configuration register 0x0000_0001 ASYNC_CONFIG4 0xF1A0_0000 R W Synchronizer configuration register 0x0000_0001 ASYNC_CONFIG5 0xF1B0_0000 R W Synchronizer configuration register 0x0000_0001 ASYNC_CONFIG6 0xF1C0_0000 R W Synchronizer configuration register 0x0000_0001 ASYNC_CONFIG7 0xF1D0_0000 R W Synchronizer configuration register 0x0000_0001 ASYNC_CONFIG8 0xF1E0_0000 R W Synchronizer...

Page 483: ...1 HALF_SYNC_SEL field of ASYNC_CONFIG0 10 registers decides whether to use half or full synchronization for synchronizer which separates two different clock domains Setting this field to HIGH selects half synchronizer which has better performance over full synchronizer On the contrary full synchronizer has a better MTBF Mean Time Between Failure resulting from crossing clock domains It is recommen...

Page 484: ...e debug with the core halted using Breakpoints and watchpoints to halt the core on specific activity A debug connection to examine and modify registers and memory and provide single step execution Conventional monitor debug This is invasive debug with the core running using a debug monitor that resides in memory Trace This is non invasive debug with the core running at full speed using Collection ...

Page 485: ...gn The DAP provides the following advantages for multi core SoC designs There is no requirement to run at the lowest common speed A slow or powered down component has no effect on access to other components This means that power management has minimal impact on debug The number of devices in the system does not affect the access speed You have direct access to individual devices You can add third ...

Page 486: ...t different signal types A set of standard triggers for cores are predefined and you can add triggers for third party cores The ECT enables tool developers to supply a standard control dialog so that software programmers can connect trigger events 2 1 2 2 Trace The CoreSight Design Kit provides components that support a standard infrastructure for the capture and transmission of trace data combina...

Page 487: ...10 S5PC110 is single processor system with CortexA8 core Its main bus system is based on AMBA3 AXI interconnects It does not support Serial Wire debug port protocol Figure 2 2 shows configuration of debugging system Figure 2 2 S5PC110 Coresight Structure 2 4 ...

Page 488: ...0_4000 0x0000_3000 or 0x8000_3000 0x0000_2000 or 0x8000_2000 0x0000_1000 or 0x8000_1000 0x0000_0000 or 0x8000_0000 0xE0D0_7000 0xE0D0_6000 0xE0D0_5000 0xE0D0_4000 0xE0D0_3000 0xE0D0_2000 0xE0D0_1000 0xE0D0_0000 SecureJTAG 0xE0D0_8000 0x0000_8000 or 0x8000_8000 Figure 2 3 Debugger Register Map of S5PC110 2 1 2 4 Authentication for Secure JTAG Operation S5PC110 supports Secure JTAG by using authenti...

Page 489: ...GEN NIDEN SPIDEN SPNIDEN JTAG unplugged 0 X X 0 0 0 0 non protected mode secure invasive 1 0 X 1 1 1 1 JTAG and authenticated as secure invasive 1 1 4 1 1 1 1 JTAG and authenticated as secure non invasive 1 1 3 1 1 0 1 JTAG and authenticated as non secure invasive 1 1 2 1 1 0 0 JTAG and authenticated as non secure non invasive 1 1 1 0 1 0 0 JTAG and non authenticated 1 1 0 0 0 0 0 The authenticati...

Page 490: ...The DAP enables debug access to the complete SoC using a number of master ports Access to the CoreSight Debug Advanced Peripheral Bus APB is enabled through the APB Access Port APB AP and APB Multiplexer APB MUX and system access through the Advanced High performance Bus Access Port AHB AP The DAP comprises of following interface blocks External debug access using the JTAG Debug Port External JTAG...

Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...

Page 492: ...er the data is read back out of the ETB Control Control registers for trace capture and flushing APB interface Read write and data pointers provide access to ETB registers In addition the APB interface supports wait states through the use of a PREADYDBG signal output by the ETB The APB interface is synchronous to the ATB domain Register bank Contains the management control and status registers for...

Page 493: ... core to another so that program execution on both processors can be stopped at the same time if required Cross Trigger Interface CTI The CTI combines and maps the trigger requests and broadcasts them to all other interfaces on the ECT as channel events When the CTI receives a channel event it maps this onto a trigger output This enables subsystems to cross trigger with each other The receiving an...

Page 494: ...of memory as secure or non secure The S5PC110 comprises of four TZPC 3 1 1 KEY FEATURES OF ACCESS CONTROLLER TZPC Protection bits This enables you to program maximum 32 areas of memory as secure or non secure Secure region bits This enables you to split an area of internal RAM into both secure and non secure regions The Access Controller includes AMBA APB system interface 3 1 2 BLOCK DIAGRAM OF AC...

Page 495: ...You can use this to split the RAM into two regions One secure One non secure This enables the best use of memory and other system resources It is assumed that the specific secure and non secure requirements for an application are determined during Boot up OS or secure kernel port development work This means that the secure and non secure memory partitioning is not expected to change dynamically du...

Page 496: ...N UBLOCK 2 DMC0 GPIO GBLOCK 3 DMC1 HDMI_LINK AUDIO I2S0 4 MDMA 5 INTC 6 MFC DSIM IEM_APC I2S2 TZPCDECPROT0 7 G3D CSIS IEM_IEC PCM2 0 PDMA0 1 SDM PDMA1 2 I2C_HDMI_PHY CORESIGHT 3 4 I2C_HDMI_DDC SPDIF 5 PCM1 6 SPI0 TZPCDECPROT1 7 LBLOCK SPI1 0 MDNIE SPI2 1 KEYIF 2 TSADC 3 I2C0 general 4 I2C PMIC 5 I2S1 6 AC97 TZPCDECPROT2 7 PCM0 0 1 PWM 2 ST 3 WDT 4 RTC 5 UART 6 SBLOCK TZPCDECPROT3 7 CBLOCK TZPCR0SI...

Page 497: ...udes I2S0 If non secure master accesses to secure slave area DECERR occurs Table 3 2 TZPC Transfer Attribute Master Attribute Transfer Attribute Slave Area Attribute Response Secure Transfer Secure Slave Area OK Secure Transfer Non Secure Slave Area OK Non Secure Transfer Secure Slave Area DECERR Secure Master Non Secure Transfer Non Secure Slave Area OK ...

Page 498: ...ifies the Decode Protection 2 Status Register 0x00000000 TZPCDECPROT2Set 0xF150_081C W Specifies the Decode Protection 2 Set Register TZPCDECPROT2Clr 0xF150_0820 W Specifies the Decode Protection 2 Clear Register TZPCDECPROT3Stat 0xF150_0824 R Not used 0x00000000 TZPCDECPROT3Set 0xF150_0828 W Not used TZPCDECPROT3Clr 0xF150_082C W Not used TZPCPERIPHID0 0xF150_0FE0 R Specifies the TZPC Peripheral ...

Page 499: ... Register TZPCDECPROT3Stat 0xFAD0_0824 R Not used 0x00000000 TZPCDECPROT3Set 0xFAD0_0828 W Not used TZPCDECPROT3Clr 0xFAD0_082C W Not used TZPCPERIPHID0 0xFAD0_0FE0 R Specifies the TZPC Peripheral Identification Register 0 0x00000070 TZPCPERIPHID1 0xFAD0_0FE4 R Specifies the TZPC Peripheral Identification Register 1 0x00000018 TZPCPERIPHID2 0xFAD0_0FE8 R Specifies the TZPC Peripheral Identificatio...

Page 500: ...al Identification Register 0 0x00000070 TZPCPERIPHID1 0xE060_0FE4 R Specifies the TZPC Peripheral Identification Register 1 0x00000018 TZPCPERIPHID2 0xE060_0FE8 R Specifies the TZPC Peripheral Identification Register 2 0x00000000 TZPCPERIPHID3 0xE060_0FEC R Specifies the TZPC Peripheral Identification Register 3 0x00000004 TZPCPCELLID0 0xE060_0FF0 R Specifies the TZPC Identification Register 0 0x0...

Page 501: ...d TZPCDECPROT3Clr 0xE1C0_082C W Not used TZPCPERIPHID0 0xE1C0_0FE0 R Specifies the TZPC Peripheral Identification Register 0 0x00000070 TZPCPERIPHID1 0xE1C0_0FE4 R Not used 0x00000018 TZPCPERIPHID2 0xE1C0_0FE8 R Not used 0x00000004 TZPCPERIPHID3 0xE1C0_0FEC R Not used 0x00000000 TZPCPCELLID0 0xE1C0_0FF0 R Specifies the TZPC Identification Register 0 0x0000000D TZPCPCELLID1 0xE1C0_0FF4 R Not used 0...

Page 502: ...otection 0 3 Status Registers TZPCDECPROTxSTAT TZPC0 R Address 0xF150_0800 0xF150_080C 0xF150_0818 TZPCDECPROTxSTAT TZPC1 R Address 0xFAD0_0800 0xFAD0_080C 0xFAD0_0818 TZPCDECPROTxSTAT TZPC2 R Address 0xE060_0800 0xE060_080C 0xE060_0818 TZPCDECPROTxSTAT TZPC3 R Address 0xE1C0_0800 0xE1C0_080C 0xE1C0_0818 TXPCDECPROTxStat Bit Description Initial State Reserved 31 8 Read undefined 0 DECPROTxStat 7 0...

Page 503: ...egion to non secure There is one bit of the register for each protection output eight outputs are implemented as standard 3 4 1 4 Decode Protection 0 2 Clear Registers TZPCDECPROTxClr TZPC0 W Address 0xF150_0808 0xF150_081C 0xF150_0820 TZPCDECPROTxClr TZPC1 W Address 0xFAD0_0808 0xFAD0_081C 0xFAD0_0820 TZPCDECPROTxClr TZPC2 W Address 0xE060_0808 0xE060_081C 0xE060_0820 TZPCDECPROTxClr TZPC3 W Addr...

Page 504: ...undefined 0 Designer0 7 4 These bits read back as 0x1 0x1 Partnumber1 3 0 These bits read back as 0x8 0x8 3 4 1 7 TZPC Peripheral Identification Register 2 TZPCPERIPHID2 R Address 0xF150_0FE8 0xFAD0_0FE8 0xE060_0FE8 0xE1C0_0FE8 TZPCPERIPHID2 Bit Description Initial State Reserved 31 8 Read undefined 0 Revision 7 4 These bits read back as the revision number which can be 0 15 0x0 Designer1 3 0 Thes...

Page 505: ...PCELLID1 Bit Description Initial State Reserved 31 8 Read undefined 0 TZPCPCELLID1 7 0 These bits read back as 0xF0 0xF0 3 4 1 11 Identification RegisteR 2 TZPCPCELLID2 R Address 0xF150_0FF8 0xFAD0_0FF8 0xE060_0FF8 0xE1C0_0FF8 TZPCPCELLID2 Bit Description Initial State Reserved 31 8 Read undefined 0 TZPCPCELLID2 7 0 These bits read back as 0x05 0x05 3 4 1 12 Identification RegisteR 3 TZPCPCELLID3 ...

Page 506: ...Section 4 INTERRUPT ...

Page 507: ...errupt Controller 1 1 1 1 Overview of Vectored Interrupt Controller 1 1 1 1 1 Key Features of Vectored Interrupt Controller 1 1 1 2 Nterrupt Source 1 2 1 3 Functional Description 1 6 1 4 Register Description 1 7 1 4 1 Register Map 1 7 ...

Page 508: ...rrupt and masks the interrupt source s from the interrupt controller on the non secure side of the system VIC Use the latter to generate nIRQ signal To generate nFIQ from the non secure interrupt sources the TZIC0 takes the nNSFIQIN signal from the non secure interrupt controller 1 1 1 KEY FEATURES OF VECTORED INTERRUPT CONTROLLER Supports 93 vectored IRQ interrupts Fixed hardware interrupts prior...

Page 509: ...VIC port no No INT Request Remark 31 127 30 126 29 125 28 124 27 123 26 122 25 121 24 120 23 119 22 118 21 117 20 116 19 115 18 114 17 113 16 112 15 111 14 110 13 109 12 108 11 107 10 106 PENDN1 TSADC 9 105 ADC1 TSADC 8 104 7 103 6 102 5 101 4 100 TSI 3 99 CEC 2 98 MMC3 1 97 VIC3 Multimedia Audio Security Etc 0 96 VIC2 31 95 SDM_FIQ security ...

Page 510: ...SADC 23 87 ADC TSADC 22 86 SPDIF 21 85 PCM1 20 84 PCM0 19 83 AC97 18 82 17 81 I2S1 16 80 I2S0 15 79 TVENC 14 78 MFC 13 77 I2C_HDMI_DDC 12 76 HDMI 11 75 Mixer 10 74 3D 9 73 2D 8 72 JPEG 7 71 FIMC2 6 70 FIMC1 5 69 FIMC0 4 68 ROTATOR 3 67 2 66 LCD 2 1 65 LCD 1 Multimedia Audio Security Etc 0 64 LCD 0 31 63 ONENAND_AUDI 30 62 MIPI_DSI 29 61 MIPI_CSI 28 60 HSMMC2 VIC1 ARM power memory 27 59 HSMMC1 ...

Page 511: ... AUDIO_SS 17 49 16 48 SPI1 15 47 SPI0 14 46 I2C0 13 45 UART3 12 44 UART2 11 43 UART1 10 42 UART0 9 41 CFC 8 40 NFC 7 39 6 38 IEM_IEC 5 37 IEM_APC 4 36 CORTEX4 nCTIIRQ 3 35 CORTEX3 nDMAEXTERIRQ 2 34 CORTEX2 nDMAIRQ 1 33 CORTEX1 nDMASIRQ Connectivity Storage 0 32 CORTEX0 nPMUIRQ 31 31 FIMC3 30 30 GPIOINT All other GPIO interrupt mux 29 29 RTC_TIC 28 28 RTC_ALARM VIC0 System DMA Timer 27 27 WDT ...

Page 512: ...A0 18 18 MDMA 17 17 16 16 EINT 16_31 EXT_INT 16 31 15 15 EINT15 EXT_INT 15 14 14 EINT14 EXT_INT 14 13 13 EINT13 EXT_INT 13 12 12 EINT12 EXT_INT 12 11 11 EINT11 EXT_INT 11 10 10 EINT10 EXT_INT 10 9 9 EINT9 EXT_INT 9 8 8 EINT8 EXT_INT 8 7 7 EINT7 EXT_INT 7 6 6 EINT6 EXT_INT 6 5 5 EINT5 EXT_INT 5 4 4 EINT4 EXT_INT 4 3 3 EINT3 EXT_INT 3 2 2 EINT2 EXT_INT 2 1 1 EINT1 EXT_INT 1 0 0 EINT0 EXT_INT 0 ...

Page 513: ...110_UM 1 VECTORED INTERRUPT CONTROLLER 1 6 1 3 FUNCTIONAL DESCRIPTION When user clears interrupt pending user must write 0 to all the VICADDRESS registers VIC0ADDRESS VIC1ADDRESS VIC2ADDRESS and VIC3ADDRESS ...

Page 514: ...0_0108 R W Specifies the Vector Address 2 Register 0x00000000 VIC0VECTADDR3 0xF200_010C R W Specifies the Vector Address 3 Register 0x00000000 VIC0VECTADDR4 0xF200_0110 R W Specifies the Vector Address 4 Register 0x00000000 VIC0VECTADDR5 0xF200_0114 R W Specifies the Vector Address 5 Register 0x00000000 VIC0VECTADDR6 0xF200_0118 R W Specifies the Vector Address 6 Register 0x00000000 VIC0VECTADDR7 ...

Page 515: ...F VIC0VECTPRIORITY3 0xF200_020C R W Specifies the Vector Priority 3 Register 0xF VIC0VECTPRIORITY4 0xF200_0210 R W Specifies the Vector Priority 4 Register 0xF VIC0VECTPRIORITY5 0xF200_0214 R W Specifies the Vector Priority 5 Register 0xF VIC0VECTPRIORITY6 0xF200_0218 R W Specifies the Vector Priority 6 Register 0xF VIC0VECTPRIORITY7 0xF200_021C R W Specifies the Vector Priority 7 Register 0xF VIC...

Page 516: ...00_0FE8 R Specifies the Peripheral Identification Register bit 23 16 0x04 VIC0PERIPHID3 0xF200_0FEC R Specifies the Peripheral Identification Register bit 31 24 0x00 VIC0PCELLID0 0xF200_0FF0 R Specifies the PrimeCell Identification Register bit 7 0 0x0D VIC0PCELLID1 0xF200_0FF4 R Specifies the PrimeCell Identification Register bit 15 9 0xF0 VIC0PCELLID2 0xF200_0FF8 R Specifies the PrimeCell Identi...

Page 517: ...14 Register 0x00000000 VIC1VECTADDR15 0xF210_013C R W Specifies the Vector Address 15 Register 0x00000000 VIC1VECTADDR16 0xF210_0140 R W Specifies the Vector Address 16 Register 0x00000000 VIC1VECTADDR17 0xF210_0144 R W Specifies the Vector Address 17 Register 0x00000000 VIC1VECTADDR18 0xF210_0148 R W Specifies the Vector Address 18 Register 0x00000000 VIC1VECTADDR19 0xF210_014C R W Specifies the ...

Page 518: ...Specifies the Vector Priority 17 Register 0xF VIC1VECTPRIORITY18 0xF210_0248 R W Specifies the Vector Priority 18 Register 0xF VIC1VECTPRIORITY19 0xF210_024C R W Specifies the Vector Priority 19 Register 0xF VIC1VECTPRIORITY20 0xF210_0250 R W Specifies the Vector Priority 20 Register 0xF VIC1VECTPRIORITY21 0xF210_0254 R W Specifies the Vector Priority 21 Register 0xF VIC1VECTPRIORITY22 0xF210_0258...

Page 519: ...rrupt Clear Register VIC2PROTECTION 0xF220_0020 R W Specifies the Protection Enable Register 0x0 VIC2SWPRIORITYMASK 0xF220_0024 R W Specifies the Software Priority Mask Register 0xFFFF VIC2PRIORITYDAISY 0xF220_0028 R W Specifies the Vector Priority Register for Daisy Chain 0xF VIC2VECTADDR0 0xF220_0100 R W Specifies the Vector Address 0 Register 0x00000000 VIC2VECTADDR1 0xF220_0104 R W Specifies t...

Page 520: ...00000000 VIC2VECTADDR29 0xF220_0174 R W Specifies the Vector Address 29 Register 0x00000000 VIC2VECTADDR30 0xF220_0178 R W Specifies the Vector Address 30 Register 0x00000000 VIC2VECTADDR31 0xF220_017C R W Specifies the Vector Address 31 Register 0x00000000 VIC2VECPRIORITY0 0xF220_0200 R W Specifies the Vector Priority 0 Register 0xF VIC2VECTPRIORITY1 0xF220_0204 R W Specifies the Vector Priority ...

Page 521: ...78 R W Specifies the Vector Priority 30 Register 0xF VIC2VECTPRIORITY31 0xF220_027C R W Specifies the Vector Priority 31 Register 0xF VIC2ADDRESS 0xF220_0F00 R W Specifies the Vector Address Register 0x00000000 VIC2PERIPHID0 0xF220_0FE0 R Specifies the Peripheral Identification Register bit 7 0 0x92 VIC2PERIPHID1 0xF220_0FE4 R Specifies the Peripheral Identification Register bit 15 9 0x11 VIC2PERI...

Page 522: ...egister 0x00000000 VIC3VECTADDR10 0xF230_0128 R W Specifies the Vector Address 10 Register 0x00000000 VIC3VECTADDR11 0xF230_012C R W Specifies the Vector Address 11 Register 0x00000000 VIC3VECTADDR12 0xF230_0130 R W Specifies the Vector Address 12 Register 0x00000000 VIC3VECTADDR13 0xF230_0134 R W Specifies the Vector Address 13 Register 0x00000000 VIC3VECTADDR14 0xF230_0138 R W Specifies the Vect...

Page 523: ...F230_0230 R W Specifies the Vector Priority 12 Register 0xF VIC3VECTPRIORITY13 0xF230_0234 R W Specifies the Vector Priority 13 Register 0xF VIC3VECTPRIORITY14 0xF230_0238 R W Specifies the Vector Priority 14 Register 0xF VIC3VECTPRIORITY15 0xF230_023C R W Specifies the Vector Priority 15 Register 0xF VIC3VECTPRIORITY16 0xF230_0240 R W Specifies the Vector Priority 16 Register 0xF VIC3VECTPRIORITY...

Page 524: ...ster 0x00000000 TZIC0RawIntr 0xF280_0004 R Specifies the Raw Interrupt Status Register TZIC0IntSelect 0xF280_0008 R W Specifies the Interrupt Select Register 0x00000000 TZIC0FIQEnable 0xF280_000C R W Specifies the FIQ Enable Register 0x00000000 TZIC0FIQENClear 0xF280_0010 W Specifies the FIQ Enable Clear Register TZIC0FIQBypass 0xF280_0014 R W Specifies the FIQ Bypass Register 0x00000000 TZIC0Prot...

Page 525: ...0000B1 TZIC2FIQStatus 0xF2A0_0000 R Specifies the FIQ Status Register 0x00000000 TZIC2RawIntr 0xF2A0_0004 R Specifies the Raw Interrupt Status Register TZIC2IntSelect 0xF2A0_0008 R W Specifies the Interrupt Select Register 0x00000000 TZIC2FIQEnable 0xF2A0_000C R W Specifies the FIQ Enable Register 0x00000000 TZIC2FIQENClear 0xF2A0_0010 W Specifies the FIQ Enable Clear Register TZIC2FIQBypass 0xF2A...

Page 526: ...3Protection 0xF2B0_0018 R W Specifies the Protection Register 0x00000000 TZIC3Lock 0xF2B0_001C W Specifies the Lock Enable Register TZIC3LockStatus 0xF2B0_0020 R Specifies the Lock Status Register 0x00000001 TZIC3PeriphID0 0xF2B0_0FE0 R Specifies the Peripheral Identification Registers 0x00000090 TZIC3PeriphID1 0xF2B0_0FE4 R 0x00000018 TZIC3PeriphID2 0xF2B0_0FE8 R 0x00000004 TZIC3PeriphID3 0xF2B0_...

Page 527: ...nterrupt is active There is one bit of the register for each interrupt source 0x00000000 1 4 1 3 Raw Interrupt Status Register VICRAWINTR R Address 0xF200_0008 0xF210_0008 0xF220_0008 0xF230_0008 VICRAWINTR Bit Description Initial State RawInterrupt 31 0 Shows the status of the FIQ interrupts before masking by the VICINTENABLE and VICINTSELECT Registers 0 Interrupt is inactive before masking 1 Int...

Page 528: ... 0x00000000 1 4 1 6 Interrupt Enable Clear VICINTENCLEAR W Address 0xF200_0014 0xF210_0014 0xF220_0014 0xF230_0014 VICINTENCLEAR Bit Description Initial State IntEnable Clear 31 0 Clears corresponding bits in the VICINTENABLE Register 0 No effect 1 Disables Interrupt in VICINTENABLE Register There is one bit of the register for each interrupt source 1 4 1 7 Software Interrupt Register VICSOFTINT R...

Page 529: ... Enables Protection mode If enabled only privileged mode accesses reads and writes can access the interrupt controller registers that is if HPROT 1 is set HIGH for the current transfer If disabled both user mode and privileged mode can access the registers This register can only be accessed in privileged mode even if protection mode is disabled 0x0 1 4 1 10 Vector Address Register VICADDRESS R W A...

Page 530: ...CTADDR 0 31 Bit Description Initial State VectorAddr 0 31 31 0 Contains ISR vector addresses 0x00000000 1 4 1 13 Vector Priority Registers VICVECTPRIORITY 0 31 and VICVECTPRIORITYDAISY R W Address 0xF200_0200 027C 0xF210_0200 027C 0xF220_0200 027C 0xF230_0200 027C VICVECTPRIORITY 0 31 and VICVECTPRIORITYDAISY Bit Description Initial State Reserved 31 4 Reserved read as 0 do not modify 0x0 VectPrio...

Page 531: ... 0x0 Revision 7 4 These bits read back as the revision number which can be between 0 and 15 0x0 Designer1 3 0 These bits read back as 0x4 0x4 1 4 1 17 VICPERIPHID3 Register VICPERIPHID3 R Address 0xF200_0FEC 0xF210_0FEC 0xF220_0FEC 0xF230_0FEC VICPERIPHID3 Bit Description Initial State 31 8 Reserved read as 0 do not modify 0x0 Configuration 7 2 These bits read back as 0x0 0x0 Configuration 1 0 Ind...

Page 532: ...it Description Initial State 31 8 Reserved read as 0 do not modify 0x0 VICPCellID3 7 0 These bits read back as 0xB1 0xB1 1 4 1 22 FIQ Status Register TZICFIQStatus R Address 0xF280_0000 0xF290_0000 0xF2A0_0000 0xF2B0_0000 TZICFIQStatus Bit Description Initial State FIQStatus 31 0 Shows the status of the interrupts after masking by the TZICFIQIntEnable and TZICFIQIntEnClear Registers A HIGH bit ind...

Page 533: ...0 Disables Interrupt 1 Enables Interrupt To enable the interrupt use this register You must use the TZICFIQEnClear Register to disable the interrupt enable Write 0 No effect 1 Enables Interrupt If Reset it disables all interrupts There is 1 bit of the register for each interrupt source 0x00000000 1 4 1 26 FIQ Enable Clear Register TZICFIQENClear W Address 0xF280_0010 0xF290_0010 0xF2A0_0010 0xF2B0...

Page 534: ...ption Initial State Lock 31 0 To enable access to the other registers in the TZIC you must write the correct access code of 0x0ACCE550 to this register To disable access to the other TZIC registers you must write any other value except 0x0ACCE550 to this register 1 4 1 30 Lock Status Register TZICLockStatus R Address 0xF280_0020 0xF290_0020 0xF2A0_0020 0xF2B0_0020 TZICLockStatus Bit Description In...

Page 535: ...umber and can be between 0 and 15 0x0 Designer1 3 0 These bits read back as 0x4 0x4 1 4 1 34 Peripheral Identification Register TZICPeriphID3 R Address 0xF280_0FEC 0xF290_0FEC 0xF2A0_0FEC 0xF2B0_0FEC TZICPeriphID3 Bit Description Initial State 31 8 Read undefined 0x0 Configuration 7 0 These bits read back as 0x00 0x0 1 4 1 35 Identification Register TZICPCellID0 R Address 0xF280_0FF0 0xF290_0FF0 0...

Page 536: ...F8 TZICPCellID2 Bit Description Initial State 31 8 Read undefined 0x0 TZICPCellID2 7 0 These bits read back as 0x05 0x05 1 4 1 38 Identification Register TZICPCellID3 Register R Address 0xF280_0FFC 0xF290_0FFC 0xF2A0_0FFC 0xF2B0_0FFC TZICPCellID3 Bit Description Initial State 31 8 Read undefined 0x0 TZICPCellID3 7 0 These bits read back as 0xB1 0xB1 ...

Page 537: ...Section 5 MEMORY ...

Page 538: ...ures of SROM Controller 2 1 2 1 3 Block Diagram of SROM Controller 2 1 2 2 Functional Description 2 2 2 2 1 nWAIT Pin Operation 2 2 2 2 2 Programmable Access Cycle 2 3 2 3 I O Description 2 4 2 4 Register Description 2 5 2 4 1 Register Map 2 5 3 OneNAND Controller 3 1 3 1 Overview of OneNAND Controller 3 1 3 2 Key Features of OneNAND Controller 3 1 3 3 Controller Usage Expectations 3 2 3 4 Functio...

Page 539: ...on 4 14 4 5 Register Description 4 15 4 5 1 Register Map 4 15 4 5 2 Nand Flash Interface and 1 4 bit ecc registers 4 17 4 5 3 ECC Registers for 8 12 and 16 bit ecc 4 26 5 Compact Flash Controller 5 1 5 1 Overview of Compact Flash Controller 5 1 5 2 Key Features of Compact Flash Controller 5 1 5 3 Block Diagram of Compact Flash Controller 5 2 5 4 Functional Description 5 2 5 5 True IDE Mode PIO PDM...

Page 540: ......

Page 541: ...t B AHB Master Port and C OneNAND Interface Port 3 3 Figure 3 2 OneNAND Accesses OneNAND Controller Address 0xB0000000 0xB01FFFFF by the External AHB Master ARM Processor 3 9 Figure 3 3 Control Register Accesses OneNAND Controller Address 0xB0600000 0xB07FFFFF by the External AHB Master ARM Processor 3 10 Figure 3 4 ONENAND_IF_CTRL OneNAND Interface Control Register Update Flow 3 13 Figure 3 5 ONE...

Page 542: ...am 5 7 Figure 5 5 UDMA In Operation Terminated by Device 5 9 Figure 5 6 UDMA In Operation Terminated by Host 5 10 Figure 5 7 UDMA Out Operation Terminated by Device 5 10 Figure 5 8 UDMA Out Operation Terminated by Host 5 11 Figure 5 9 Flowchart for Abort in ATA Mode 5 13 Figure 6 1 Memory Interface Through EBI 6 2 Figure 6 2 Clock Scheme of Memory Controllers and EBI 6 3 ...

Page 543: ...e 3 1 OneNAND Controller Memory Map 3 6 Table 3 2 OneNAND Chip 0 nCE 0 Address Map If the OneNAND device is Connected to nCE 0 3 7 Table 3 3 Flex OneNAND Chip 0 nCE 0 Address Map If the Flex OneNAND device is Connected to nCE 0 3 8 Table 5 1 Timing Parameter Each PIO Mode 5 5 Table 5 2 MDMA Timing Parameters 5 7 Table 5 3 Timing Parameter Each UDMA Mode 5 11 Table 5 4 True IDE Mode I O Decoding 5 ...

Page 544: ...ith JEDEC DDR2 low power DDR and low power DDR2 SDRAM specification Uses the SEC LPDDR2 PHY interface to support high speed memory devices Supports up to two external chip selects and 1 2 4 8 banks per one chip Supports 128 Mb 256 Mb 512 Mb 1 Gb 2 Gb and 4 Gb density Memory Devices Supports 16 32 bit wide memory data width Optimized pipeline stage for low latency Supports QoS scheme to ensure low ...

Page 545: ...t also acts as a read FIFO if AXI Master is not ready and has an APB interface for special function registers direct commands and an AXI low power channel interface The Scheduler block uses the memory bank Finite State Machine FSM information to arbitrate the bus transactions in the command queues and transforms the commands into a memory command type which is sent to the Memory interface block It...

Page 546: ...et the ConControl At this moment an auto refresh counter should be off 6 Set the MemControl At this moment all power down modes should be off 7 Set the MemConfig0 register If there are two external memory chips also set the MemConfig1 register 8 Set the PrechConfig and PwrdnConfig registers 9 Set the TimingAref TimingRow TimingData and TimingPower registers according to memory AC parameters 10 If ...

Page 547: ... should be off 6 Set the MemControl At this moment all power down modes should be off 7 Set the MemConfig0 register If there are two external memory chips set the MemConfig1 register 8 Set the PrechConfig and PwrdnConfig registers 9 Set the TimingAref TimingRow TimingData and TimingPower registers according to memory AC parameters 10 If QoS scheme is required set the QosControl0 15 and QosConfig0 ...

Page 548: ...ording to clock frequency and memory tAC parameters 4 Set the PhyControl0 ctrl_start bit field to 1 5 Set the ConControl At this moment an auto refresh counter should be off 6 Set the MemControl At this moment all power down modes should be off 7 Set the MemConfig0 register If there are two external memory chips set the MemConfig1 register 8 Set the PrechConfig and PwrdnConfig registers 9 Set the ...

Page 549: ...ion Mode and to program the operating parameters 26 If there are two external memory chips perform steps 14 25 for chip1 memory device 27 Set the ConControl to turn on an auto refresh counter 28 If power down modes is required set the MemControl registers 1 2 2 ADDRESS MAPPING The controller modifies the address of the bus transaction coming from the AXI slave port into a memory address chip selec...

Page 550: ...ss Mapping As shown in Figure 1 2 the linear mapping method maps the AXI address in the order of bank row column and width Since the bank address does not change for at least one bank size applications that use linear address mapping have a high possibility to access the same bank ...

Page 551: ...d a row size interleaved mapping accesses a different bank Therefore applications that use interleaved mapping access numerous banks This improves the performance but increases power consumption 1 2 3 LOW POWER OPERATION The DRAM controller executes a low power memory operation in five ways namely AXI Low power channel Dynamic power down Dynamic self refresh Clock stop Direct command Each feature ...

Page 552: ...rom power down state and executes in a normal operation state 1 2 3 3 Dynamic Self Refresh Similar to the dynamic power down feature Refer to Section 2 3 2 Dynamic Power Down if the command queue is empty for a specific amount of cycles PwrdnConfig dsref_cyc bit field the memory device enters self refresh mode Since exiting power down mode requires many cycles we recommend to choose a greater cycl...

Page 553: ... a bank that uses an open page policy and other applications to a bank that uses a close page auto precharge policy Open Page Policy After a READ or WRITE the accessed row is left open Close Page Auto Precharge Policy Right after a READ or WRITE command the controller issues an auto precharge to the bank 1 2 4 2 Timeout Precharge If a certain bank uses an open page policy the row is left open afte...

Page 554: ...commands that are in the control queue There are three types of QoS namely qos_cnt qos_cnt_f default_qos 1 2 5 1 qos_cnt There are 16 configurable QoSControls which have independent qos_masks that masks the ARID AWID from one bit up to the ARID AWID width All 16 QoSControls are either enabled or disabled 1 If the command is received via the AXI bus the ARID AWID is masked by the qos_masks QoSConfi...

Page 555: ...cnt_f value that is specified for the IP is applied to the command to give a higher QoS priority over other IP commands For write transactions for example when the IP s FIFO is more than 3 4th full there is almost no margin of time available before the FIFO becomes full At this moment if the IP flags the memory controller through it s index path the qos_cnt_f QoSControl index qos_cnt_f value that ...

Page 556: ...ed Table 1 1 shows the QoS fast index of each IP Table 1 1 Fast Qos index table qos_fast index Master 0 Reserved 1 Reserved 2 Reserved 3 Reserved 4 FIMD window0 5 FIMD window4 6 FIMD window1 7 FIMD window2 8 FIMD window3 9 FIMC0 10 FIMC1 11 FIMC2 12 Reserved 13 VP 14 MIXER_GRP0 15 MIXER_GRP1 1 2 5 3 Default Qos If qos_cnt is not applied to the command a default QoS counter Is set to a different va...

Page 557: ...sing the shifted DQS the PHY samples the read data and saves the data into the read data input FIFO which is located inside the PHY Then the controller fetches the data from the PHY while considering the read latency and the read fetch delay and then sends it to the AXI read channel The following figures show the read data capture process s timing diagram for each memory type Figure 1 6 Timing Dia...

Page 558: ...FIFO the controller sends the read data to the AXI read channel in read latency 1 read fetch cycles The read fetch cycle is set using the ConControl rd_fetch bit field Figure 1 7 Timing Diagram of Read Data Capture DDR2 non zero delay RL 3 rd_fetch 2 Figure 1 7 is different from Figure 1 6 because a delay exists Negedge sampling happens at T5 and T6 which is one cycle slower than T4 T5 shown in Fi...

Page 559: ... Therefore rd_fetch must have minimum one value Figure 1 8 Timing Diagram of Read Data Capture LPDDR LPDDR2 zero delay RL 3 rd_fetch 1 An LPDDR LPDDR2 does not have an internal DLL Without an internal DLL as shown in Figure 1 8 the data is sent out after tDQSCK before the read latency is over Even if we assume zero delay since tDQSCK becomes relatively large in high frequencies the read fetch cycl...

Page 560: ...10_UM 1 DRAM CONTROLLER 1 17 Figure 1 9 Timing Diagram of Read Data Capture LPDDR LPDDR2 non zero delay RL 3 rd_fetch 2 If a delay exists as shown in Figure 1 9 a bigger value should be assigned to rd_fetch ...

Page 561: ...ncies as shown in Figure 1 10 In this situation negedge sampling happens before read latency and therefore read fetch is set to zero To calculate the LPDDR LPDDR2 rd_fetch value rd_fetch LPDDR LPDDR2 INT 1 Delay 0 5T 0 25T T INT Delay T 0 25 Delay board delay PHY input delay T clock period INT x the rounded up integer value of x Therefore if the value of Delay T is less than 0 25 rd_fetch is set t...

Page 562: ... Row Address Selection Xm1RASn dedicated CASn O Column Address Selection Xm1CASn dedicated WEn O Write Enable Xm1WEn dedicated DATA 31 0 I O Memory Data Bus Xm1DATA 31 0 dedicated DQM 3 0 O Write Masking Per Byte Xm1DQM 3 0 dedicated DQSp 3 0 I O Data Strobe Signal Per Byte Xm1DQS 3 0 dedicated DQSn 3 0 I O Data Strobe Negative Signal Per Byte Xm1DQSn 3 0 dedicated ADCT 18 0 CKE O Memory Address B...

Page 563: ... ADDR_13 ADDR_13 ADDR_13 Xm1ADDR 14 BA_0 BA_0 BA_0 BA_0 Xm1ADDR 15 BA_1 BA_1 BA_1 BA_1 Xm1CSn 1 CS_1 BA_2 BA_2 CS_1 Xm1CSn 0 CS_0 CS_0 CS_0 CS_0 CS_0 Xm1CKE 1 CKE_1 ADDR_14 ADDR_14 CKE_1 Xm1CKE 0 CKE_0 CKE_0 CKE_0 CKE_0 CKE_0 NOTE 1 Address Config 1 The Number of Banks MEMCONFIGn chip_bank is set under 4banks and the Number of Row Address Bits MEMCONFIGn chip_row is set under 14bits 2 Address Conf...

Page 564: ...ifies the AC Timing Register for SDRAM Row 0x0F23_3286 TIMINGDATA 0xF000_0038 R W Specifies the AC Timing Register for SDRAM Data 0x1213_0204 TIMINGPOWER 0xF000_003C R W Specifies the AC Timing Register for Power Mode of SDRAM 0x0E1B_0422 PHYSTATUS 0xF000_0040 R Specifies the PHY Status Register 0x0000_000X CHIP0STATUS 0xF000_0048 R Specifies the Memory Chip0 Status Register 0x0000_0000 CHIP1STATU...

Page 565: ...ice Control Register 8 0x0000_0000 QOSCONFIG8 0xF000_00A4 R W Specifies the Quality of Service Configuration Register 8 0x0000_0000 QOSCONTROL9 0xF000_00A8 R W Specifies the Quality of Service Control Register 9 0x0000_0000 QOSCONFIG9 0xF000_00AC R W Specifies the Quality of Service Configuration Register 9 0x0000_0000 QOSCONTROL10 0xF000_00B0 R W Specifies the Quality of Service Control Register ...

Page 566: ...ster for SDRAM Row 0x0F233286 TIMINGDATA 0xF140_0038 R W Specifies the AC Timing Register for SDRAM Data 0x12130204 TIMINGPOWER 0xF140_003C R W Specifies the AC Timing Register for Power Specifies the Mode of SDRAM 0x0E1B0422 PHYSTATUS 0xF140_0040 R Specifies the PHY Status Register 0x0000000X CHIP0STATUS 0xF140_0048 R Specifies the Memory Chip0 Status Register 0x00000000 CHIP1STATUS 0xF140_004C R...

Page 567: ...onfiguration Register 8 0x00000000 QOSCONTROL9 0xF140_00A8 R W Specifies the Quality of Service Control Register 9 0x00000000 QOSCONFIG9 0xF140_00AC R W Specifies the Quality of Service Configuration Register 9 0x00000000 QOSCONTROL10 0xF140_00B0 R W Specifies the Quality of Service Control Register 10 0x00000000 QOSCONFIG10 0xF140_00B4 R W Specifies the Quality of Service Configuration Register 1...

Page 568: ...ctable latency of read data coming from memory devices by tDQSCK variation or the board flying time The read fetch delay of PHY read FIFO must be controlled by this parameter The controller will fetch read data from PHY after read_latency n mclk cycles Refer to 1 2 6 Read Data Capture R W 0x1 qos_fast_en 11 Enables adaptive QoS 0x0 Disables 0x1 Enables If enabled the controller loads QoS counter v...

Page 569: ...ifferent Chips 0x0 Disables 0x1 Enables To prevent collision between reads from two different memory devices a one cycle gap is required Enable this register to insert the gap automatically for continuous reads from two different memory devices R W 0x1 aref_en 5 Auto Refresh Counter 0x0 Disables 0x1 Enables Enable this to decrease the auto refresh counter by 1 at the rising edge of the mclk R W 0x...

Page 570: ... Reserved R W 0x2 mem_type 11 8 Type of Memory 0x0 Reserved 0x1 LPDDR 0x2 LPDDR2 0x3 Reserved 0x4 DDR2 0x5 0xf Reserved R W 0x1 add_lat_pall 7 6 Additional Latency for PALL 0x0 0 cycle 0x1 1 cycle 0x2 2 cycle 0x3 3 cycle If all banks precharge command is issued the latency of precharging will be tRP add_lat_pall R W 0x0 dsref_en 5 Dynamic Self Refresh 0x0 Disables 0x1 Enables Refer to 1 2 3 3 Dyna...

Page 571: ...Timeout Precharge dpwrdn_type 3 2 Type of Dynamic Power Down 0x0 Active Precharge power down 0x1 Force precharge power down 0x2 0x3 Reserved Refer to 1 2 3 2 Dynamic Power Down R W 0x0 dpwrdn_en 1 Dynamic Power Down 0x0 Disable 0x1 Enable R W 0x0 clk_stop_en 0 Dynamic Clock Control 0x0 Always running 0x1 Stops during idle periods Refer to 1 2 3 4 Clock Stop R W 0x0 ...

Page 572: ...0xF8 then AXI offset address becomes 0x0000_0000 0x07FF_FFFF If AXI base address of memory chip0 is 0x2000_0000 then memory chip0 has an address range of 0x2000_0000 0x27FF_FFFF R W DMC0 0xF0 DMC1 0xE0 chip_map 15 12 Address Mapping Method AXI to Memory 0x0 Linear bank row column width 0x1 Interleaved row bank column width 0x2 Mixed1 if bank MSB 1 b1 1 b1 bank except MSB row column width else 1 b0...

Page 573: ...0 then AXI offset address becomes 0x0000_0000 0x0FFF_FFFF If AXI base address of memory chip1 is 0x2800_0000 then memory chip1 has an address range of 0x2800_0000 0x37FF_FFFF R W DMC0 0xF0 DMC1 0xE0 chip_map 15 12 Address Mapping Method AXI to memory 0x0 Linear bank row column width 0x1 Interleaved row bank column width 0x2 Mixed1 if bank MSB 1 b1 1 b1 bank except MSB row column width else 1 b0 ro...

Page 574: ...trol chip0 1_empty before issuing a direct command You must disable dynamic power down dynamic self refresh and force precharge function MemControl register MRS EMRS and MRR commands should be issued if all banks are in idle state If MRS EMRS and MRR is issued to LPDDR2 the CA pins must be mapped as follows MA 7 0 cmd_addr 1 0 cmd_bank 2 0 cmd_addr 12 10 OP 7 0 cmd_addr 9 2 R W 0x0 Reserved 23 21 ...

Page 575: ...ve Policy 0x0 Open page policy 0x1 Close page auto precharge policy chip1_policy n n is the bank number of chip1 Open Page Policy After a READ or WRITE the row accessed before is left open Close Page Auto Precharge Policy Right after a READ or WRITE command memory devices automatically precharges the bank This is a bank selective precharge policy For example if chip1_policy 2 is 0x0 bank2 of chip1...

Page 576: ...If DQS is coming with read latency plus n mclk cycles this registers must be set to n mclk cycles R W 0x0 ctrl_dfdqs 3 Differential DQS If enabled PHY generates differential DQS out signals for write command and receives differential DQS input signals for read command This function is used in case of DDR2 LPDDR2 R W 0x0 ctrl_half 2 DLL Low Speed HIGH active signal to activate the low speed mode fo...

Page 577: ...D Refresh CMD R efres h CM D DLL Lock St art DLL Loc ked Read W rit e Ref res h Period DLL on DLL off W rite c trl_s tart_point v alue Write ctr l_inc value NOTE PHY DLL Lock Procedure Figure 1 11 DLL Lock Procedure Use DLL to compensate Process Voltage and Temperature PVT condition Therefore DLL should not be turned off for reliable operation except for the case of frequency scaling To lower freq...

Page 578: ...trl_offsetc 14 8 Delay Offset for DQS Cleaning Gate offset amount for DDR If this field is fixed this value should not be changed during operation This value is valid after ctrl_resync becomes HIGH and LOW ctrl_offsetc 6 1 tFS fine step delay GATEout delay amount ctrl_offsetc 5 0 x tFS ctrl_offsetc 6 0 GATEout delay amount ctrl_offsetc 5 0 x tFS R W 0x0 ctrl_ref 7 4 Reference Count for DLL Lock Co...

Page 579: ...D L tE C K io _ ck _o u t A B C D F ee d b ac k t A C NOTE DQS Cleaning Scheme Figure 1 12 Board Level Connection Diagram for DQS Cleaning tA I O output delay tB Package bonding wire delay tC Package board delay tD Board trace delay tE I O input delay tDL delay line delay tAC minimum CK to DQS timing of LPDDR DDR2 memory spec LPDDR 1ns DDR2 0 5tCK tFS Fine step delay in DLL From PhyStatus0 ctrl_lo...

Page 580: ...tV ctrl_offsetc 6 0 If ctrl_shiftc 2 0 is 3 b100 tF is Tperiod 8 0 9375ns If tCK is 7 5ns If ctrl_offsetc 6 0 is 7 b00010_00 tV is 0 320ns 40ps 8 worst case if tFS 40ps Therefore tDL tF tV 0 9375ns 0 320ns 1 2575ns Figure 1 13 DQS Cleaning for LPDDR if tAC Min Figure 1 14 DQS Cleaning for LPDDR if tAC Max ...

Page 581: ...resh Entry 0xn n aclk cycles If the command queue is empty for n 1 cycles the controller forces the memory device into self refresh state Refer to 1 2 3 3 Dynamic Self Refresh R W 0xFFFF Reserved 15 8 Should be zero 0x0 dpwrdn_cyc 7 0 Number of Cycles for Dynamic Power Down Entry 0xn n aclk cycles If the command queue is empty for n 1 cycles the controller forces the memory device into active prec...

Page 582: ...h to Active Auto refresh command period in cycles t_rfc T mclk should be greater than or equal to the minimum value of memory tRFC R W 0xF t_rrd 23 20 Active bank A to Active bank B delay in cycles t_rrd T mclk should be greater than or equal to the minimum value of memory tRRD R W 0x2 t_rp 19 16 Precharge command period in cycles t_rp T mclk should be greater than or equal to the minimum value of...

Page 583: ...l read to Precharge command delay in cycles t_rtp T mclk should be greater than or equal to the minimum value of memory tRTP t_rtp must be 0x1 in case of JEDEC LPDDR R W 0x1 cl 19 16 CAS Latency for LPDDR DDR DDR2 in cycles cl should be greater than or equal to the minimum value of memory CL R W 0x3 Reserved 15 12 Should be zero 0x0 wl 11 8 Write data latency for only LPDDR2 in cycles wl should be...

Page 584: ... mclk should be greater than or equal to the minimum value of memory tXSR In case of DDR DDR2 this value should be greater than or equal to the minimum value of memory tXSRD R W 0x1B t_xp 15 8 Exit power down to next valid command delay in cycles t_xp T mclk should be greater than or equal to the minimum value of memory tXP R W 0x4 t_cke 7 4 CKE minimum pulse width minimum power down mode duration...

Page 585: ...k_value 9 2 number of delay cells for coarse lock ctrl_lock_value 1 0 control value for fine lock R 0x0 Reserved 3 Should be zero 0x0 ctrl_locked 2 DLL Lock 0 Unlocks DLL 1 Locks DLL R 0x0 ctrl_flock 1 Fine Lock Information It is indicated that DLL is locked with fine resolution phase offset error is less than 80ps R 0xX ctrl_clock 0 Coarse Lock Information It is indicated that DLL changes step de...

Page 586: ...The current state of bank 4 of memory chip0 R 0x0 bank3_state 15 12 The current state of bank 3 of memory chip0 R 0x0 bank2_state 11 8 The current state of bank 2 of memory chip0 R 0x0 bank1_state 7 4 The current state of bank 1 of memory chip0 R 0x0 bank0_state 3 0 The current state of bank 0 of memory chip0 0x0 Idle precharged 0x1 MRS EMRS 0x2 Deep power down 0x3 Self refresh 0x4 Auto refresh 0x...

Page 587: ... The current state of bank 4 of SDRAM chip1 R 0x0 bank3_state 15 12 The current state of bank 3 of SDRAM chip1 R 0x0 bank2_state 11 8 The current state of bank 2 of SDRAM chip1 R 0x0 bank1_state 7 4 The current state of bank 1 of SDRAM chip1 R 0x0 bank0_state 3 0 The current state of bank 0 of SDRAM chip1 0x0 Idle precharged 0x1 MRS EMRS 0x2 Deep power down 0x3 Self refresh 0x4 Auto refresh 0x5 Pr...

Page 588: ...0xFFFF 1 4 1 18 Memory Mode Registers Status Register MrStatus Read Only Address 0xF000_0054 0xF140_0054 MRSTATUS Bit Description R W Initial State Reserved 31 8 Should be zero 0x0 mr_status 7 0 Mode Registers Status R 0x0 1 4 1 19 PHY Test Register 0 PhyTest0 R W Address 0xF000_0058 0xF140_0058 PHYTEST0 Bit Description R W Initial State ctrl_fb_cnt4 31 24 Count Value for Control Channel R 0x0 Res...

Page 589: ...tate Reserved 31 28 Should be zero 0x0 qos_cnt 27 16 QoS Cycles 0xn n aclk cycles The matched ARID AWID uses this value for its timeout counters instead of ConControl timeout_cnt R W 0x0 qos_cnt_f 15 4 QoS cycles for fast request 0xn n aclk cycles When Concontrol qos_fast_en is enabled and input pin qos_fast n bit is 1 this qos_cnt_f value is loaded to the timeout counter R W 0x0 Reserved 3 1 Shou...

Page 590: ... W 0x0 qos_id 15 0 QoS ID This is used to compare with the masked ARID AWID to check whether its timeout counter should be used for QoS After applying the qos_mask to these ARID AWID it is compared with qos_id The qos_id would be 0b001100_0000 using the example above Comparing the masked ID if the result is equal to the qos_id then the QoSControl0 qos_cnt is applied to this ARID AWID transaction f...

Page 591: ...1_0001_0010 FIMD window 4 FIMD_W1 R W 14 b000_0000_0101_0010 FIMD window 1 FIMD_W2 R W 14 b000_0001_0101_0010 FIMD window 2 FIMD_W3 R W 14 b000_0010_0101_0010 FIMD window 3 G2D R W 14 b000_xxxx_1001_0010 VP R W 14 b000_0xxx_x010_0010 MIXER_GRP0 R W 14 b000_0000_0110_0010 MIXER_GRP1 R W 14 b000_0000_1110_0010 SSYS R W 14 b000_0000_0011_0010 GSYS R W 14 b000_0000_0111_0010 ESYS0 R W 14 b000_0000_101...

Page 592: ...R W 14 b000_0001_0001_1011 FIMD window 4 FIMD_W1 R W 14 b000_0000_0101_1011 FIMD window 1 FIMD_W2 R W 14 b000_0001_0101_1011 FIMD window 2 FIMD_W3 R W 14 b000_0010_0101_1011 FIMD window 3 G2D R W 14 b000_xxxx_1001_0011 VP R W 14 b000_0xxx_x010_1011 MIXER_GRP0 R W 14 b000_0000_0110_1011 MIXER_GRP1 R W 14 b000_0000_1110_1011 SSYS R W 14 b000_0000_0011_0011 GSYS R W 14 b000_0000_0111_0011 ESYS0 R W 1...

Page 593: ... Supports SRAM various ROMs and NOR flash memory Supports only 8 or 16 bit data bus only 16 bit data bus for BANK0 Address space Up to 16MB per Bank Supports 6 banks Fixed memory bank start address External wait to extend the bus cycle Supports byte and half word access for external memory 2 1 3 BLOCK DIAGRAM OF SROM CONTROLLER SROM DECODER SFR CONTROL STATE MACHINE SROM I F SIGNAL GENERATO N AHB ...

Page 594: ...memory bank is enabled the external nWAIT pin should prolong the duration of nOE while the memory bank is active nWAIT is checked from tacc 1 nOE will be deasserted at the next clock after sampling nWAIT is high The nWE signal has the same relation with nOE signal tRC Tacs Tcos Tacc 4 HCLK ADDR nGCS nOE nWAIT DATA R Delayed Sampling nWAIT Figure 2 2 SROM Controller nWAIT Timing Diagram ...

Page 595: ... 2 cycle Tacp 2 cycle Tcos 2 cycle Tcoh 2 cycle Tacc 3 cycle Tcah 2 cycle Figure 2 3 SROM Controller Read Timing Diagram HCLK ADDR nGCS DATA W Tacs Tacc Tcoh Tcah ADDRESS nWE Tcos DATA Tacs 2 cycle Tacp don t care Tcos 2 cycle Tcoh 2 cycle Tacc 3 cycle Tcah 2 cycle Figure 2 4 SROM Controller Write Timing Diagram NOTE Page mode is only supported on read cycle ...

Page 596: ...gnal Xm0CSn 5 0 muxed ADDR 22 0 Output SROM Address bus Xm0ADDR 22 0 muxed nOE Output SROM Output Enable Xm0OEn muxed nWE Output SROM Write Enable Xm0WEn muxed nWBE nBE 1 0 Output SROM Byte write Enable Byte Enable Xm0BEn muxed DATA 15 0 In Out SROM Data bus Xm0DATA 15 0 muxed nWAIT Input SROM Wait input Xm0WAITn muxed ...

Page 597: ...he SROM Bank0 control register 0x000F_0000 SROM_BC1 0xE800_0008 R W Specifies the SROM Bank1 control register 0x000F_0000 SROM_BC2 0xE800_000C R W Specifies the SROM Bank2 control register 0x000F_0000 SROM_BC3 0xE800_0010 R W Specifies the SROM Bank3 control register 0x000F_0000 SROM_BC4 0xE800_0014 R W Specifies the SROM Bank4 control register 0x000F_0000 SROM_BC5 0xE800_0018 R W Specifies the SR...

Page 598: ...6 bit 0 ByteEnable4 19 nWBE nBE for UB LB control for Memory Bank4 0 Not using UB LB XrnWBE 1 0 is dedicated nWBE 1 0 1 Using UB LB XrnWBE 1 0 is dedicated nBE 1 0 0 WaitEnable4 18 Wait enable control for Memory Bank4 0 Disables WAIT 1 Enables WAIT 0 AddrMode4 17 Select SROM ADDR Base for Memory Bank4 0 SROM_ADDR is Half word base address SROM_ADDR 22 0 HADDR 23 1 1 SROM_ADDR is byte base address ...

Page 599: ... is 0 SROM_ADDR is byte base address Ignored this bit 0 DataWidth2 8 Data bus width control for Memory Bank2 0 8 bit 1 16 bit 0 ByteEnable1 7 nWBE nBE for UB LB control for Memory Bank1 0 Not using UB LB XrnWBE 1 0 is dedicated nWBE 1 0 1 Using UB LB XrnWBE 1 0 is dedicated nBE 1 0 0 WaitEnable1 6 Wait enable control for Memory Bank1 0 Disables WAIT 1 Enables WAIT 0 AddrMode1 5 Select SROM ADDR Ba...

Page 600: ...e for Memory Bank0 0 SROM_ADDR is Half word base address SROM_ADDR 22 0 HADDR 23 1 1 SROM_ADDR is byte base address SROM_ADDR 22 0 HADDR 22 0 Note When DataWidth0 is 0 SROM_ADDR is byte base address Ignored this bit 0 DataWidth0 0 Data bus width control for Memory Bank0 1 16 bit Note Only 16bit for bank0 can t change 1 ...

Page 601: ...Adress set up before nGCS 0000 0 clock 0001 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks Note More 1 2 cycles according to bus i f status 0000 Tcos 27 24 Chip selection set up before nOE 0000 0 clock 0001 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks 0000 Reserved 23 21 Reserved 000 Tacc 20 16 Ac...

Page 602: ...g time after nGCSn 0000 0 clock 0001 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks Note More 1 2 cycles according to bus i f status 0000 Tacp 7 4 Page mode access cycle Page mode 0000 0 clock 0001 1 clocks 0010 2 clocks 0011 3 clocks 1100 12 clocks 1101 13 clocks 1110 14 clocks 1111 15 clocks 0000 Reserved 3 2 Reserved PMC 1 0 Page mode configurat...

Page 603: ...nchronous FIFOs for matching speed between OneNAND flash memory and AHB system bus interface Supports both asynchronous and synchronous read write of the OneNAND flash memory device Programmable burst transfer size of the OneNAND flash memory interface 4 8 16 32 1024 and continuous Supports 16 bit data path to memory and 32 bit data path to the AHB system bus interface Supports multiple memory dev...

Page 604: ...neNAND controller is designed with the following expectations Supported transfer types are SINGLE INCR4 INCR8 INCR16 transactions Supported transfer sizes are WORD HALFWORD transactions for the OneNAND slave Supported transfer sizes are WORD transactions for the register slave ...

Page 605: ...sting the processing power of ARM processor These additional hardware resources can be utilized to maximize the performance and minimize the usage of ARM processor for OneNAND read write copy operation 3 4 1 BLOCK DIAGRAM OF ONEENAND CONTROLLER Figure 3 1 shows the block diagram of OneNAND controller that comprises one AHB slave port A one AHB master port B and one OneNAND interface port C Figure ...

Page 606: ...nsure there are no memory transfers 2 Switch the clock ratio in the SFR of system controller 3 Write to the clock ratio register 4 Start the memory accesses 3 4 3 INITIALIZATION PROTOCOL 3 4 3 1 Power On After power on the S5PC110 and OneNAND controller are initialized Thereafter OneNAND controller will automatically configure itself to work with the OneNAND flash memory devices This automatic con...

Page 607: ...devices Figure 3 2 shows the data path when OneNAND device is accessed by the external AHB master like ARM processor If AHB address offset from the base address belongs to the bottom 2MB address space this AHB transaction goes to the OneNAND interface to access the OneNAND device Each OneNAND device has its own 128KB address space and this 128KB address space is used to address the BootRAM DataRAM...

Page 608: ...ture use 0xB0080000 0xB009FFFF 128KB Reserved for future use 0xB00A0000 0xB00BFFFF 128KB Reserved for future use 0xB00C0000 0xB00DFFFF 128KB Reserved for future use 0xB00E0000 0xB00FFFFF 128KB Reserved for future use 0xB0100000 0xB011FFFF 128KB Reserved for future use 0xB0120000 0xB013FFFF 128KB Reserved for future use 0xB0140000 0xB015FFFF 128KB Reserved for future use 0xB0160000 0xB017FFFF 128KB...

Page 609: ...12B 4KB DataRAM Main page1 sector3 Main area 64KBytes 0xB0001400 0xB000FFFE 59K 59K Reserved 0xB0010000 0xB001000E 16B BootRAM Spare sector0 0xB0010010 0xB001001E 16B 32B BootRAM Spare sector1 0xB0010020 0xB001002E 16B DataRAM Spare page0 sector0 0xB0010030 0xB001003E 16B DataRAM Spare page0 sector1 0xB0010040 0xB001004E 16B DataRAM Spare page0 sector2 0xB0010050 0xB001005E 16B DataRAM Spare page0...

Page 610: ...512B 4KB DataRAM Main n th page sector7 Main area 64KBytes 0xB0001400 0xB000FFFE 59K 59K Reserved 0xB0010000 0xB001000E 16B BootRAM Spare sector0 0xB0010010 0xB001001E 16B 32B BootRAM Spare sector1 0xB0010020 0xB001002E 16B DataRAM Spare n th page sector0 0xB0010030 0xB001003E 16B DataRAM Spare n th page sector1 0xB0010040 0xB001004E 16B DataRAM Spare n th page sector2 0xB0010050 0xB001005E 16B Da...

Page 611: ...S5PC110_UM 3 ONENAND CONTROLLER 3 9 Figure 3 2 OneNAND Accesses OneNAND Controller Address 0xB0000000 0xB01FFFFF by the External AHB Master ARM Processor ...

Page 612: ...S5PC110_UM 3 ONENAND CONTROLLER 3 10 Figure 3 3 Control Register Accesses OneNAND Controller Address 0xB0600000 0xB07FFFFF by the External AHB Master ARM Processor ...

Page 613: ... system bus The clock frequency relationship between OneNAND device and AHB system bus is fully asynchronous The OneNAND device supports only 16 bit data bus width On the other hand the OneNAND controller supports 32 bit AHB data bus width While reading data from OneNAND device and writing that data to FIFO the OneNAND interface automatically resolves the data bus width mismatch This interface als...

Page 614: ...ration sequence to change the OneNAND Interface Control ONENAND_IF_CTRL register value To update this register the system software must follow the specific sequence illustrated in Figure 3 4 Note that the OneNAND Read Write Busy ORWB bit must be checked to confirm that there is no bus transaction in progress on the OneNAND interface before write new configuration to the OneNAND Interface Control O...

Page 615: ...Read One Dummy Halfword froman OneNAND Device OneNAND Interface is Ready to Accept the AHB Read Wite Requst to Access the OneNAND Device ONENAND_IF_CTRL Register Update Complete NOTE Figure 3 4 ONENAND_IF_CTRL OneNAND Interface Control Register Update Flow NOTE This dummy halfword read is necessary to confirm that new configuration value is written to the OneNAND device before updating the ONENAND...

Page 616: ...S5PC110_UM 3 ONENAND CONTROLLER 3 14 Figure 3 5 ONENAND_IF_ASYNC_TIMING_CTRL OneNAND Interface Async Timing Control Register Update Flow ...

Page 617: ... of the OneNAND Interface Status ONENAND_IF_STATUS register is set to 1 T4 OSINTD x OneNAND Status INT Done bit of the Interrupt Controller OneNAND Status INTC_ONENAND_STATUS register is set to 1 because OMINTD x OneNAND Mask INT Done bit of the Interrupt Controller OneNAND Mask INTC_ONENAND_MASK is deasserted to 0 Simultaneously ARM_IRQ pin is asserted to high to generate an interrupt to the syst...

Page 618: ...0_UM 3 ONENAND CONTROLLER 3 16 Figure 3 6 OneNAND Device INT Pin Rising Edge Wait Operations with a Polling Method Figure 3 7 OneNAND Device INT Pin Rising Edge Wait Operations with an Interrupt Driven Method ...

Page 619: ...S5PC110_UM 3 ONENAND CONTROLLER 3 17 Figure 3 8 OneNAND Device INT Pin Rising Edge Wait Operation Timing Diagram DMA Engin ...

Page 620: ...s OneNAND or control registers on the internal AHB The other port can access SDRAM on the external AHB AHB backbone as shown in Figure 3 9 Each port has 32 entry synchronous FIFOs as data buffer through which two AHB masters of the DMA engine transfer data This helps to improve the performance of data transfer because two AHB master ports of DMA engine access the source and destination memories at...

Page 621: ... to notify the system software that the DMA operation is completed There are two methods with which the system software waits for the completion of the DMA operation and determines the DMA engine s completion status DMA operation with a polling method DMA operation with an interrupt driven method 3 6 5 1 DMA Operation With a Polling Method The system software polls DMA_TRANS_STATUS register to che...

Page 622: ...essor Jumps to the ISR Interrupt Service Routine Read INTC_DMA_STATUS Write 1 to DCTD bit of INTC_DMA_CLR Write 1 to DCTE bit of INTC_DMA_CLR System ISR Start DMA Complete with Errors NO Process Interrupt Events Other Than DMA System ISR Complete System ISR Complete System ISR Complete DMA Complete Read INTC_DMA_MASK DMA Start Write to DMA_SRC_ADDR Write to DMA_SRC_CFG Write to DMA_DST_ADDR Write ...

Page 623: ... Active LOW Xm0CSn 5 4 muxed nWE O Write Enable indicates that the current bus cycle is a write cycle Active LOW Xm0WEn muxed nOE O Output Enable indicates that the current bus cycle is a read cycle Active LOW Xm0OEn muxed INT 1 0 I Interrupt inputs from OneNAND memory Bank 0 1 If OneNAND memory is not used these signals should be tied to zero Xm0FRnB 5 4 muxed nAVD O Address valid output In the P...

Page 624: ...040002 DMA_TRANS_SIZE 0xB060_0414 R W DMA Transfer Size Register 0x00000000 DMA_TRANS_CMD 0xB060_0418 W DMA Transfer Command Register 0x00000000 DMA_TRANS_STATUS 0xB060_041C R DMA Transfer Status Register 0x00000000 DMA_TRANS_DIR 0xB060_0420 R W DMA Transfer Direction Register 0x00000000 INTC_DMA_CLR 0xB060_1004 W Interrupt Controller DMA Clear Register 0x00000000 INTC_ONENAND_CLR 0xB060_1008 W In...

Page 625: ...d to enable or disable the read prefetch operation of the OneNAND interface 0b Read Prefetch Disable 1b Read Prefetch Enable OneNAND Interface has its own read prefetch FIFO This FIFO is implemented as an asynchronous FIFO of 32 bit x 32 depth between AHB and OneNAND clock domains If the sequential read access is dominant prefetch next read data in advance to increase the OneNAND read bandwidth If...

Page 626: ...st length among 4 burst 8 burst 16 burst 32 burst 1024 burst and continuous burst Note that BL burst length bits are valid only for the synchronous read write operation 000b Continuous Burst 001b 4 Burst 010b 8 Burst 011b 16 Burst 100b 32 Burst 101b 1024 Burst 110b Reserved 111b Reserved 000b 8 3 Reserved HF 2 High Frequency This bit is used to enable or disable the high frequency mode High freque...

Page 627: ...rface Synchronous Read Timing CLK 2x Internal CLK nCE nOE nWE ADDR DQ RDY nAVD BRWL Clocks 1 Clock 1 Clock Valid A ddress 3 Clocks 1 st W rite Data 2 nd Write Data 3 rd W rite Data BL th W rite Data BL Clocks Figure 3 13 OneNAND Interface Synchronous Write Timing ...

Page 628: ... Done clear 0b no operation INTC 1 1b Device 1 OneNAND Interrupt Done clear 0b no operation 00h 15 2 Reserved WR 1 Warm Reset For OneNAND warm reset writing 1 to this bit makes nRP pin of OneNAND device low during 20 CLK It is mandatory to assert the nRP pin to zero for warm reset during tRP time and the tRP time is more than 200ns After warm reset it should wait for tREADY1 to access the OneNAND ...

Page 629: ...010b 2 CLK 1111b 15 CLK 3h WLL 11 8 nWE Low Length nWE signal is held to low for WLL clock time at OneNAND asynchronous read write execution 0000b Reserved Do NOT Use 0001b 1 CLK 0010b 2 CLK 1111b 15 CLK 4h OHL 7 4 nOE High Length nOE signal is held to high for OHL clock time at OneNAND asynchronous read write execution 0000b Reserved Do NOT Use 0001b 1 CLK 0010b 2 CLK 1111b 15 CLK 1h OLL 3 0 nOE ...

Page 630: ...Low Length 2 Clocks nOE High Length Clocks 1 Clock 1 Clock 1 Clock CLK 2x I nternal Figure 3 14 OneNAND Interface Asynchronous Read Timing CLK nCE nOE nWE ADDR RDY nAVD V alid Address DQ Valid Write Data 1 Clock 1 Clock 1 Clock nWE Low Length Clocks nWE High Length Clocks CLK 2x I nternal Figure 3 15 OneNAND Interface Asynchronous Write Timing ...

Page 631: ...when OneNAND INT pin s rising edge is detected and is cleared to 0 when INTC OneNAND INT Done Clear bit of OneNAND Interface Command Register ONENAND_IF_CMD is set to 1 INTD 0 1b Device 0 OneNAND Interrupt Done 0b No operation INTD 1 1b Device 1 OneNAND Interrupt Done 0b No operation 11b 15 1 Reserved ORWB 0 OneNAND Read Write Busy This status is used to check whether the OneNAND interface is busy...

Page 632: ...ST burst length to initiate the burst transfer on the AHB during the DMA transfer If this address alignment condition is not satisfied the actual burst length on the AHB will be single until this condition is met 000b Single 001b Reserved 010b 4 Burst 011b 8 Burst 100b 16 Burst 101b Reserved 110b Reserved 111b Reserved 100b 15 9 Reserved SAM 8 Source Addressing Mode This bit refers to addressing m...

Page 633: ...he DMA transfer will be smaller than the access size specified in these bits 00b 8 bit byte 01b 16 bit half word 10b 32 bit word 11b Reserved 3 8 3 3 DMA Destination Address Register DMA_DST_ADDR R W Address 0xB060_0408 DMA_DST_ADDR Bit Description Initial State DA 31 0 Destination Address Destination address on the AHB for the DMA operation This address is the start address to which the DMA engin...

Page 634: ... 110b Reserved 111b Reserved 100b 15 9 Reserved DAM 8 Destination Addressing Mode It specifies Addressing mode during the destination memory access on the AHB for the DMA operation The incremental addressing mode is used for the general DMA operation and the constant mode is used to access repeatedly the specific address like a data register 0b Incremental addressing mode 1b Constant addressing mo...

Page 635: ...rt BYTE transactions 000000h 3 8 3 6 DMA Transfer Command Register DMA_TRANS_CMD W Address 0xB060_0418 DMA_TRANS_ CMD Bit Description Initial State 31 19 Reserved TDC 18 Transfer Done Clear When this bit is set to 1 the TD Transfer Done bit flag of the DMA Transfer Status Register DMA_TRANS_STATUS in the DMA engine is cleared to 0 0b 17 Reserved TEC 16 Transfer Error Clear When this bit is set to ...

Page 636: ... AHB master ports and these are connected to the external AHB and the internal AHB respectively Therefore source and destination address registers cannot be configured to the slaves on the same AHB for the DMA operation Due to this fact only following two cases are allowed for source destination address register value 1 source memory is the slave on the external AHB and destination memory is the s...

Page 637: ... State 31 1 Reserved TDIR 0 Transfer Direction This bit specifies the transfer direction of the DMA operation between the OneNAND controller s internal AHB memory and the OneNAND controller s external AHB memory 0b OneNAND controller read Internal AHB memory to external AHB memory 1b OneNAND controller write External AHB memory to internal AHB memory 0b ...

Page 638: ...egister INTC_DMA_MASK is 0 the DSTD DMA Status Transfer Done bit of the Interrupt Controller DMA Status Register INTC_DMA_STATUS is set to 1 because this interrupt source is not masked Now the ARM_IRQ pin of the OneNAND controller is asserted to 1 and an interrupt is generated by the OneNAND controller Note that the ARM_IRQ pin is OR ed value of all the bits of interrupt controller status register...

Page 639: ...fer done bit flag of the Interrupt Controller DMA Status Register INTC_DMA_STATUS in the interrupt controller is disabled to generate an interrupt 1b 13 17 Reserved DMTE 16 DMA Mask Transfer Error When this bit is set to 1 the DPTE DMA status transfer error bit flag of the Interrupt Controller DMA Status Register INTC_DMA_STATUS in the interrupt controller is disabled to generate an interrupt 1b 1...

Page 640: ...ne This bits are the exact copy of the INTD INT done bit flag of the OneNAND Interface Status Register ONENAND_IF_STATUS 11b 3 8 4 7 Interrupt Controller DMA Status Register INTC_DMA_STATUS R Address 0xB060_1064 INTC_DMA_ STATUS Bit Description Initial State 31 25 Reserved DSTD 24 DMA Status Transfer Done This bit is logical AND operation result of DPTD DMA pending transfer done bit flag of the in...

Page 641: ...Description Initial State 31 2 Reserved OSINTD 1 0 OneNAND Status INT Done This bits are logical AND operation result of OPINTD OneNAND pending INT done bit flags of the interrupt controller OneNAND pending register INTC_ONENAND_PEND and inverse of OMINTD OneNAND mask INT done bit flag of the Interrupt Controller OneNAND Mask Register INTC_ONENAND_MASK 00b ...

Page 642: ...r the NAND flash content is copied to DRAM main program will be executed on DRAM 4 2 KEY FEATURES OF NAND FLASH CONTROLLER The key features of NAND flash controller include NAND flash memory interface Supports 512Bytes 2KB 4KB and 8KB pages Software mode You can directly access NAND flash memory for example this feature can be used in read erase program NAND flash memory Interface Supports 8 bit N...

Page 643: ...Interface CLE ALE nFCE nRE nWE R nB I O0 I O7 AHB Slave I F Control State Machine SYSTEM BUS Figure 4 1 NAND Flash Controller Block Diagram 4 2 2 NAND FLASH MEMORY TIMING HCLK CLE ALE nWE TACLS TWRPH0 TWRPH1 DATA COMMAND ADDRESS Figure 4 2 CLE and ALE Timing TACLS 1 TWRPH0 0 TWRPH1 0 ...

Page 644: ...S5PC110_UM 4 NAND FLASH CONTROLLER 4 3 HCLK nWE nRE DATA DATA TWRPH0 TWRPH1 Figure 4 3 nWE and nRE Timing TWRPH0 0 TWRPH1 0 ...

Page 645: ...ifies read data from the NAND Flash Memory read cycle Reading main ECC registers NFMECCD0 NFMECCD1 and Spare ECC registers NFSECCD specify read data from the NAND Flash Memory NOTE In the software mode use polling or interrupt to check the RnB status input pin 4 3 1 DATA REGISTER CONFIGURATION 4 3 1 1 8 bit NAND Flash Memory Interface A Word Access Register Endian Bit 31 24 Bit 23 16 Bit 15 8 Bit ...

Page 646: ...ength of main data is 512 bytes and the length of spare meta data depends on user application Since these ECC modules support variable length of main and spare meta data you must set the ECC parity conversion codes to handle free page For more information on ECC parity conversion codes refer to the 4 3 11 Free page specifies an erased page The value of erased page is 0xff Therefore set the ECC par...

Page 647: ...CCLock and SpareECCLock bit of the control register generates the 1 bit ECC If ECCLock is low the hardware ECC modules generate the ECC codes 1 bit ECC Register Configuration The following table shows the configuration of 1 bit ECC value read from spare area of external NAND flash memory The format of ECC read from memory is important to compare the ECC parity code generated by the hardware module...

Page 648: ...ue of the ECC status register does not change 4 To generate spare area ECC parity code Clear SpareECCLock NFCONT 6 bit as 0 Unlock 5 The spare area ECC module generates ECC parity code on register NFSECC whenever data is read or written 6 After you complete reading or writing spare area set the SpareECCLock bit to 1 Lock ECC Parity code is locked and the value of the ECC status register will not b...

Page 649: ...more than 512 byte page you cannot program immediately In this case you have to copy these parity codes to other memory like DRAM After writing all main data you can write the copied ECC values to spare area The parity codes have self correctable information including parity code itself 4 To generate spare area ECC parity code set the MsgLength to 1 24 byte message length and the ECCType to 10 ena...

Page 650: ...es whether error bit exists or not If any error exists refer NFECCERR0 1 and NFMLCBITPT registers to fix 5 If you have more main data to read go back to step 1 6 To check meta data error set the MsgLength to 1 24 byte message length and the ECCType to 1 enable 4 bit ECC ECC module generates ECC parity code for 512 byte read data Therefore you must reset ECC value by writing the InitMECC NFCONT 5 b...

Page 651: ...se a NAND Flash memory having 512 byte page you can program these values to spare area However if you use a NAND Flash memory more than 512 byte page you cannot program immediately In this case you must copy these ECC parity codes to other memory like DRAM After writing all main data you can write the copied ECC values to spare area The parity codes have self correctable information including pari...

Page 652: ...whether error bits have occurred or not Therefore you have to read ECC parity code immediately after reading 512 byte After ECC parity code is read the 8 12 16 bit ECC engine searches for error internally 8 12 16 bit ECC search engine needs minimum of 155 cycles to find any errors DecodeDone NFECCSTAT 24 can be used to check whether ECC decoding is completed or not 4 When DecodeDone NFECCSTAT 24 i...

Page 653: ...ange ECC parity conversion codes Steps to know ECC parity conversion codes according to the size of message length 1 Clear all ECC parity conversion registers NFECCCONECC0 NFECCCONECC6 as all zero 2 Set all registers for page program 3 Reset InitMECC NFECCCONT 2 bit as 1 4 Write 0xff data as much as the size of meta data 5 After you write data as MsgLength NFECCCONF 25 16 the EncodeDone NFECCSTAT ...

Page 654: ...ed area an illegal access error will occur NFSTAT 5 bit will be set 3 Lock tight mode In lock tight mode you can access NAND block area between NFSBLK and NFEBLK as soft lock mode The differences is that you cannot change NFSBLK and NFEBLK registers and also LOCK NFCONT 16 and LockTight NFCONT 17 bits When you try to program or erase the locked area an illegal access error will occur NFSTAT 5 bit ...

Page 655: ...utput Address Data Bus Xm0DATA muxed Xm0FRnB 3 0 Input Ready and Busy Xm0FRnB muxed Xm0FCLE Output Command Latch Enable Xm0FCLE muxed Xm0FALE Output Address Latch Enable Xm0FALE muxed Xm0CSn 2 5 Output Chip Enable Xm0CSn muxed Xm0FREn Output Read Enable Xm0FREn muxed Xm0FWEn Output Write Enable Xm0FWEn muxed ...

Page 656: ...tatus1 Register 0xFFFF_FFFF NFSECC 0xB0E0_003C R Generated Spare Area ECC Status Register 0xFFFF_FFFF NFMLCBITPT 0xB0E0_0040 R 4 bit ECC Error Bit Pattern Register 0x0000_0000 8 12 16 bit ECC Register Map NFECCCONF 0xB0E2_0000 R W ECC Configuration Register 0x0000_0000 NFECCCONT 0xB0E2_0020 R W ECC Control Register 0x0000_0000 NFECCSTAT 0xB0E2_0030 R ECC Status Register 0x0000_0000 NFECCSECSTAT 0x...

Page 657: ...R ECC error bit pattern1 register 0x0000_0000 NFECCERP2 0xB0E2_00F8 R ECC error bit pattern2 register 0x0000_0000 NFECCERP3 0xB0E2_00FC R ECC error bit pattern3 register 0x0000_0000 NFECCCONECC0 0xB0E2_0110 R W ECC parity conversion code0 register 0x0000_0000 NFECCCONECC1 0xB0E2_0114 R W ECC parity conversion code1 register 0x0000_0000 NFECCCONECC2 0xB0E2_0118 R W ECC parity conversion code2 regis...

Page 658: ... x TWRPH0 1 Note You should add additional cycles about 10ns for page read because of additional signal delay on PCB pattern 0x0 TWRPH1 7 4 TWRPH1 duration setting value 0 15 Duration HCLK x TWRPH1 1 0x0 MLCFlash 3 This bit indicates the kind of NAND Flash memory to use 0 SLC NAND Flash 1 MLC NAND Flash 0 PageSize 2 This bit indicates the page size of NAND Flash Memory When MLCFlash is 0 the value...

Page 659: ...r this bit For more information refer to the 4 3 12 Lock scheme for data protection 0 LOCK 16 Soft Lock configuration 0 Disable lock 1 Enable lock Software can modify soft lock area any time For more information refer to the 4 3 12 1 Reserved 15 14 Reserved 00 EnbMLCEncInt 13 4 bit ECC encoding completion interrupt control 0 Disable interrupt 1 Enable interrupt 0 EnbMLCDecInt 12 4 bit ECC decoding...

Page 660: ...l 1 Reg_nCE0 1 NAND Flash Memory nRCS 0 signal control 0 Force nRCS 0 to low Enable chip select 1 Force nRCS 0 to High Disable chip select Note The setting all nCE 3 0 zero can not be allowed Only one nCE can be asserted to enable external NAND flash memory The lower bit has more priority when user set all nCE 3 0 zeros 1 MODE 0 NAND Flash controller operating mode 0 Disable NAND Flash Controller ...

Page 661: ... memory 0x00 Reserved 15 8 Reserved 0x00 ECCData0 ECC0 7 0 1st ECC Note In software mode read this register when you need to read 1st ECC value from NAND flash memory This register has the same read function as NFDATA 0x00 NOTE Only word access is allowed 4 5 2 7 Main Data Area ECC Register NFMECCD0 R W Address 0xB0E0_0018 NFMECCD1 Bit Description Initial State Reserved 31 24 Reserved 0x00 ECCData...

Page 662: ... 3rd block address of the block erase operation 0x00 SBLK_ADDR1 15 8 The 2nd block address of the block erase operation 0x00 SBLK_ADDR0 7 0 The 1st block address of the block erase operation Only bit 7 5 are valid 0x00 NOTE Advance Flash s block Address start from 3 address cycle So block address register only needs 3 bytes For more information about lock scheme refer to the 4 3 12 4 5 2 10 Progra...

Page 663: ...bit ECC encoding is completed 0 MLCDecodeDone 6 When 4 bit ECC decoding is finished this bit is set and an interrupt is issued if MLCDecodeDone is enabled The NFMLCBITPT NFMLCL0 and NFMLCEL1 have valid values To clear this write 1 1 4 bit ECC decoding is completed 0 IllegalAccess 5 Once Soft Lock or Lock tight is enabled and any illegal access program erase to the memory takes place then this bit ...

Page 664: ...ta area bit fail error occurred 00 No Error 01 1 bit error correctable 10 Multiple error 11 ECC area error 10 NOTE The above values are valid only when both ECC register and ECC status register have valid value When ECC Type is 4 bit ECC NFECCERR0 Bit Description Initial State MLCECCBusy 31 Indicates the 4 bit ECC decoding engine is searching whether a error exists or not 0 Idle 1 Busy 0 MLCECCRea...

Page 665: ... Initial State MECC3 31 24 ECC3 for data 0xFF MECC2 23 16 ECC2 for data 0xFF MECC1 15 8 ECC1 for data 0xFF MECC0 7 0 ECC0 for data 0xFF NOTE The NAND flash controller generate NFMECC0 1 when read or write main area data while the MainECCLock NFCONT 7 bit is 0 Unlock When ECCType is 4 bit ECC NFMECC0 Bit Description Initial State 4th Parity 31 24 4th Check Parity generated from main area 512 byte 0...

Page 666: ... the MainECCLock NFCON 7 bit is 0 unlock 4 5 2 16 Spare Area ECC Status Register NFSECC R Address 0xB0E0_003C NFSECC Bit Description Initial State Reserved 31 16 Reserved 0xFFFF SECC1 15 8 Spare area ECC1 Status 0xFF SECC0 7 0 Spare area ECC0 Status 0xFF NOTE The NAND flash controller generate NFSECC when read or write spare area data while the SpareECCLock NFCONT 6 bit is 0 Unlock 4 5 2 17 MLC 4 ...

Page 667: ...00 12 bit ECC 101 16 bit ECC 512B 110 Reserved 111 Reserved 0x0 4 5 3 2 Nand Flash ECC Control Register NFECCCONT R W Address 0xB0E2_0020 NFECCCONT Bit Description Initial State Reserved 31 26 Reserved 0x00 EnbMLCEncInt 25 MLC ECC encoding completion interrupt control 0 Disable interrupt 1 Enable interrupt 0 EnbMLCDecInt 24 MLC ECC decoding completion interrupt control 0 Disable interrupt 1 Enable...

Page 668: ...one is enabled The NFMLCBITPT NFMLCL0 and NFMLCEL1 have valid values To clear this write 1 1 MLC ECC decoding is completed 0 Reserved 23 9 Reserved 0x0000 FreePageStat 8 It indicates whether the sector is free page or not 0 Reserved 7 0 Reserved 0x00 4 5 3 4 Nand Flash ECC Sector Status Register NFECCSECSTAT R Address 0xB0E2_0040 NFECCSECSTAT Bit Description Initial State ValdErrorStat 31 8 Each b...

Page 669: ...ain area 0x00 NFECCPRGECC3 Bit Description Initial State 16th Parity 31 24 16th Check Parity generated from main area 0x00 15th Parity 23 16 15th Check Parity generated from main area 0x00 14th Parity 15 8 14th Check Parity generated from main area 0x00 13th Parity 7 0 13th Check Parity generated from main area 0x00 NFECCPRGECC4 Bit Description Initial State 20th Parity 31 24 20th Check Parity gen...

Page 670: ...byte location of 5th bit error 0x000 NFECCERL3 Bit Description Initial State Reserved 31 26 Reserved 0x0 ErrByteLoc8 25 16 Error byte location of 8th bit error 0x000 Reserved 15 10 Reserved 0x0 ErrByteLoc7 9 0 Error byte location of 7th bit error 0x000 NFECCERL4 Bit Description Initial State Reserved 31 26 Reserved 0x0 ErrByteLoc10 25 16 Error byte location of 10th bit error 0x000 Reserved 15 10 R...

Page 671: ...00 NFECCERP1 Bit Description Initial State 8th ErrBitPattern 31 24 8th Error bit pattern 0x00 7th ErrBitPattern 23 16 7th Error bit pattern 0x00 6th ErrBitPattern 15 8 6th Error bit pattern 0x00 5th ErrBitPattern 7 0 5th Error bit pattern 0x00 NFECCERP2 Bit Description Initial State 12th ErrBitPattern 31 24 12th Error bit pattern 0x00 11th ErrBitPattern 23 16 11th Error bit pattern 0x00 10th ErrBi...

Page 672: ...version code 0x00 NFECCCONECC3 Bit Description Initial State 16th Conversion Code 31 24 16th ECC Parity conversion code 0x00 15th Conversion Code 23 16 15th ECC Parity conversion code 0x00 14th Conversion Code 15 8 14th ECC Parity conversion code 0x00 13th Conversion Code 7 0 13th ECC Parity conversion code 0x00 NFECCCONECC4 Bit Description Initial State 20th Conversion Code 31 24 20th ECC Parity ...

Page 673: ...d requests to the CFC block requester interface The Slave interface responds to the requests initiated To complete the AHB Bus transaction the CFC drives the appropriate AHB response onto the AHB Bus The CFC can control the Hard Disk and the Compact Flash that can operate in true IDE mode 5 2 KEY FEATURES OF COMPACT FLASH CONTROLLER The key features of CFC are as follows Supports all ATA PIO from ...

Page 674: ...ntroller has 32 word sized 32 bits Special Function Registers The ATAPI controller directly accesses the system RAM when it implements MDMA and UDMA data transfer Therefore there are three operating modes called PIO MDMA and UDMA in the ATA controller The signal timing depends on the transfer class and its modes The ATA host controller supports several classes PIO MDMA and UDMA They have various m...

Page 675: ...fer protocol supports 8 bit register access in driver and 16 bit PIO data access If PIO mode 3 or 4 is the currently selected mode of operation both hosts and devices support ATA_IORDY The Figure 5 2 defines the relationships between host and device interface signals for data and registers transfer ...

Page 676: ...ler is in the ATA_TRANS state The figure indicates various timing parameters Timing t1 indicates the time between address valid and IORD IOWR asserted Timing t2 indicates the time for which IORD IOWR is asserted The ATA state transfer in PDMA class follows similar timing t 2 t 1 teoc t1 CS 0 CS 1 DA 2 0 DIOR DIOW WR DD 15 0 or DD 7 0 RD DD 15 0 or DD 7 0 Figure 5 2 PIO Mode Waveform ...

Page 677: ...ATA_PIO_TIME REGISTER SETTING EXAMPLE IN CASE OF DATA TRANSFER The t1 minimum time is 70ns in the system clock of 100MHz 10ns It gives 7 t1 divided by 10ns This case has no residual therefore pio_t1 3 0 assigns 6 which is 7 minus 1 If it has residual assign the quotient at pio_t1 3 0 ATA_PIO_TIME Tpara PIO mode Minimum Maximum system clock 1 tPIO0 Timing Parameter of PIO Mode 0 in case of Register...

Page 678: ...S5PC110_UM 5 COMPACT FLASH CONTROLLER 5 6 5 6 FLOWCHART FOR PIO READ WRITE Figure 5 3 Flowchart for Read Write in PIO Class ...

Page 679: ...timing parameters The ATA_CS0n and CS1n are inactive during MDMA transfer The ATA Host controller is always the master in the MDMA transfer classes The MDMA has three transfer modes Mode 0 2 The fastest mode is mode 2 The Figure 5 4 defines the relationships between host and device interface signals for data transfer The Table 5 2 describes the timing parameters of MDMA read and write transfer Fig...

Page 680: ...I MDMA transfer protocol To write and read transfer Steps to Write Protocol 1 Wait for the driver to activate ATA_DMARQ 2 Activate ATA_DMACKn deactivate ATA_CS0n CS1n and set time to 0 3 Activate ATA_DIOWn at time tM 4 Drive 16 bit data on the lines at time tD 5 Deactivate ATA_DIOWn after tD 6 If ATA_DMARQ is still active repeat step 3 to 6 for another word and deactivate ATA_DMACKn at time tM Ste...

Page 681: ...The following figures Figure 5 5 Figure 5 6 Figure 5 7 and Figure 5 8 defines the relationships between host and device interface signals for UDMA data transfer The timing parameters involved is tACKENV tRP tSS tDVS and tDVH tACKENV indicates the setup and hold times of DMACK Before assertion or negation and envelope time From DMACKn to STOP and HDMARDYn tRP indicates Ready to pause time tSS indic...

Page 682: ...7 0 DMACK DMARQ DIOW DIOR IORDY tRP tACKENV tACKENV tDVS tDVH Figure 5 6 UDMA In Operation Terminated by Host CS0 CS1 DA 2 0 DD 15 0 or DD 7 0 DMACK DMARQ DIOW DIOR IORDY tACKENV tACKENV tACKENV tSS tDVS tDVH tACKENV tDVS tDVH Figure 5 7 UDMA Out Operation Terminated by Device ...

Page 683: ...MA Out Operation Terminated by Host Table 5 3 Timing Parameter Each UDMA Mode UDMA mode UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4 tACKENV 20 70 20 70 20 70 20 55 20 55 tSS 50 50 50 50 50 tRP 160 125 100 100 100 tDVS 70 48 31 20 6 7 tDVH 6 2 50 6 2 32 6 2 29 6 2 25 6 2 23 3 tDVS tDVH 120 80 60 45 30 NOTE unit ns 50 is tDVS tDVH tDVS 120 70 50 ...

Page 684: ..._trp 15 8 0x0f tdvs 70 10 7 udma_tdvs value 7 1 6 udma_tdvs 23 16 0x06 tdvh 50 10 5 udma_tdvh value 5 1 4 udma_tdvh 27 24 0x4 tdvh minimum timing is 6 2ns but the timing parameter sets 50ns since the tDVS and tDVH summation is 120ns The Table 5 4 shows True IDE Mode Control Signaling Table 5 4 True IDE Mode I O Decoding nCE2 nCE1 A2 A1 A0 nDMACK nIORD 0 nIOWR 0 Note 1 0 0 0 0 1 PIO RD data PIO WR ...

Page 685: ... state after completing one full cycle of the finite state machine FSM The FSM transition from IDLE state happens if ATA transfer state is in ATA_TRANS The FSM continues the cycle while the abort is asserted The transfer in any class stays in IDLE after detecting ATA state in ATA_ABORT Figure 5 9 Flowchart for Abort in ATA Mode ...

Page 686: ...wr_en O Data Output Enable Strobe IORDY I Data transfer wait signal DMA ready during UDMA write DMA strobe during UDMA read XmsmADDR 3 muxed INTRQ I Device Interrupt signal XmsmADDR 4 muxed DMARQ I The DMA request signal for data transfers between host and device XmsmADDR 5 muxed DRESETn O Device reset signal from host XmsmADDR 6 muxed DMACKn O The DMA acknowledge signal that data has been accepte...

Page 687: ...he ATA UDMA timing 0x080b1a83 ATA_XFR_NUM 0xE820_0034 R W Specifies the ATA transfer number 0x00000000 ATA_XFR_CNT 0xE820_0038 R Specifies the ATA current transfer count 0x00000000 ATA_TBUF_BASE 0xE820_003C R W Specifies the ATA start address of track buffer 0x00000000 ATA_TBUF_SIZE 0xE820_0040 R W Specifies the ATA size of track buffer 0x00000000 ATA_SBUF_BASE 0xE820_0044 R W Specifies the ATA st...

Page 688: ...A PIO device command status register 0x00000000 ATA_PIO_DAD 0xE820_0074 R W Specifies the ATA PIO device control alternate status register 0x00000000 ATA_PIO_READY 0xE820_0078 R Specifies the ATA PIO data read write ready 0x00000003 ATA_PIO_RDATA 0xE820_007C R Specifies the ATA PIO read data from device data register 0x00000000 BUS_FIFO_STATUS 0xE820_0080 R Specifies the ATA internal AHB FIFO stat...

Page 689: ...x1 ata_enable 0 Enables ATA 0 Disables ATA and preparation for clock down 1 Enables ATA R W 0x0 5 11 1 2 ATA Status Register ATA_STATUS R Address 0xE820_0004 ATA_STATUS Bit Description R W Initial State Reserved 31 6 Reserved R 0x0 atadev_cblid 5 ATAPI cable identification R 0x0 atadev_irq 4 ATAPI interrupt signal line R 0x0 atadev_iordy 3 ATAPI iordy signal line R 0x1 atadev_dmareq 2 ATAPI dmareq...

Page 690: ...roller move to idle state 00 Stop command 01 Start command Available in idle state 10 Abort command 11 Continue command Available in transfer pause After CPU ABORT commands make a software reset by ATA_SWRST to clear the leftover values of internal registers R W 0x0 The STOP command controls the ATA Device side signal but does not control DMA side Namely if the FIFO has data after STOP command DMA...

Page 691: ...Q R W Address 0xE820_0010 ATA_IRQ Bit Description R W Initial State Reserved 31 6 Reserved R 0x0 mdma_hold_int 5 If ATAPI device makes pending in MDMA class CPU clears this interrupt by writing 1 R W 0x0 sbuf_empty_int 4 If source buffer is empty CPU clears this interrupt by writing 1 R W 0x0 tbuf_full_int 3 If track buffer is half full CPU clears this interrupt by writing 1 R W 0x0 atadev_irq_int...

Page 692: ...ld_int Enable R W 0x0 mask_sbut_empty_int 4 0 Mask sbut_empty_int Disable 1 Unmask sbuf_empty_int Enable R W 0x0 mask_tbuf_full_int 3 0 Mask tbuf_full_int Disable 1 Unmask tbuf_full_int Enable R W 0x0 mask_atadev_irq_int 2 0 Mask atadev_irq_int Disable 1 Unmask ata_irq_int Enable R W 0x0 mask_udma_hold_int 1 0 Mask udma_hold_int Disable 1 Unmask udma_hold_int Enable R W 0x0 mask_xfr_done_int 0 0 M...

Page 693: ...tion 0 Stay in pause state and wait for CPU s action 1 Continue automatically R W 0x0 Reserved 8 Reserved R 0x0 Reserved 7 Reserved R 0x0 byte_swap 6 Determines whether data endian is little or big in 16 bit data 0 Little endian data 15 8 data 7 0 1 Big endian data 7 0 data 15 8 In case of PIO mode 0 Big endian 1 Little endian R W 0x0 atadev_irq_al 5 Device interrupt signal level 0 Active high 1 A...

Page 694: ...9 12 PIO timing parameter teoc end of cycle time It shall not have zero value R W 0x27 pio_t2 11 4 PIO timing parameter t2 DIOR Wn pulse width It cannot have zero value R W 0x2f pio_t1 3 0 PIO timing parameter t1 address valid to DIOR Wn R W 0xa 5 11 2 7 ATA UDMA Time ATA_UDMA_TIME R W Address 0xE820_0030 ATA_UDMA_TIME Bit Description R W Initial State Reserved 31 28 Reserved R 0x0 udma_tdvh 27 24...

Page 695: ...AHB burst size is 8 R 0x00000000 Reserved 0 Reserved R 0x0 5 11 2 10 Start Address of the Track Buffer ATA_TBUF_BASE R W Address 0xE820_003C ATA_TBUF_BASE Bit Description R W Initial State track_buffer_base 31 2 Start address of track buffer 4 byte unit R W 0x00000000 Reserved 1 0 Reserved R 0x0 5 11 2 11 Size of the Track Buffer ATA_TBUF_SIZE R W Address 0xE820_0040 ATA_TBUF_SIZE Bit Description ...

Page 696: ... ATA_CADDR_SBUF R Address 0xE820_0050 ATA_CADDR_SBUF Bit Description R W Initial State source_buf_cur_adr 31 2 Current address of source buffer R 0x00000000 Reserved 1 0 Reserved R 0x0 5 11 2 16 ATA PIO Data Register ATA_PIO_DTR R W Address 0xE820_0054 ATA_PIO_DTR Bit Description R W Initial State Reserved 31 16 Reserved R 0x0 pio_dev_dtr 15 0 16 bit PIO data register R W 0x0000 5 11 2 17 ATA PIO ...

Page 697: ...tial State Reserved 31 8 Reserved R 0x0 pio_dev_lhr 7 0 8 bit PIO LBA high command block register R W 0x00 5 11 2 22 ATA PIO Device Register ATA_PIO_DVR R W Address 0xE820_006C ATA_PIO_DVR Bit Description R W Initial State Reserved 31 8 Reserved R 0x0 pio_dev_dvr 7 0 8 bit PIO device command block register R W 0x00 5 11 2 23 ATA PIO Device Command Status Register ATA_PIO_CSD R W Address 0xE820_007...

Page 698: ...ATA_PIO_DATA register R 0x1 5 11 2 26 ATA PIO Read Data Register ATA_PIO_RDATA R Address 0xE820_007C ATA_PIO_RDATA Bit Description R W Initial State Reserved 31 16 Reserved R 0x0 pio_rdata 15 0 PIO read data register while HOST read from ATA device register R 0x0000 5 11 2 27 AHB Bus FIFO Status Register BUS_FIFO_STATUS R Address 0xE820_0080 BUS_FIFO_STATUS Bit Description R W Initial State Reserv...

Page 699: ...0 IDLE 2 b01 T1 2 b10 T2 2 b11 TEOC R 0x0 pdma_state 25 24 2 b00 IDLE 2 b01 T1 2 b10 T2 2 b11 TEOC R 0x0 Reserved 23 Reserved R 0x0 dma_state 1 0 22 21 0 IDLE 1 TD 2 TM 3 TEOC R 0x00 udma_state 4 0 20 16 5 b00000 IDLE 5 b00001 TMI 5 b00010 CRCS 5 b00011 CRCH 5 b00100 END 5 b01000 STOPW 5 b01001 ACKW 5 b01010 NSEQWS 5 b01011 NSEQWH 5 b01100 SEQWS 5 b01101 SEQWH 5 b01110 TSSW 5 b10000 STOPR 5 b10001...

Page 700: ...o the memory controller with highest priority The memory controller must complete the current transfer and release the bus To signal these actions EBIBACKOFF is made the output of EBI The EBI arbitration scheme tracks the memory controller that is currently granted and waits for the transaction from the memory controller to finish EBIREQ is set to Low by the memory controller before it grants the ...

Page 701: ...S5PC110_UM 6 EXTERNAL BUS INTERFACE 6 2 6 3 BLOCK DIAGRAM OF MEMORY INTERFACE THROUGH EBI Figure 6 1 Memory Interface Through EBI ...

Page 702: ...CK SCHEME OF MEMORY CONTROLLERS AND EBI Figure 6 2 Clock Scheme of Memory Controllers and EBI NOTE The OneNAND Clock selection register name in Section 2 3 Clock Controller is OneNAND_SEL OneNAND_Async The register address is 0xE010_0200 CLK_SRC0 28 ...

Page 703: ...Section 6 DMA ...

Page 704: ...1 DMA Controller 1 1 1 1 Overview of DMA Controller 1 1 1 1 1 Key Features of DMA Controller 1 2 1 2 Register Description 1 5 1 2 1 Register Map 1 5 1 3 Instruction 1 25 1 3 1 Key Instruction 1 26 1 3 2 USAGE Model 1 28 ...

Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...

Page 706: ...le Page Number Number Table 1 1 DMA Request Mapping Table 1 2 Table 1 2 DMA_mem Register Summary 1 5 Table 1 3 DMA_peri0 Register Summary 1 9 Table 1 4 DMA_peri0 Register Summary 1 13 Table 1 5 Instruction Syntax Summary 1 25 ...

Page 707: ...DMA top consists of PL330 and some logics On the other hand Peri DMA top consists of two PL330s DMA0 and DMA1 and dma_map Figure 1 1 Two DMA Tops All peripherals must be set as non secure at TrustZone Protection Controller TZPC module since DMA_peri operates only as non secure The bus interface of PL330 is AXI so that DMA_mem and DMA_peri are attached to AXI_B0 and AXI_B1 respectively For more inf...

Page 708: ...rrupt sources only one interrupt is sent to Vectored Interrupt Controller VIC for each DMA To see the interrupt number of DMA refer to the interrupt number table in Chapter 04 01 Interrupt Controller The software reads Interrupt Status INTSTATUS register for each module to check whether an interrupt occurs Table 1 1 DMA Request Mapping Table Module No DMA Request Category Service Module 31 PCM2_TX...

Page 709: ...RT0_TX 0 UART0_RX System 31 Reserved 30 Reserved 29 Reserved 28 Reserved 27 SPDIF 26 PWM 25 Reserved Others 24 AC_PCMout 23 AC_PCMin 22 AC_MICin by only DMA0 21 20 19 SPI1_TX 18 SPI1_RX 17 SPI0_TX 16 SPI0_RX 15 Reserved 14 Reserved 13 I2S1_TX 12 I2S1_RX 11 I2S0S_TX 10 I2S0_TX 9 I2S0_RX Audio and SPI 8 Reserved 7 UART3_TX 6 UART3_RX Peri DMA0 5 UART2_TX System ...

Page 710: ...ER 1 4 Module No DMA Request Category Service Module 4 UART2_RX 3 UART1_TX 2 UART1_RX 1 UART0_TX 0 UART0_RX DMA_mem Security by M2M DMA only Caution When PDMA0 or PDMA1 are enabled the CLK_GATE_IP2 8 at SYSCON must be set to 1 ...

Page 711: ...TUS 0xFA20_0028 R Specifies the Interrupt Status Register For more information refer to page 3 16 of PL330 TRM 0x0 INTCLR 0xFA20_002C W Specifies the Interrupt Clear Register For more information refer to page 3 17 of PL330 TRM 0x0 FSM 0xFA20_0030 R Specifies the Fault Status DMA Manager Register For more information refer to page 3 18 of PL330 TRM 0x0 FSC 0xFA20_0034 R Specifies the Fault Status ...

Page 712: ...PC for DMA Channel 3 0x0 CPC4 0xFA20_0124 R Specifies the Channel PC for DMA Channel 4 0x0 CPC5 0xFA20_012C R Specifies the Channel PC for DMA Channel 5 0x0 CPC6 0xFA20_0134 R Specifies the Channel PC for DMA Channel 6 0x0 CPC7 0xFA20_013C R Specifies the Channel PC for DMA Channel 7 0x0 0xFA20_0140 0xFA20_03FC Reserved Source Address Registers For more information refer to page 3 27 of PL330 TRM ...

Page 713: ...egisters For more information refer to page 3 35 of PL330 TRM LC0_0 0xFA20_040C R Specifies the Loop Counter 0 for DMA Channel 0 0x0 LC0_1 0xFA20_042C R Specifies the Loop Counter 0 for DMA Channel 1 0x0 LC0_2 0xFA20_044C R Specifies the Loop Counter 0 for DMA Channel 2 0x0 LC0_3 0xFA20_046C R Specifies the Loop Counter 0 for DMA Channel 3 0x0 LC0_4 0xFA20_048C R Specifies the Loop Counter 0 for D...

Page 714: ...E00 R Specifies the Configuration Register 0 For more information refer to page 3 40 of PL330 TRM 0x003E_1071 CR1 0xFA20_0E04 R Specifies the Configuration Register 1 For more information refer to page 3 42 of PL330 TRM 0x0000_0075 CR2 0xFA20_0E08 R Specifies the Configuration Register 2 For more information refer to page 3 43 of PL330 TRM 0x0 CR3 0xFA20_0E0C R Specifies the Configuration Register...

Page 715: ...034 R Specifies the Fault Status DMA Channel Register For more information refer to page 3 19 of PL330 TRM 0x0 FTM 0xE090_0038 R Specifies the Fault Type DMA Manager Register For more information refer to page 3 20 of PL330 TRM 0x0 Reserved 0xE090_003C Reserved FTC0 0xE090_0040 R Specifies the Fault Type for DMA Channel 0 0x0 FTC1 0xE090_0044 R Specifies the Fault Type for DMA Channel 1 0x0 FTC2 0...

Page 716: ...egisters For more information refer to page 3 27 of PL330 TRM SA_0 0xE090_0400 R Specifies the Source Address for DMA Channel 0 0x0 SA_1 0xE090_0420 R Specifies the Source Address for DMA Channel 1 0x0 SA_2 0xE090_0440 R Specifies the Source Address for DMA Channel 2 0x0 SA_3 0xE090_0460 R Specifies the Source Address for DMA Channel 3 0x0 SA_4 0xE090_0480 R Specifies the Source Address for DMA Ch...

Page 717: ...the Loop Counter 0 for DMA Channel 2 0x0 LC0_3 0xE090_046C R Specifies the Loop Counter 0 for DMA Channel 3 0x0 LC0_4 0xE090_048C R Specifies the Loop Counter 0 for DMA Channel 4 0x0 LC0_5 0xE090_04AC R Specifies the Loop Counter 0 for DMA Channel 5 0x0 LC0_6 0xE090_04CC R Specifies the Loop Counter 0 for DMA Channel 6 0x0 LC0_7 0xE090_04EC R Specifies the Loop Counter 0 for DMA Channel 7 0x0 Loop...

Page 718: ..._F075 CR1 0xE090_0E04 R Specifies the Configuration Register 1 For more information refer to page 3 42 of PL330 TRM 0x0000_0074 CR2 0xE090_0E08 R Specifies the Configuration Register 2 For more information refer to page 3 43 of PL330 TRM 0x0000_0000 CR3 0xE090_0E0C R Specifies the Configuration Register 3 For more information refer to page 3 44 of PL330 TRM 0xFFFF_FFF F CR4 0xE090_0E10 R Specifies...

Page 719: ...0034 R Specifies the Fault Status DMA Channel Register For more information refer to page 3 19 of PL330 TRM 0x0 FTM 0xE090_0038 R Specifies the Fault Type DMA Manager Register For more information refer to page 3 20 of PL330 TRM 0x0 Reserved 0xE090_003C Reserved FTC0 0xE090_0040 R Specifies the Fault Type for DMA Channel 0 0x0 FTC1 0xE090_0044 R Specifies the Fault Type for DMA Channel 1 0x0 FTC2 ...

Page 720: ...egisters For more information refer to page 3 27 of PL330 TRM SA_0 0xE090_0400 R Specifies the Source Address for DMA Channel 0 0x0 SA_1 0xE090_0420 R Specifies the Source Address for DMA Channel 1 0x0 SA_2 0xE090_0440 R Specifies the Source Address for DMA Channel 2 0x0 SA_3 0xE090_0460 R Specifies the Source Address for DMA Channel 3 0x0 SA_4 0xE090_0480 R Specifies the Source Address for DMA Ch...

Page 721: ...the Loop Counter 0 for DMA Channel 2 0x0 LC0_3 0xE090_046C R Specifies the Loop Counter 0 for DMA Channel 3 0x0 LC0_4 0xE090_048C R Specifies the Loop Counter 0 for DMA Channel 4 0x0 LC0_5 0xE090_04AC R Specifies the Loop Counter 0 for DMA Channel 5 0x0 LC0_6 0xE090_04CC R Specifies the Loop Counter 0 for DMA Channel 6 0x0 LC0_7 0xE090_04EC R Specifies the Loop Counter 0 for DMA Channel 7 0x0 Loop...

Page 722: ...e information refer to page 3 42 of PL330 TRM 0x0000_0074 CR2 0xE090_0E08 R Specifies the Configuration Register 2 For more information refer to page 3 43 of PL330 TRM 0x0000_0000 CR3 0xE090_0E0C R Specifies the Configuration Register 3 For more information refer to page 3 44 of PL330 TRM 0xFFFF_FFF F CR4 0xE090_0E10 R Specifies the Configuration Register 4 For more information refer to page 3 45 ...

Page 723: ...Address 0xFA20_04A8 CC_6 R Address 0xFA20_04C8 CC_7 R Address 0xFA20_04E8 CCn Bit Description Initial State dst_burst_size 17 15 Programs the burst size that DMAC uses when it writes the destination data b000 1 byte b001 2 bytes b010 4 bytes b011 8 bytes Other Reserved 0 src_burst_size 3 1 Programs the burst size that DMAC uses when it reads the source data b000 1 byte b001 2 bytes b010 4 bytes b0...

Page 724: ...90_0488 0xE0A0_0488 CC_5 R Address 0xE090_04A8 0xE0A0_04A8 CC_6 R Address 0xE090_04C8 0xE0A0_04C8 CC_7 R Address 0xE090_04E8 0xE0A0_04E8 CCn Bit Description Initial State D st_burst_size 17 15 Programs the burst size that DMAC uses when it writes the destination data b000 1 byte b001 2 bytes b010 4 bytes Other Reserved 0 src_burst_size 3 1 Programs the burst size that DMAC uses when it reads the s...

Page 725: ...request interfaces that the DMAC provides b11111 32 peripheral request interfaces 0x1F num_chnls 6 4 Specifies the number of DMA channels that the DMAC supports b111 8 DMA channels 0x7 mgr_ns_at_rst 2 Indicates the status of the boot_manager_ns signal when the DMAC exits from reset 1 boot_manager_ns was HIGH 1 boot_en 1 Indicates the status of the boot_from_pc signal when the DMAC exits from reset...

Page 726: ...ller 1 2 1 5 Configuration Register2 for DMA_PERI 0 1 CR2 R CR2 for DMA_PERI0 R Address 0xE090_0E08 CR2 for DMA_PERI1 R Address 0xE0A0_0E08 CR2 Bit Description Initial State boot_addr 31 0 Provides the value of boot_addr 31 0 when the DMAC exits from reset 32 b0 0 The first DMAC instruction fetch is to the address specified by DMA PC at reset value 1 2 1 6 Configuration Register3 for DMA_PERI 0 1 ...

Page 727: ...Address 0xE090_0E14 CRDn for DMA_PERI1 R Address 0xE0A0_0E14 CRDn Bit Description Initial State data_buffer_dep 29 20 Specifies the number of lines that data buffer contains b000000111 8 lines 0x7 rd_q_dep 19 16 Specifies the depth of read queue b0111 8 lines 0x7 rd_cap 14 12 Specifies the read issuing capability that programs the number of outstanding read transactions b011 4 0x3 wr_q_dep 11 8 Sp...

Page 728: ...r_ns_at_rst 2 Indicates the status of boot_manager_ns signal when the DMAC exits from reset 0 boot_manager_ns is set to LOW 0 boot_en 1 Indicates the status of boot_from_pc signal when the DMAC exits from reset 0 boot_from_pc is set to LOW 0 periph_req 0 Supports peripheral requests 1 DMAC provides the number of peripheral request interfaces that num_periph_req field specifies 1 1 2 1 10 Configura...

Page 729: ...ster3 for DMA_MEM CR3 R Address 0xFA20_0E0C CR3 Bit Description Initial State INS 31 0 Specifies the security state of interrupt outputs Bit N 1 Assigns irq N to non secure state 32 hffff_ffff 0xFFFF_FFFF 1 2 1 13 Configuration Register4 for DMA_MEM CR4 R Address 0xFA20_0E10 CR4 Bit Description Initial State PNS 31 0 Specifies the security state of peripheral request interfaces Bit N 1 Assigns per...

Page 730: ...rd_q_dep 19 16 Specifies the depth of read queue b0111 8 lines 0x7 rd_cap 14 12 Specifies the read issuing capability that programs the number of outstanding read transactions b011 4 0x3 wr_q_dep 11 8 Specifies the depth of write queue b0111 8 lines 0x7 wr_cap 6 4 Specifies the write issuing capability that programs the number of outstanding write transactions b011 4 0x3 data_width 2 0 Specifies t...

Page 731: ...30 TRM DMAKILL Kill M C See DMAKILL on page 4 13 of PL330 TRM DMAMOV Move C See DMAMOV on page 4 14 of PL330 TRM DMANOP No operation M C See DMANOP on page 4 16 of PL330 TRM DMARMB Read Memory Barrier C See DMARMB on page 4 16 of PL330 TRM DMASEV Send Event M C See DMASEV on page 4 17 of PL330 TRM DMAST Store C See DMAST S B on page 4 17 of PL330 TRM DMASTP Store and notify Peripheral C See DMASTP...

Page 732: ...R A Example DMAMOV SAR 0x24000000 o 0x2400_0000 is the source address of DMA operation DAR A Example DMAMOV DAR 0x24001000 o 0x2400_1000 is destination address of DMA operation CCR A Example DMAMOV CCR SB2 SS32 SP0 DB2 DS32 DP0 o Source Burst length is 2 32 bit data width o Destination Burst length is 2 32 bit data width o SP0 and DP0 mean normal and secure respectively SP2 and DP2 means normal an...

Page 733: ... to store zeros using AXI transactions specified by DAR and CCR For example if you define CCR as 32 bit and burst length as 2 the DMASTZ generates a bus transaction of 32 bit and burst length 2 with zeros at data bus 1 3 1 5 DMALP DMALPEND DMALP lc0 4 code DMALPEND lc0 loops iterates the code 4 times There are two loop counters lc0 and lc1 You can use nested loop by two loop counters 1 3 1 6 DMAWF...

Page 734: ...SFRs can receive only three instructions namely DMAGO DMASEV and DMAKILL o DMAGO starts a channel For more information refer to page number 3 38 3 40 and page number 4 6 4 8 in PL330 TRM C DBGCMD executes the instruction stored in the DBGINST0 and SFRs Example Load channel control register Single transfer 32 bit non secure DMAMOV CCR SB1 SS32 SP2 DB1 DS32 DP2 SB1 DB1 Burst length 1 SS32 DS32 32 bi...

Page 735: ...mem Runs in both secure ns bit at DMAGO instruction is 0 and non secure ns bit at DMAGO instruction is 1 modes B DMA_peri Runs in non secure ns bit at DMAGO instruction is 1 mode only 2 ASM code A For non secure transaction o Use SP2 and DP2 at DMAMOV instruction o APROT 1 will be 1 b1 B For secure transaction o Use SP0 and DP0 at DMAMOV instruction o APROT 1 will be 1 b0 ...

Page 736: ... DMAC sets irq N as HIGH 2 To set the corresponding IRQ HIGH by executing DMASEV program assembly code Use DMASEV instruction means an interrupt using one of the IRQ outputs 3 Clear the interrupt by writing to the Interrupt Clear Register Each bit in the INTCLR register controls the clearing of an interrupt Program to control the clearing of the IRQ outputs o Bit N 0 The status of irq N does not c...

Page 737: ...Section 7 TIMER ...

Page 738: ...ew of System Timer 2 1 2 2 Key Features of System Timer 2 2 2 3 Internal Function of System Timer 2 2 2 4 Detailed Operation 2 3 2 5 Tick Generation with Fractional Divider 2 4 2 6 Usage Model 2 6 2 6 1 Counter Setting 2 6 2 6 2 Interrupt 2 6 2 6 3 Count Value Update 2 6 2 6 4 START Timer 2 7 2 6 5 STOP Timer 2 7 2 6 6 Change Interval Interrupt at Run time 2 7 2 7 I O Description 2 8 2 8 Register ...

Page 739: ...ration Description 4 2 4 3 Leap Year Generator 4 3 4 4 Read Write Register 4 4 4 4 1 Backup Battery Operation 4 4 4 5 Alarm Function 4 4 4 6 Tick Time Interrupt 4 5 4 7 32 768khz X Tal Connection Example 4 6 4 8 RTC Start 4 6 4 9 I O Description 4 7 4 10 Register Description 4 8 4 10 1 Register Map 4 8 ...

Page 740: ... 8 Waveform when a Deadzone Feature is Enabled 1 11 Figure 2 1 Overall System Timer Block Diagram 2 1 Figure 2 2 Two Separate Timers 2 2 Figure 2 3 Timer Operation with Always on of Auto reload 2 3 Figure 2 4 Timer Operation Without Auto Reload One shot mode 2 3 Figure 2 5 Approximate 5Hz tick with 2Hz input clock 2 4 Figure 2 6 Approximate 1ms tick with RTC Clock Dedicated Fractional Divider 2 5 ...

Page 741: ...List of Tables Table Title Page Number Number Table 1 1 Minimum and Maximum Resolution based on Prescaler and Clock Divider Values 1 5 Table 1 1 Tick Interrupt Resolution 4 5 ...

Page 742: ...nd 4 select SCLK_PWM Each timer has its own 32 bit down counter which is driven by the timer clock The down counter is initially loaded from the Timer Count Buffer register TCNTBn If the down counter reaches zero the timer interrupt request is generated to inform the CPU that the timer operation is complete If the timer down counter reaches zero the value of corresponding TCNTBn automatically relo...

Page 743: ...CMPBn with 109 Start Timer Set the start bit and manually update this bit to off The TCNTBn value of 159 is loaded into the down counter and then the output TOUTn is set to low If down counter counts down the value from TCNTBn to value in the TCMPBn register 109 the output changes from low to high If the down counter reaches 0 it generates an interrupt request The down counter automatically reload...

Page 744: ... 1 4 1 8 1 16 PCLK SCLK_PWM SCLK_PWM SCLK_PWM SCLK_PWM SCLK_PWM SCLK_PWM Control Logic0 Control Logic1 Control Logic2 Control Logic3 Control Logic4 DeadZone Generator Deadzone Deadzone XpwmTOUT0 No pin XpwmTOUT1 1 1 1 1 XpwmTOUT2 XpwmTOUT3 Figure 1 2 PWM TIMER Clock Tree Diagram The Figure 1 2 shows the clock generation scheme for individual PWM Channels Each timer can generate level interrupts 1 ...

Page 745: ...iguration PWM is running Auto Reload and One Shot Pulse Mode One external input to start the PWM Dead Zone Generator on two PWM Outputs Level Interrupt Generation The PWM has two operation modes namely Auto Reload and One Shot Pulse Auto Reload Mode In this mode continuous PWM pulses are generated based on programmed duty cycle and polarity One Shot Pulse Mode In this mode only one PWM pulse is ge...

Page 746: ... 32 2KHz 133274 14s 1 16 PCLK 66MHz 0 485us 2 06MHz 62 061us 16 1KHz 266548 27s 1 3 2 BASIC TIMER OPERATION 3 3 2 0 1 1 0 2 1 0 0 TCNTBn 2 TCMPBn 0 manual update 0 auto reload 1 interrupt request interrupt request TCNTBn 3 TCMPBn 1 manual update 1 auto reload 1 TOUTn TCMPn TCNTn auto reload 0 command status timer is started TCNTn TCMPn auto reload start bit 1 TCNTn TCMPn timer is stopped Figure 1 ...

Page 747: ...NTBn 2 and TCMPBn 0 for the next operation 4 Set auto reload 1 and manual update 0 If you set manual update 1 at this time TCNTn is changed to 2 and TCMP is changed to 0 Therefore interrupt is generated at interval two cycle instead of three cycle You must set auto reload 1 automatically for the next operation 5 Set start 1 for starting the operation Then TCNTn is down counting If TCNTn is 0 inter...

Page 748: ...f TCNTBn is read the read value does not reflect the current state of the counter but the reload value for the next timer duration Auto reload is the operation copies the TCNTBn into TCNTn if TCNTn reaches 0 The value written to TCNTBn is loaded to TCNTn if the TCNTn reaches to 0 and auto reload is enabled If the TCNTn is 0 and the auto reload bit is 0 then TCNTn does not operate further Write TCN...

Page 749: ... level of TOUTn is changed from low to high 5 When TCNTn reaches 0 it generates interrupt request 6 TCNTn and TCMPn are automatically reloaded with TCNTBn and TCMPBn as 79 40 39 and 39 In the Interrupt Service Routine ISR the TCNTBn and TCMPBn are set as 79 20 59 and 59 7 If TCNTn and TCMPn have the same value the logic level of TOUTn is changed from low to high 8 When TCNTn reaches to 0 it genera...

Page 750: ...nverter on off bit whether inverter is used or not 3 Set the start bit of the corresponding timer to start the timer 1 3 6 PWM PULSE WIDTH MODULATION Write TCMPBn 60 Write TCMPBn 50 Write TCMPBn 40 Write TCMPBn 30 Write TCMPBn 30 Write TCMPBn next PWM 60 50 40 30 30 Figure 1 6 Example of PWM Use TCMPBn to implement the PWM feature PWM frequency is determined by TCNTBn A PWM value is determined by ...

Page 751: ...erter is off 1 Turn off the auto reload bit Then TOUTn goes to high level and the timer is stopped after TCNTn reaches to 0 This method is recommended 2 Stop the timer by clearing the timer start stop bit to 0 If TCNTn TCMPn the output level is high If TCNTn TCMPn the output level is low 3 TOUTn is inverted by the inverter on off bit in TCON The inverter removes the additional circuit to adjust th...

Page 752: ...me TOUT_0 specifies the PWM output nTOUT_0 specifies the inversion of the TOUT_0 If the dead zone is enabled the output wave form of TOUT_0 and nTOUT_0 is TOUT_0_DZ and nTOUT_0_DZ TOUT0_DZ and nTOUT_0_DZ cannot be turned on simultaneously by the dead zone interval For functional correctness the dead zone length must be set smaller than compare counter value TOUT0 nTOUT0 DEADZONE INTERVAL TOUT0_DZ ...

Page 753: ...OUT_0 Output PWMTIMER TOUT 0 XpwmTOUT 0 muxed TOUT_1 Output PWMTIMER TOUT 1 XpwmTOUT 1 muxed TOUT_2 Output PWMTIMER TOUT 2 XpwmTOUT 2 muxed TOUT_3 Output PWMTIMER TOUT 3 XpwmTOUT 3 muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals ...

Page 754: ... 1 Count Buffer Register 0x0000_0000 TCMPB1 0xE250_001C R W Specifies the Timer 1 Compare Buffer Register 0x0000_0000 TCNTO1 0xE250_0020 R Specifies the Timer 1 Count Observation Register 0x0000_0000 TCNTB2 0xE250_0024 R W Specifies the Timer 2 Count Buffer Register 0x0000_0000 TCMPB2 0xE250_0028 R W Specifies the Timer 2 Compare Buffer Register 0x0000_0000 TCNTO2 0xE250_002C R Specifies the Timer...

Page 755: ... prescaler value 1 255 divider value 1 2 4 8 16 TCLK Dead zone length 0 254 TCFG0 Bit Description Initial State Reserved 31 24 Reserved Bits 0x00 Dead zone length 23 16 Dead zone length 0x00 Prescaler 1 15 8 Prescaler 1 value for Timer 2 3 and 4 0x01 Prescaler 0 7 0 Prescaler 0 value for timer 0 and 1 0x01 NOTE If deadzone Length is set as n Real Dead Zone Length is n 1 n 0 254 ...

Page 756: ... 8 0100 1 16 0101 SCLK_PWM 0x00 Divider MUX1 7 4 Selects Mux input for PWM Timer 1 0000 1 1 0001 1 2 0010 1 4 0011 1 8 0100 1 16 0101 SCLK_PWM 0x00 Divider MUX0 3 0 Selects Mux input for PWM Timer 0 0000 1 1 0001 1 2 0010 1 4 0011 1 8 0100 1 16 0101 SCLK_PWM 0x00 NOTE If you use SCLK_PWM duty of TOUT can show minimal error SCLK_PWM is sampled by PCLK in PWM module But SCLK_PWM and PCLK is asynchro...

Page 757: ...One Shot 1 Interval Mode Auto Reload 0x0 Timer 2 Output Inverter on off 14 0 Inverter Off 1 TOUT_2 Inverter On 0x0 Timer 2 Manual Update 13 0 No Operation 1 Update TCNTB2 TCMPB2 0x0 Timer 2 Start Stop 12 0 Stop 1 Start Timer 2 0x0 Timer 1 Auto Reload on off 11 0 One Shot 1 Interval Mode Auto Reload 0x0 Timer 1 Output Inverter on off 10 0 Inverter Off 1 TOUT_1 Inverter On 0x0 Timer 1 Manual Update ...

Page 758: ...E250_0014 TCNTO0 Bit Description Initial State Timer 0 Count Observation 31 0 Timer 0 Count Observation Register 0x0000_0000 1 5 1 7 Timer1 Counter Register TCNTB1 R W Address 0xE250_0018 TCNTB1 Bit Description Initial State Timer 1 Count Buffer 31 0 Timer 1 Count Buffer Register 0x0000_0000 1 5 1 8 Timer1 Compare Register TCMPB1 R W Address 0xE250_001C TCMPB1 Bit Description Initial State Timer 1...

Page 759: ...E250_002C TCNTO2 Bit Description Initial State Timer 2 Count Observation 31 0 Timer 2 Count Observation Register 0x0000_0000 1 5 1 13 Timer3 Counter Register TCNTB3 R W Address 0xE250_0030 TCNTB3 Bit Description Initial State Timer 3 Count Buffer 31 0 Timer 3 Count Buffer Register 0x0000_0000 1 5 1 14 Timer2 Compare Register TCMPB2 R W Address 0xE250_0034 TCMPB2 Bit Description Initial State Timer...

Page 760: ...Status Bit Clears by writing 1 on this bit 0x0 Timer 3 Interrupt Status 8 Timer 3 Interrupt Status Bit Clears by writing 1 on this bit 0x0 Timer 2 Interrupt Status 7 Timer 2 Interrupt Status Bit Clears by writing 1 on this bit 0x0 Timer 1 Interrupt Status 6 Timer 1 Interrupt Status Bit Clears by writing 1 on this bit 0x0 Timer 0 Interrupt Status 5 Timer 0 Interrupt Status Bit Clears by writing 1 o...

Page 761: ...EW OF SYSTEM TIMER System timer provides two distinctive features namely It provides 1ms time tick at any power mode except sleep mode Changeable interrupt interval without stopping reference tick timer Figure 2 1 Overall System Timer Block Diagram 2 1 ...

Page 762: ...tick generation with RTC clock frequency 32 768 kHz 2 3 INTERNAL FUNCTION OF SYSTEM TIMER Figure 2 2 Two Separate Timers There are two separate system timers in S5PC110 The first timer is used for tick generation while the other is used for interrupt generation Two independent SFR sets and logic blocks are used for tick and interrupt region Each logic block operates separately Therefore you can ch...

Page 763: ...rupt is asserted when INTCNT value is expired INTCNT 0 SW reads ICNTO to know elapsed time NOTE As shown in Figure 2 3 when ICNTB is changed with interrupt manual update TCON 4 or ICNTB 31 the new changed value is applied to interrupt counter INTCNT at that time When ICNTB is changed without interrupt manual update TCON 4 or ICNTB 31 at Figure 2 3 the new changed value is applied to INTCNT interru...

Page 764: ... is no global frequency error If output clock frequency is much slower than input clock frequency the instance of local frequency error decreases To configure fractional divider divider mux and pre scaler cannot be used for fractional divider write TCFG 10 0 as 0 Write TCFG 14 as 1 1 General Write TCFG 15 as 0 Input frequency must be 4 times larger than target frequency VALUE Frequency of TCLKB 2 ...

Page 765: ... are not 1ms tick after 125 ticks it represents exact 125ms passed In other words there is no accumulation error Exact 125ms after 125 ticks 0 993KHz 0 993KHz 1 024 KHz Figure 2 6 Approximate 1ms tick with RTC Clock Dedicated Fractional Divider If you do not required to use fractional divider for making tick method for writing TICNTB and TFCNTB is as follows Write TCFG 14 as 0 Write TICNTB as the ...

Page 766: ...s the system timer uses RTC or XXTI clock for counter These clocks are slower than PCLK the operating clock of SFR After the write status interrupts are asserted the software can check whether the new value is really updated at the internal counter SW must wait until that time If you do not want to assert an interrupt continuously read INT_CSTAT polling method to know update timing In that case yo...

Page 767: ...t that time 9 Wait until TCON write interrupt occurs and write 1 to INT_CSTAT 5 to clear interrupt status bit 10 Write both TCON 3 1 to run interrupt and tick timer And also set interrupt type by TCON 5 at this time 11 Wait until TCON write interrupt occurs and write 1 to INT_CSTAT 5 to clear interrupt status bit 2 6 5 STOP TIMER 1 Write INT_CSTAT 6 1 b0 to disable Interrupt counter expired INTCNT...

Page 768: ...ds for system clock XXTI XXTO Dedicated XT_RTC_I XT_RTC_O In Out Oscillator pads for RTC clock XrtcXTI XrtcXTO Dedicated XT_USB_I XT_USB_O I O Oscillator pads for USB clock XusbXTI XusbXTO Dedicated NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals ...

Page 769: ...TICNTB E260_0008 R W Specifies the Tick Integer Count Buffer Register 0x0000_0000 TICNTO E260_000C R Specifies the Tick Integer Count Observation Register 0x0000_0000 TFCNTB E260_0010 R W Specifies the Tick Fractional Count Buffer Register 0x0000_0000 E260_0014 Reserved 0x0000_0000 ICNTB E260_0018 R W Specifies the Interrupt Count Buffer Register 0x0000_0000 ICNTO E260_001C R Specifies the Interru...

Page 770: ...timer uses fractional divider for TICKGEN TCFG 14 1 0x0 TICKGEN SEL 14 0 Integer divider 1 Fractional divider When integer divider is used don t care TCFG 15 and TFCNTB 0x0 TCLKB MUX 13 12 Selects clock input for TCLKB 00 System Main Clock XXTI or XUSB depends on OM 0 pin 01 XrtcXTI 10 XusbXTI 11 P APB CLK Usable clock source is restricted by power mode oscillator pad configuration XrtcXTI for any...

Page 771: ...terrupt set TCON 5 as 0 In that case the interrupt occurs at every TICK after interrupt counter reaches zero If you want to use interval mode for interrupt set TCON 5 as 1 In that case the value in ICNTB is automatically reloaded to INTCNT counter when INTCNT expires 2 8 1 3 TICK Integer Counter Register TICNTB R W Address E260_0008 Real Timer Counter Value TICNTB 1 Do not use 0 for TICNTB TICNTB ...

Page 772: ...ddress E260_0018 Real Interrupt Counter Value ICNTB 1 If ICNTB value is 0 interrupt occurs at every TICK ICNTB Bit Description Initial State Interrupt Manual Update 31 0 No operation 1 Update ICNTB This bit is auto cleared 0x0 Interrupt Count Buffer 30 0 Interrupt Count Buffer Register 0x0 2 8 1 7 Interrupt Observation Register ICNTO R Address E260_001C ICNTO Bit Description Initial State Reserved...

Page 773: ...ter user writes value to TCON this bit is asserted Clear by writing 1 on this bit 0x0 ICNTB Write Status 4 ICNTB Write Interrupt Status Bit After user writes value to ICNTB this bit is asserted Clear by writing 1 on this bit 0x0 TFCNTB Write Status 3 TFCTNB Write Interrupt Status Bit After user writes value to TFCNTB this bit is asserted Clear by writing 1 on this bit 0x0 TICNTB Write Status 2 TIC...

Page 774: ... errors WDT can be used as a normal 16 bit interval timer to request interrupt service The WDT generates the reset signal The difference between WDT and PWM timer is that WDT generates the reset signal 3 2 KEY FEATURES OF WATCHDOG TIMER Supports Normal interval timer mode with interrupt request Activates Internal reset signal if the timer count value reaches 0 Time out Supports Level triggered Int...

Page 775: ... The prescaler value and frequency division factor are specified in the watchdog timer control WTCON register Valid prescaler values range from 0 to 28 1 The frequency division factor can be selected as 16 32 64 or 128 Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle t_watchdog 1 PCLK Prescaler value 1 Division_factor 3 3 2 WTDAT...

Page 776: ...ust not operate if the S5PC110 is in debug mode using Embedded ICE The watchdog timer determines from the CPU core signal DBGACK signal whether it is currently in the debug mode Once the DBGACK signal is asserted the reset output of the watchdog timer is not activated as the watchdog timer expires ...

Page 777: ...ddress R W Description Reset Value WTCON 0xE270_0000 R W Watchdog Timer Control Register 0x00008021 WTDAT 0xE270_0004 R W Watchdog Timer Data Register 0x00008000 WTCNT 0xE270_0008 R W Watchdog Timer Count Register 0x00008000 WTCLRINT 0xE270_000C W Watchdog Timer Interrupt Clear Register ...

Page 778: ...d disable the Watchdog timer WTCON Bit Description Initial State Reserved 31 16 Reserved 0 Prescaler value 15 8 Prescaler value The valid range is from 0 to 28 1 0x80 Reserved 7 6 Reserved These two bits must be 00 in normal operation 00 Watchdog timer 5 Enables or disables Watchdog timer bit 0 Disables 1 Enables 1 Clock select 4 3 Determines the clock division factor 00 16 01 32 10 64 11 128 00 I...

Page 779: ...or the watchdog timer during normal operation Note that the content of the WTDAT register cannot be automatically loaded into the timer count register if the watchdog timer is enabled initially therefore the WTCNT register must be set to an initial value before enabling it WTCNT Bit Description Initial State Reserved 31 16 Reserved 0 Count value 15 0 The current count value of the watchdog timer 0...

Page 780: ...8 kHz crystal and performs the function of alarm 4 2 KEY FEATURES OF REAL TIME CLOCK Supports BCD Number that is Second Minute Hour Day of the week Day Month and Year Supports Leap Year Generator Supports Alarm Function that is Alarm Interrupt or Wake up from power down modes idle deep idle stop deep stop and sleep Supports Tick Counter Function that is Tick Interrupt or Wake up from power down mo...

Page 781: ...S5PC110_UM 4 REAL TIME CLOCK RTC 4 2 1 REAL TIME CLOCK OPERATION DESCRIPTION Figure 4 1 Real Time Clock Block Diagram 4 2 ...

Page 782: ... 31 This is calculated based on the data from BCDDAY BCDMON and BCDYEAR This block considers leap year while deciding on the last day of a month NOTE The BCDYEAR register is 12 bit wide It can represent maximum three BCD digits The implicit number of thousands place is 2 Therefore it can represent years from 400 n to 400 n 999 n 0 1 2 3 4 5 ...

Page 783: ...2060 Year 1 Month 1 Day 0 Hour and 0 Minute because of the one second deviation In this case you must read again from BCDYEAR to BCDSEC if BCDSEC is zero 4 4 1 BACKUP BATTERY OPERATION The backup battery can drive the RTC logic The backup battery supplies the power through the RTCVDD pin into the RTC block even if the system power is off If the system is off the interfaces of the CPU and RTC logic...

Page 784: ...384 2 14 0 262143 0 06 4 b0010 8192 2 13 0 524287 0 12 4 b0011 4096 2 12 0 1048575 0 24 4 b0100 2048 2 11 0 2097151 0 49 4 b0101 1024 2 10 0 4194303 0 97 4 b0110 512 2 9 0 8388607 1 95 4 b0111 256 2 8 0 16777215 3 90 4 b1000 128 2 7 0 33554431 7 81 4 b1001 64 2 6 0 67108863 15 62 4 b1010 32 2 5 0 134217727 31 25 4 b1011 16 2 4 0 268435455 62 50 4 b1100 8 2 3 0 536870911 125 4 b1101 4 2 2 0 1073741...

Page 785: ... 4 2 shows a circuit of the RTC unit oscillation at 32 768kHz The capacitance 20pF of the load capacitor is an example value It should be adjusted according to the crystal load capacitance Figure 4 2 Main Oscillator Circuit Example 4 8 RTC START To start RTC set RTCCON 0 as 1 4 6 ...

Page 786: ...Oscillator Clock Output XrtcXTO Dedicated XRTCCLKO Output 32 768 kHz RTC Clock Output 1 8 3 3V This signal is turned off by default It can be enabled by setting 1 in CLKOUTEN field of RTCCON register Note In order to use XRTCCLO ALIVE power must be supplied XRTCCLKO Dedicated NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals ...

Page 787: ...m Hour Data Register 0x00000000 ALMDAY 0xE280_0060 R W Specifies the Alarm Day Data Register 0x00000000 ALMMON 0xE280_0064 R W Specifies the Alarm Month Data Register 0x00000000 ALMYEAR 0xE280_0068 R W Specifies the Alarm Year Data Register 0x00000000 BCDSEC 0xE280_0070 R W Specifies the BCD Second Register Undefined BCDMIN 0xE280_0074 R W Specifies the BCD Minute Register Undefined BCDHOUR 0xE280...

Page 788: ...its of INTP register by writing 1 s to the bits that you want to clear regardless of RTCEN value INTP Bit Description Initial State Reserved 31 2 Reserved 0 ALARM 1 Alarm interrupt pending bit 0 No interrupt occurred 1 Interrupt occurred 0 Time TIC 0 Time TIC interrupt pending bit 0 No interrupt occurred 1 Interrupt occurred 0 ...

Page 789: ...ock output on XRTCCLKO pad 0 Disables 1 Enables 0 TICEN 8 Enables Tick timer 0 Disables 1 Enables 0 TICCKSEL 7 4 Tick timer sub clock selection 4 b0000 32768 Hz 4 b0001 16384 Hz 4 b0010 8192 Hz 4 b0011 4096 Hz 4 b0100 2048 Hz 4 b0101 1024 Hz 4 b0110 512 Hz 4 b0111 256 Hz 4 b1000 128 Hz 4 b1001 64 Hz 4 b1010 32 Hz 4 b1011 16 Hz 4 b1100 8 Hz 4 b1101 4 Hz 4 b1110 2 Hz 4 b1111 1 Hz 4 b0000 CLKRST 3 RT...

Page 790: ...operation mode Enable ALMEN to use ALARM_INT and ALARM_WK If compare value is year ALMEN and YEAREN must be enabled If compare values are year month day hour min and sec ALMEN YEAREN MONEN DAYEN HOUREN MINEN and SECEN must be enabled RTCALM Bit Description Initial State Reserved 31 7 Reserved 0 ALMEN 6 Enables Alarm global 0 Disables 1 Enables Note For using ALARM_INT and ALARM_WK set ALMEN as 1 b...

Page 791: ... Description Initial State Reserved 31 7 Reserved 0 6 4 BCD value for alarm minute 0 5 000 MINDATA 3 0 0 9 0000 4 10 1 7 Alarm Hour Data Register ALMHOUR R W Address 0xE280_005C ALMHOUR Bit Description Initial State Reserved 31 6 Reserved 0 5 4 BCD value for alarm hour 0 2 00 HOURDATA 3 0 0 9 0000 4 10 1 8 Alarm DaY Data Register ALMDAY R W Address 0xE280_0060 ALMDAY Bit Description Initial State ...

Page 792: ...xE280_0068 ALMYEAR Bit Description Initial State Reserved 31 8 Reserved 0 11 8 BCD value for alarm year 0 9 0000 7 4 0 9 0000 YEARDATA 3 0 0 9 0000 4 10 1 11 BCD Second Register BCDSEC R W Address 0xE280_0070 BCDSEC Bit Description Initial State Reserved 31 7 Reserved 6 4 BCD value for second 0 5 SECDATA 3 0 0 9 4 10 1 12 BCD Minute Register BCDMIN R W Address 0xE280_0074 BCDMIN Bit Description In...

Page 793: ...007C BCDDAY Bit Description Initial State Reserved 31 6 Reserved 5 4 BCD value for day 0 3 DAYDATA 3 0 0 9 4 10 1 15 BCD Day of the Week Register BCDDAYWEEK R W Address 0xE280_0080 BCDDAYWEEK Bit Description Initial State Reserved 31 3 Reserved DAYWEEKDATA 2 0 BCD value for a day of the week 1 7 4 10 1 16 BCD Month Register BCDMON R W Address 0xE280_0084 BCDMON Bit Description Initial State Reserv...

Page 794: ...s 0xE280_0088 BCDYEAR Bit Description Initial State Reserved 31 8 Reserved 11 8 BCD value for year 0 9 7 4 0 9 YEARDATA 3 0 0 9 4 10 1 18 Tick Counter Register CURTICCNT R Address 0xE280_0090 CURTICCNT Bit Description Initial State Tick counter observation 31 0 Current tick count value ...

Page 795: ...Section 8 CONNECTIVITY STORAGE ...

Page 796: ... Overview of IIC Bus Interface 2 1 2 2 Key Features of IIC Bus Inteface 2 2 2 3 IIC Bus Interface Operation 2 3 2 3 1 Start and Stop Conditions 2 3 2 3 2 Data Transfer Format 2 4 2 3 3 ACK Signal Transmission 2 5 2 3 4 Read Write Operation 2 6 2 3 5 Bus Arbitration Procedures 2 6 2 3 6 Abort Conditions 2 6 2 3 7 Configuring IIC Bus 2 6 2 3 8 Flowcharts of Operations in Each Mode 2 7 2 4 I O Descri...

Page 797: ... Global Registers 5 53 5 8 5 Host Mode Registers Host Port Control and Status Registers 5 57 5 8 6 Host Mode Registers Host Channel Specific Registers 5 60 5 8 7 Device Mode Registers Device Global Registers 5 65 6 Modem Interface 6 1 6 1 Overview of Modem Interface 6 1 6 2 Key Features of Modem Interface 6 2 6 3 Interrupt Ports 6 2 6 3 1 Wakeup 6 2 6 4 Address Mapping 6 3 6 5 Timing Diagram 6 4 6...

Page 798: ...0 1 Response Bit Definition for Each Response Type 7 45 7 10 2 Buffer Data Port Register 7 46 7 10 3 Present State Register 7 47 7 10 4 Host Control Register 7 53 7 10 5 Power Control Register 7 54 7 10 6 Block Gap Control Register 7 55 7 10 7 Wakeup Control Register 7 57 7 10 8 Clock Control Register 7 58 7 10 9 Timeout Control Register 7 60 7 10 10 Software Reset Register 7 61 7 10 11 Normal Int...

Page 799: ...sport Stream Interface 8 1 8 1 1 Key Features of Transport Stream Interface 8 1 8 1 2 Broadcast Mode 8 2 8 1 3 Block Diagram of TS Interface 8 4 8 1 4 I O Description of TSI 8 5 8 1 5 Functional Description 8 6 8 2 Register Description 8 16 8 2 1 Register Map 8 16 8 2 2 TSI Register Description 8 18 ...

Page 800: ...e 2 9 Figure 2 9 Operations for Slave Receiver Mode 2 10 Figure 3 1 SPI Transfer Format 3 4 Figure 3 2 Auto Chip Select Mode Waveform CPOL 0 CPHA 0 CH_WIDTH Byte 3 12 Figure 4 1 USB System Block Diagram 4 2 Figure 4 2 USB 2 0 Host Controller Block Diagram 4 3 Figure 5 1 System Level Block Diagram 5 2 Figure 5 2 OTG Link CSR Memory Map 5 6 Figure 5 3 OTG FIFO Mapping 5 7 Figure 5 4 USB PHY Clock Pa...

Page 801: ...mmand Inhibit DAT and Command Inhibit CMD with Data Transfer 7 51 Figure 7 19 Timing of Command Inhibit DAT for the Case of Response with Busy 7 52 Figure 7 20 Timing of Command Inhibit CMD for the Case of No Response Command 7 52 Figure 8 1 Support TSI in the Broadcasting Mode 8 2 Figure 8 2 TSI Block Diagram 8 4 Figure 8 3 Transport Stream Packet Data Format 8 6 Figure 8 4 Transport Stream Signa...

Page 802: ...ng Standard Mode 6 5 Table 6 4 Modem Interface Write Timing Address Muxed mode 6 6 Table 6 5 Modem Interface Read Timing Address Muxed mode 6 7 Table 7 1 ADMA Length Field 7 24 Table 7 2 ADMA States 7 26 Table 8 1 Characteristics of Several Mobile TV Standard Modes 8 3 Table 8 2 TSI I O Description 8 5 Table 8 3 Sync Detection Process using Sync Byte sync_det_cnt 3 8 10 Table 8 4 Sync Detection Pr...

Page 803: ...o stop bit insertion 5 bit 6 bit 7 bit or 8 bit data width and parity checking Each UART contains a baud rate generator a transmitter a receiver and a control unit as shown in Figure 1 1 The baud rate generator uses PCLK or SCLK_UART The transmitter and the receiver contain FIFOs and data shifters The data to be transmitted is written to Tx FIFO and copied to the transmit shifter The data is then ...

Page 804: ...IFO mode Transmit Holding Register Non FIFO mode Receive FIFO Register FIFO mode Receive Holding Register Non FIFO mode only In FIFO mode all bytes of Buffer Register are used as FIFO register In non FIFO mode only 1 byte of Buffer Register is used as Holding register Transmit Shifter Transmit Buffer Register Receive Shifter Receive Buffer Register Figure 1 1 Block Diagram of UART ...

Page 805: ...verwritten the old data before the old data was read Parity error indicates that the receiver has detected an unexpected parity condition Frame error indicates that the received data does not have a valid stop bit Break condition indicates that the RxDn input is held in the logic 0 state for more than one frame transmission time Receive time out condition occurs if no data is received during the 3...

Page 806: ...with FIFO 1 Select the transmit mode Interrupt or DMA mode 2 Check the value of Rx FIFO count in UFSTATn register If the value is less than 16 you must set the value of UMCONn 0 to 1 activate nRTS However if the value equal to or larger than 16 you must set the value to 0 inactivate nRTS 3 Repeat the Step 2 1 3 4 2 Tx Operation with FIFO 1 Select the transmit mode Interrupt or DMA mode 2 Check the...

Page 807: ... a receive error status interrupt request is detected you can identify the source of interrupt by reading the value of UERSTATn If the receiver transfers data of the receive shifter to the receive FIFO register in FIFO mode and the number of received data is greater than or equal to the Rx FIFO Trigger Level Rx interrupt is generated if Receive mode in control register UCONn is set to 1 Interrupt ...

Page 808: ...rror occurs at the same time only one interrupt is generated 1 3 8 UART ERROR STATUS FIFO UART contains the error status FIFO besides the Rx FIFO register The error status FIFO indicates which data among FIFO registers is received with an error An error interrupt is issued only if the data containing an error is ready to read out To clear the error status FIFO URXHn with an error and UERSTATn must...

Page 809: ... ASYNCHRONOUS RECEIVER AND TRANSMITTER 1 7 E D C B A Rx FIFO URXHn UERSTATn break error parity error frame error Error Status Generator Unit Error Status FIFO Figure 1 3 UART Receives the Five Characters Including Two Errors ...

Page 810: ...smit mode the transmit pulse comes out at the rate of 3 16 that is normal serial transmit rate if the transmit data bit is 0 In IR receive mode however the receiver must detect the 3 16 pulsed period to recognize a 0 value Refer to the frame timing diagrams shown in Figure 1 5 and Figure 1 7 IrDA Tx Encoder 0 1 0 1 IrDA Rx D ecoder TxD R xD TxD IRS RxD RE UAR T Block Figure 1 4 IrDA Function Block...

Page 811: ...t Bit Stop Bit Data Bits IR Transmit Frame Bit Time Pulse Width 3 16 Bit Frame 0 0 0 0 1 1 1 1 1 Figure 1 6 Infra Red Transmit Mode Frame Timing Diagram 0 Start Bit Stop Bit Data Bits IR Receive Frame 0 0 0 0 1 1 1 1 1 Figure 1 7 Infra Red Receive Mode Frame Timing Diagram ...

Page 812: ...igure 1 8 Input Clock Diagram for UART S5PC110 provides UART with a variety of clocks As described in the Figure 1 8 the UART is able to select clocks from PCLK or SCLK_UART which is from clock controller You can also select SCLK_UART from PLLs To select SCLK_UART please refer to Section 2 3 Clock Controller ...

Page 813: ...UART1 XuCTSn 1 muxed UART_1_RTSn Output Requests to Send active low for UART1 XuRTSn 1 muxed UART_2_RXD Input Receives Data for UART2 XuRXD 2 muxed UART_2_TXD Output Transmits Data for UART2 XuTXD 2 muxed UART_2_CTSn Input Clears to Send active low for UART2 XuRXD 3 muxed UART_2_RTSn Output Requests to Send active low for UART2 XuTXD 3 muxed UART_3_RXD Input Receives Data for UART3 XuRXD 3 muxed U...

Page 814: ...hannel 0 Transmit Buffer Register URXH0 0xE290_0024 R Specifies the UART Channel 0 Receive Buffer Register 0x00000000 UBRDIV0 0xE290_0028 R W Specifies the UART Channel 0 Baud Rate Divisor Register 0x00000000 UDIVSLOT0 0xE290_002C R W Specifies the UART Channel 0 Dividing Slot Register 0x00000000 UINTP0 0xE290_0030 R W Specifies the UART Channel 0 Interrupt Pending Register 0x00000000 UINTSP0 0xE2...

Page 815: ...0000 ULCON2 0xE290_0800 R W Specifies the UART Channel 2 Line Control Register 0x00000000 UCON2 0xE290_0804 R W Specifies the UART Channel 2 Control Register 0x00000000 UFCON2 0xE290_0808 R W Specifies the UART Channel 2 FIFO Control Register 0x00000000 UMCON2 0xE290_080C R W Specifies the UART Channel 2 Modem Control Register 0x00000000 UTRSTAT2 0xE290_0810 R Specifies the UART Channel 2 Tx Rx St...

Page 816: ...Rx Status Register 0x00000006 UERSTAT3 0xE290_0C14 R Specifies the UART Channel 3 Rx Error Status Register 0x00000000 UFSTAT3 0xE290_0C18 R Specifies the UART Channel 3 FIFO Status Register 0x00000000 UMSTAT3 0xE290_0C1C R Specifies the UART Channel 3 Modem Status Register 0x00000000 UTXH3 0xE290_0C20 W Specifies the UART Channel 3 transmit Buffer Register URXH3 0xE290_0C24 R Specifies the UART Ch...

Page 817: ...6 Determines whether to use the Infrared mode 0 Normal mode operation 1 Infrared Tx Rx mode 0 Parity Mode 5 3 Specifies the type of parity generation to be performed and checking during UART transmit and receive operation 0xx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 000 Number of Stop Bit 2 Specifies how many stop bits are used to signa...

Page 818: ...ested when the Tx buffer is empty in the Non FIFO mode or when it reaches Tx FIFO Trigger Level in the FIFO mode 1 Level Interrupt is requested when Tx buffer is empty in the Non FIFO mode or when it reaches Tx FIFO Trigger Level in the FIFO mode 0 Rx Interrupt Type 8 Interrupt request type 2 0 Pulse Interrupt is requested when instant Rx buffer receives data in the Non FIFO mode or when it reache...

Page 819: ...it buffer register 00 Disables 01 Interrupt request or polling mode 10 DMA mode 11 Reserved 00 Receive Mode 1 0 Determines which function is able to read data from UART receive buffer register 00 Disables 01 Interrupt request or polling mode 10 DMA mode 11 Reserved 00 NOTE 1 DIV_VAL UBRDIVn num of 1 s in UDIVSLOTn 16 Refer to 1 6 1 11 UART Channel Baud Rate Division Register and 1 6 1 12 UART Chan...

Page 820: ...nnel 0 000 0 byte 001 32 bytes 010 64 bytes 011 96 bytes 100 128 bytes 101 160 bytes 110 192 bytes 111 224 bytes Channel 1 000 0 byte 001 8 bytes 010 16 bytes 011 24 bytes 100 32 bytes 101 40 bytes 110 48 bytes 111 56 bytes Channel 2 3 000 0 byte 001 2 bytes 010 4 bytes 011 6 bytes 100 8 bytes 101 10 bytes 110 12 bytes 111 14 bytes 000 Reserved 7 Reserved 0 Rx FIFO Trigger Level 6 4 Determines the...

Page 821: ... 0 Tx FIFO Reset 2 Auto clears after resetting FIFO 0 Normal 1 Tx FIFO reset 0 Rx FIFO Reset 1 Auto clears after resetting FIFO 0 Normal 1 Rx FIFO reset 0 FIFO Enable 0 0 Disables 1 Enables 0 NOTE If the UART does not reach the FIFO trigger level and does not receive data during 3 word time in DMA receive mode with FIFO the Rx interrupt will be generated receive time out You must check the FIFO st...

Page 822: ...es 011 160 bytes 100 128 bytes 101 96 bytes 110 64 bytes 111 32 bytes Channel 1 000 63 bytes 001 56 bytes 010 48 bytes 011 40 bytes 100 32 bytes 101 24 bytes 110 16 bytes 111 8 bytes Channel 2 000 15 bytes 001 14 bytes 010 12 bytes 011 10 bytes 100 8 bytes 101 6 bytes 110 4 bytes 111 2 bytes 000 Auto Flow Control AFC 4 0 Disables 1 Enables 0 Modem Interrupt Enable 3 0 Disables 1 Enables 0 Reserved...

Page 823: ... transmit buffer and shifter register empty 1 Transmit buffer empty 1 This bit is automatically set to 1 if transmit buffer register is empty 0 Buffer register is not empty 1 Buffer register is empty In Non FIFO mode Interrupt or DMA is requested In FIFO mode Interrupt or DMA is requested if Tx FIFO Trigger Level is set to 00 Empty If UART uses FIFO check Tx FIFO Count bits and Tx FIFO Full bit in...

Page 824: ...his bit is automatically set to 1 if a frame error occurs during the receive operation 0 No frame error occurs during the receive operation 1 Frame error occurs Interrupt is requested during the receive operation 0 Parity Error 1 This bit is automatically set to 1 if a parity error occurs during the receive operation 0 No parity error occurs during receive the receive operation 1 Parity error occu...

Page 825: ...iption Initial State Reserved 31 25 Reserved 0 Tx FIFO Full 24 This bit is automatically set to 1 if the transmitted FIFO is full during transmit operation 0 Not full 1 Full 0 Tx FIFO Count 23 16 Number of data in Tx FIFO 0 Reserved 15 10 0 Rx FIFO Error 9 This bit is set to 1 if Rx FIFO contains invalid data which results from frame error parity error or break signal 0 Rx FIFO Full 8 This bit is ...

Page 826: ... the UART block namely UMSTAT0 UMSTAT1 and UMSTAT2 UMSTAT0 Bit Description Initial State Reserved 31 5 Reserved 0 Delta CTS 4 This bit indicates that the nCTS input to the S5PC110 has changed its state since the last time it was read by CPU Refer Figure 1 9 0 Has not changed 1 Has changed 0 Reserved 3 1 Reserved 00 Clear to Send 0 0 CTS signal is not activated nCTS pin is high 1 CTS signal is acti...

Page 827: ...ved 31 8 Reserved UTXHn 7 0 Transmit data for UARTn 1 6 1 10 UART Recive Buffer Register Holding Register FIFO Register URXH0 R Address 0xE290_0024 URXH1 R Address 0xE290_0424 URXH2 R Address 0xE290_0824 URXH3 R Address 0xE290_0C24 There are four UART receive buffer registers in the UART block namely URXH0 URXH1 URXH2 and URXH3 URXHn contains 8 bit data for received data URXHn Bit Description Init...

Page 828: ... UBRDIV1 R W Address 0xE290_0428 UBRDIV2 R W Address 0xE290_0828 UBRDIV3 R W Address 0xE290_0C28 UBRDIV n Bit Description Initial State Reserved 31 16 Reserved 0 UBRDIVn 15 0 Baud rate division value When UART clock source is PCLK UBRDIVn must be more than 0 UBRDIVn 0 0x0000 NOTE If UBRDIV value is 0 UART baudrate is not affected by UDIVSLOT value ...

Page 829: ...UBRDIV1 UBRDIV2 and UBRDIV3 The value stored in the baud rate divisor register UBRDIVn and dividing slot register UDIVSLOTn is used to determine the serial Tx Rx clock rate baud rate as follows DIV_VAL UBRDIVn num of 1 s in UDIVSLOTn 16 DIV_VAL PCLK bps x 16 1 or DIV_VAL SCLK_UART bps x 16 1 Where the divisor should be from 1 to 216 1 Using UDIVSLOT you can generate the baud rate more accurately F...

Page 830: ...1b 6 0x4A52 0100_1010_0101_0010b 14 0xDFDF 1101_1111_1101_1111b 7 0x54AA 0101_0100_1010_1010b 15 0xFFDF 1111_1111_1101_1111b 2 Baud Rate Error Tolerance UART Frame error should be less than 1 87 3 160 tUPCLK UBRDIVn 1 x 16 x 1Frame PCLK or SCLK_UART tUPCLK Real UART Clock tEXTUARTCLK 1Frame baud rate tEXTUARTCLK Ideal UART Clock UART error tUPCLK tEXTUARTCLK tEXTUARTCLK x 100 1Frame start bit data...

Page 831: ...channel generates interrupt This register must be cleared in the interrupt service routine after clearing interrupt pending register in Interrupt Controller INTC Clear specific bits of UINTP register by writing 1 s to the bits that you want to clear 1 6 1 14 UART Interrupt Source Pending Register UINTSP0 R W Address 0xE290_0034 UINTSP1 R W Address 0xE290_0434 UINTSP2 R W Address 0xE290_0834 UINTSP...

Page 832: ...t to 1 interrupt request signal to the Interrupt Controller is not generated even though corresponding interrupt is generated Note Even in such a case the corresponding bit of UINTSPn register is set to 1 If the mask bit is 0 the interrupt requests are serviced from the corresponding interrupt source UINTMn Bit Description Initial State Reserved 31 4 Reserved 0 MODEM 3 Mask Modem interrupt 0 TXD 2...

Page 833: ...CCON Multi master I2C bus control status register I2CSTAT Multi master I2C bus Tx Rx data shift register I2CDS Multi master I2C bus address register I2CADD If the I2C bus is free both SDA and SCL lines should be both at High level A High to Low transition of SDA initiates a Start condition A Low to High transition of SDA initiates a Stop condition while SCL remains steady at High Level The master ...

Page 834: ...ATURES OF IIC BUS INTEFACE Four channel Multi Master Slave I2C BUS interfaces one channel for general purpose one channel for PMIC two channel for HDMI dedicated 7 bit addressing mode Serial 8 bit oriented and bidirectional data transfer Supports up to 100kbit s in the Standard mode Supports up to 400kbit s in the Fast mode Supports master transmit master receive slave transmit and slave receive o...

Page 835: ...top condition terminates the data transfer A Stop condition is a Low to High transition of the SDA line while SCL is High The master generates Start and Stop conditions The I2C bus gets busy if a Start condition is generated On the other hand a Stop condition frees the I2C bus If a master initiates a Start condition it should send a slave address to notify the slave device One byte of address fiel...

Page 836: ...are sent first NOTES 1 S Start rS Repeat Start P Stop A Acknowledge 2 From Master to Slave From Slave to Master Write Mode Format with 7 bit Addresses 0 Write Data Transferred Data Acknowledge S Slave Address 7bits R W A P DATA 1Byte A Read Mode Format with 7 bit Addresses 1 Read Data Transferred Data Acknowledge S Slave Address 7 bits R W A P DATA A Figure 2 3 I2C Bus Interface Data Format SDA Ac...

Page 837: ... line to High to release the SDA line if the ACK clock pulse is received The receiver drives the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High period of the ninth SCL pulse The software I2CSTAT enables or disables ACK bit transmit function However the ACK pulse on the ninth clock of SCL is required to complete the one byte data transfer operation Data Output by ...

Page 838: ...ed itself or not For the purpose of evaluation each master detects the address bits While each master generates the slave address it detects the address bit on the SDA line because the SDA line is likely to get Low rather than high Assume that one master generates a Low as first address bit while the other master is maintaining High In this case both masters detect Low on the bus because the Low s...

Page 839: ... I2CSTAT to enable Serial Output Write slave address to I2CDS Write 0xF0 M T Start to I2CSTAT The data of the I2CDS is transmitted After ACK period interrupt is pending Write 0xD0 M T Stop to I2CSTAT Write new data transmitted to I2CDS Stop Clear pending bit to resume The data of the I2CDS is shifted to SDA START Master Tx mode has been configured Clear pending bit Wait until the stop condition ta...

Page 840: ...ress is transmitted After ACK period interrupt is pending Write 0x90 M R Stop to I2CSTAT Read a new data from I2CDS Stop Clear pending bit to resume SDA is shifted to I2CDS START Master Rx mode has been configured Clear pending bit Wait until the stop condition takes effect END Y N Figure 2 7 Operations for Master Receiver Mode ...

Page 841: ... and I2CDS the received slave address Write data to I2CDS The I2C address match interrupt is generated Clear pending bit to resume The data of the I2CDS is shifted to SDA START Slave Tx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 2 8 Operations for Slave Transmitter Mode ...

Page 842: ...es I2CADD and I2CDS the received slave address Read data from I2CDS The I2C address match interrupt is generated Clear pending bit to resume SDA is shifted to I2CDS START Slave Rx mode has been configured END Matched N Y Stop Interrupt is pending N Y Figure 2 9 Operations for Slave Receiver Mode ...

Page 843: ...a Line Xi2c0SDA muxed I2C2_SCL Input Output I2C BUS Interface2 Serial Clock Line Xi2c2SCL muxed I2C2_SDA Input Output I2C BUS Interface2 Serial Data Line Xi2c2SDA muxed I2C_HDMI_DDC_SCL Input Output I2C BUS Interface for HDMI DDC Serial Clock Line Xi2c1SCL muxed I2C_HDMI_DDC_SDA Input Output I2C BUS Interface for HDMI DDC Serial Data Line Xi2c1SDA muxed NOTE I2C BUS Interface for HDMI PHY is inter...

Page 844: ...0x00 I2CCON_HD MI_DDC 0xFAB0_0000 R W Specifies the I2C Bus Interface for HDMI DDC control register 0x0X I2CSTAT_HD MI_DDC 0xFAB0_0004 R W Specifies the I2C Bus Interface for HDMI DDC control status register 0x00 I2CADD_HD MI_DDC 0xFAB0_0008 R W Specifies the I2C Bus Interface for HDMI DDC address register 0xXX I2CDS_HDMI _DDC 0xFAB0_000C R W Specifies the I2C Bus Interface for HDMI DDC transmit r...

Page 845: ...pt is pending If read 2 Clear pending condition and Resume the operation If write 1 1 Interrupt is pending If read 2 N A If write 0 Transmit clock value 4 3 0 I2C Bus transmit clock prescaler I2C Bus transmit clock frequency is determined by this 4 bit prescaler value according to the following formula Tx clock I2CCLK I2CCON 3 0 1 Undefined NOTE 1 Interfacing with EEPROM the ACK generation may be ...

Page 846: ...e data in I2CDS is transferred automatically just after the start signal 0 Serial output 4 I2C bus data output enable disable bit 0 Disables Rx Tx 1 Enables Rx Tx 0 Arbitration status flag 3 I2C bus arbitration procedure status flag bit 0 Bus arbitration successful 1 Bus arbitration failed during serial I O 0 Address as slave status flag 2 I2C bus address as slave status flag bit 0 Cleared when ST...

Page 847: ...is read any time regardless of the current serial output enable bit I2CSTAT setting Slave address 7 1 Not mapped 0 Undefined 2 5 1 4 Multi Master I2C Bus Transmit Receive Data Shift Register I2CDS0 R W Address 0xE180_000C I2CDS2 R W Address 0xE1A0_000C I2CDS_HDMI_DDC R W Address 0xFAB0_000C I2CDS_HDMI_PHY R W Address 0xFA90_000C I2CDS Bit Description Initial State Data shift 7 0 8 bit data shift r...

Page 848: ...xFA90_0010 I2CLC Bit Description Initial State Filter enable 2 I2C bus filter enable bit If SDA port is operating as input this bit should be High This filter prevents error caused by glitch between two PCLK clock 0 Disables Filter 1 Enables Filter 0 SDA output delay 1 0 I2C Bus SDA line delay length selection bits SDA line is delayed as following clock time PCLK 00 0 clocks 01 5 clocks 10 10 cloc...

Page 849: ...pports the protocols for National Semiconductor Microwire and Motorola Serial Peripheral Interface 3 2 KEY FEATURES OF SERIAL PERIPHERAL INTERFACE The features of SPI include Full duplex 8 16 32 bit shift register for TX RX 8 bit Prescaler logic 2 clock sources PCLK and SPI_EXT_CLK from SYSCON Supports 8 bit 16 bit 32 bit bus interface Supports the Motorola SPI protocol and National Semiconductor ...

Page 850: ...ted valid bits are from 0 bit to 7 bit User can define the trigger threshold to raise interrupt to CPU The trigger level of each FIFO in port 0 is set by 4 bytes step from 0 byte to 252 bytes and that of each FIFO in port 1 is set by 1 byte step from 0 byte to 63 bytes TxDMAOn or RxDMAOn bit of SPI_MODE_CFG register must be set to use DMA access DMA access supports only single transfer and 4 burst...

Page 851: ...rnal SPICLK If SPI runs at high operating frequency such as 50MHz it is difficult to capture the MISO input because the required arrival time of MISO which is an half cycle period in S5PC110 is shorter than the arrival time of MISO that consists of SPICLK output delay of SPI master MISO output delay of SPI slave and MISO input delay of SPI master To overcome the problem S5PC110 SPI provides 3 feed...

Page 852: ... 1 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 1 CPHA 0 Format A Cycle MOSI 1 2 3 4 5 6 7 8 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB SPICLK MISO LSB CPOL 0 CPHA 1 Format B Cycle MOSI 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MSB SPICLK MISO MSB CPOL 0 CPHA 0 Format A LSB MSB MSB MSB MSB of previous frame LSB LSB of next frame LSB LSB of ...

Page 853: ...de is used to get data from slave output port Data are transmitted to master through this port in slave mode Out when used as slave In when used as master XspiMISO 0 XspiMISO 1 muxed SPI_0_MOSI SPI_1_MOSI In Out This port is the output port in Master mode This port is used to transfer data from master output port Data are received from master through this port in slave mode Out when used as master...

Page 854: ...R_REG0 0xE1300024 R W Specifies the SPI Port 0 Interrupt Pending Clear Register 0x0 SWAP_CFG0 0xE1300028 R W Specifies the SPI Port 0 Swap Config Register 0x0 FB_CLK_SEL0 0xE130002C R W Specifies the SPI Port 0 Feedback Clock Selection Register 0x0 CH_CFG1 0xE1400000 R W Specifies the SPI Port 1 Configuration Register 0x0 CLK_CFG1 0xE1400004 R W Specifies the SPI Port 1 Clock Configuration Registe...

Page 855: ...ERAL INTERFACE 3 7 Register Address R W Description Reset Value SWAP_CFG1 0xE1400028 R W Specifies the SPI Port 1 Swap Config Register 0x0 FB_CLK_SEL1 0xE140002C R W Specifies the SPI Port 1 Feedback Clock Selection Register 0x0 ...

Page 856: ...PHA set 2 Set Feedback Clock Selection register 3 Set Clock configuration register 4 Set SPI MODE configuration register 5 Set SPI INT_EN register 6 Set PACKET_CNT_REG register if necessary 7 Set Tx or Rx Channel on 8 Set nSSout low to start Tx or Rx operation a Set nSSout Bit to low then start TX data writing b If auto chip selection bit is set nSSout is controlled automatically ...

Page 857: ...ST 5 Software reset The following registers and bits are cleared by this bit Rx Tx FIFO Data SPI_STATUS Once reset this bit must be clear manually 0 Inactive 1 Active 0 SLAVE 4 Whether SPI Channel is Master or Slave 0 Master 1 Slave 0 CPOL 3 Determines whether active high or active low clock 0 Active High 1 Active Low 0 CPHA 2 Select one of the two fundamentally different transfer format 0 Format ...

Page 858: ...130_0004 CLK_CFG1 R W Address 0xE140_0004 CLK_CFGn Bit Description Initial State SPI_CLKSEL 9 Clock source selection to generate SPI clock out 0 PCLK 1 SPI_EXT_CLK 0 ENCLK 8 Clock enable disable 0 Disable 1 Enable 0 SPI_SCALER 7 0 SPI clock out division rate SPI clock out Clock source 2 x Prescaler value 1 0 ...

Page 859: ...ytes 4 x N Port 1 trigger level bytes N N value of RX_RDY_LVL field 0 TX_RDY_LVL 10 5 Tx FIFO trigger level in INT mode Port 0 trigger level bytes 4 x N Port 1 trigger level bytes N N value of TX_RDY_LVL field 0 Reserved 4 3 Reserved RX_DMA_SW 2 Rx DMA mode enable disable 0 Disables DMA Mode 1 Enables DMA Mode 0 TX_DMA_SW 1 Tx DMA mode on off 0 Disables DMA Mode 1 Enables DMA Mode 0 DMA_TYPE 0 DMA...

Page 860: ...ved AUTO_N_MANUAL 1 Chip select toggle manual or auto selection 0 Manual 1 Auto 0 NSSOUT 0 Slave selection signal manual only 0 Active 1 Inactive 1 If AUTO_N_MANUAL is set NSSOUT is controlled by SPI controller and data transfer is not performed continuously Unit data size depends on CH_WIDTH SPICLK MOSI MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB MISO NSSOUT MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB MS...

Page 861: ...t Enable for RxOverrun 0 Disables 1 Enables 0 INT_EN_RX_UNDERRUN 4 Interrupt Enable for RxUnderrun 0 Disables 1 Enables 0 INT_EN_TX_OVERRUN 3 Interrupt Enable for TxOverrun 0 Disables 1 Enables 0 INT_EN_TX_UNDERRUN 2 Interrupt Enable for TxUnderrun In slave mode this bit must be clear first after turning on slave TX path 0 Disables 1 Enables 0 INT_EN_RX_FIFO_RDY 1 Interrupt Enable for RxFifoRdy IN...

Page 862: ...64 bytes in port 0 TX_FIFO_LVL 14 6 Data level in Tx FIFO 0 256 bytes in port 0 0 64 bytes in port 0 RX_OVERRUN 5 Rx FIFO overrun error 0 No Error 1 Overrun Error 0 RX_UNDERRUN 4 Rx FIFO underrun error 0 No Error 1 Underrun Error 0 TX_OVERRUN 3 Tx FIFO overrun error 0 No Error 1 Overrun Error 0 TX_UNDERRUN 2 Tx FIFO underrun error Tx FIFO underrun error is occurred if TX FIFO is empty in slave mod...

Page 863: ... 8 SPI RX Data Register SPI_RX_DATA0 R Address 0xE130_001C SPI_RX_DATA1 R Address 0xE140_001C SPI_RX_DATAn Bit Description Initial State RX_DATA 31 0 This field contains the data to be received over the SPI channel 0 3 4 2 9 Packet Count Register PACKET_CNT_REG0 R W Address 0xE130_0020 PACKET_CNT_REG1 R W Address 0xE140_0020 PACKET_CNT_REGn Bit Description Initial State PACKET_CNT_EN 16 Enable bit...

Page 864: ...ending clear bit 0 Non Clear 1 Clear 0 TX_OVERRUN_CLR 3 TX overrun pending clear bit 0 Non Clear 1 Clear 0 RX_UNDERRUN_CLR 2 RX underrun pending clear bit 0 Non clear 1 Clear 0 RX_OVERRUN_CLR 1 RX overrun pending clear bit 0 Non Clear 1 Clear 0 TRAILING_CLR 0 Trailing pending clear bit 0 Non Clear 1 Clear 0 NOTE After error interrupt pending clear SPI controller should be reset Error interrupt lis...

Page 865: ...8 SWAP_CFGn Bit Description Initial State RX_HWORD_SWAP 7 0 Off 1 Swap 0 RX_BYTE_SWAP 6 0 Off 1 Swap 0 RX_BIT_SWAP 5 0 Off 1 Swap 0 RX_SWAP_EN 4 Swap enable 0 Normal 1 Swap 0 TX_HWORD_SWAP 3 0 Off 1 Swap 0 TX_BYTE_SWAP 2 0 Off 1 Swap 0 TX_BIT_SWAP 1 0 Off 1 Swap 0 TX_SWAP_EN 0 Swap enable 0 Normal 1 Swap 0 NOTE Data size must be larger than swap size ...

Page 866: ...inds of feedback clocks which experience different path delays This register selects which one is to be used Note that this register value is meaningless when SPI operates in slave mode 00 SPICLK bypass do not use feedback clock 01 A feedback clock with 90 degree phase lagging 10 A feedback clock with 180 degree phase lagging 11 A feedback clock with 270 degree phase lagging NOTE 90 degree phase l...

Page 867: ...plies with Enhanced HCI EHCI Rev 1 0a and Open HCI OHCI Rev1 0 specifications Both EHCI and OHCI compatible Complies with USB Rev 2 0 specification Complies with USB Rev 1 1 specification Supports high speed 480 Mbps transfer peripherals Supports power management features such as Full Suspend Resume functionality including Remote Wakeup Over current protection on ports hooks for master clock suspe...

Page 868: ...two independent blocks namely USB HOST 2 0 controller and USB PHY Controller Each of these blocks has an AHB Slave interface that provides the microcontroller with read and write access to the Control and Status Registers CSRs The HOST Link has an AHB Master to enable the link to transfer data on the AHB Figure 4 1 USB System Block Diagram ...

Page 869: ...n EHCI Operation Register Root Hub List Porcessor Packet Buffer USB 1 1 OHCI Host Controller USB 2 0 EHCI Host Controller USB PHY1 AHB BIU XuhostDP XuhostDM AHB Master Slave Interfac USB 2 0 Host Controller Figure 4 2 USB 2 0 Host Controller Block Diagram ...

Page 870: ...tor 0x00000000 PERIODICLISTBASE 0xEC20_0024 R W Specifies the Periodic Frame List Base Address Register 0x00000000 ASYNCLISTADDR 0xEC20_0028 R W Specifies the Asynchronous List Address 0x00000000 Implemented Auxiliary Registers for USB Host Controller CONFIGFLAG 0xEC20_0050 R W Specifies the Configured Flag Register 0x00000000 Port Status Control 0xEC20_0054 R W Specifies the Port Status and Contr...

Page 871: ...lkHeadED 0xEC30_0028 R W Specifies the USB Host Controller Bulk Head ED Register 0x0000_0000 HcBulkCurrentED 0xEC30_002C R W Specifies the USB Host Controller Bulk Current ED Register 0x0000_0000 HcDoneHead 0xEC30_0030 R Specifies the USB Host Controller Done Head Register 0x0000_0000 HcRmInterval 0xEC30_0034 R W Specifies the USB Host Controller FmInterval Register 0x0000_2EDF HcFmRemaining 0xEC3...

Page 872: ...ength burst INCR 16 Forces AHB master to start INCR4 8 16 bursts only on burst boundaries AHB requires that double word width burst be addressed aligned only the double word boundary 1 b1 Start INCRX burst only on burst x aligned addresses 1 b0 Normal AHB operation start bursts on any double word boundary 15 When the OHCI clocks are suspended the system has to assert this signal to start the clock...

Page 873: ...ed to disconnect the data fetch if the threshold amount of space is not available in the Packet Buffer The IN threshold is used to start the memory transfer as soon as the IN threshold amount of data is available in the Packet Buffer It is also used to disconnect the data write if the threshold amount of data is not available in the Packet Buffer For INCRX configurations the minimum threshold amou...

Page 874: ...ks to be added to the Transmit to Transmit turnaround delay value maintained in the core The default value of this register field is 0 9 Periodic Frame List Fetch Setting this bit will force the host controller to fetch the periodic frame list in every microframe of a frame 8 1 Time Available Offset This value indicates the additional number of bytes to be accommodated for the time available calcu...

Page 875: ...is deasserted when run stop is reset by software but the hchalted bit is not yet set 1 b1 Disables the automatic feature which takes all ports out of suspend when software clears the run stop bit This is for backward compatibility 4 1 b0 Enables NAK reload fix 1 b1 Disables NAK reload fix Reset value is 1 b0 Attribute is R W Reserved 3 2 1 b1 Scales down port enumeration time 1 1 b1 Makes the HCCP...

Page 876: ...e RO 4 3 2 7 AHB Error Status INSNREG06 R W Address 0xEC20_00A8 INSNREG05 Bit Description Initial State 31 AHB Error Captured Indicator that an AHB error was encountered and values were captured To clear this field the application must write a 0 to it 0x00000000 Reserved 30 12 11 9 HBURST value of the control phase at which the AHB error occurred 8 4 Number of beats expected in the burst at which ...

Page 877: ...FEATURES OF USB2 0 HS OTG The USB2 0 HS OTG features include Complies with the On The Go Supplement to the USB 2 0 Specification Revision 1 0a Operates in High Speed 480 Mbps Full Speed 12 Mbps and Low Speed 1 5 Mbps Host only modes Supports UTMI Level 3 interface Revision 1 0 Supports Session Request Protocol SRP and Host Negotiation Protocol HNP Supports only 32 bit data on the AHB 1 Control End...

Page 878: ...ontroller is composed of two independent blocks namely USB 2 0 OTG and USB PHY Controller Each of these blocks has an AHB Slave interface that provides the microcontroller with read and write access to the Control and Status Registers CSRs The OTG Link has an AHB Master to enable the link to transfer data on the AHB ...

Page 879: ...B The AHB master uses programmed DMA address HCDMAn register in Host mode and DIEPDMAn DOEPDMAn register in Device mode to access the data buffers 5 4 2 SLAVE MODE USB OTG can operate in either transaction level or pipelined transaction level The application handles one data packet at a time per channel endpoint in transaction level operations In pipelined transaction level operation the applicati...

Page 880: ... 1 Enables This bit must be set before USB PHY0 is used R W 1 b0 The USB_CONTROL register based on the address E010_E80Ch is guided to be set differently depending on the following system operation mode 5 5 1 NORMAL MODE Reset Value of ENABLE is 1 b0 To start USB transaction set this value to 1 b1 In Normal Mode power to USB PHY is switched off if USB OTG function is not used 5 5 2 STOP DEEP STOP ...

Page 881: ...ific Registers Device Mode Registers Device Global Registers Device Endpoint Specific Registers The Core Global and Host Port control and status registers are accessed in both Host and Device modes If the OTG Link operates in either Device or Host mode the application must not access registers from other modes If an unauthorized access occurs a Mode Mismatch interrupt is generated and value is ref...

Page 882: ...ice EP 0 Host Channel 0 FIFO CSR Device EP 1 Host Channel 1 FIFO CSR Device EP 14 Host Channel 14 FIFO CSR Device EP 15 Host Channel 15 FIFO CSR OTG LINK BASE 000h OTG LINK BASE 0400h OTG LINK BASE 0800h OTG LINK BASE 0E00h OTG LINK BASE 1000h OTG LINK BASE 2000h OTG LINK BASE 3000h OTG LINK BASE 0F000h OTG LINK BASE 10000h OTG LINK BASE 11000h NOTE Device Ep n Host Channel n FIFO data can be acce...

Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...

Page 884: ...FO_DEPTH OTG_TX_DINEP_DFIFP_DEPTH_0 DIEPTXF_1 31 16 OTG_TX_DINEP_DFIFO_DEPTH_1 DEIPTXF_2 15 0 DIEPTXF_1 15 0 OTG_TX_DINEP_DFIFO_DEPTH_1 DIEPTXF_2 31 16 OTG_TX_DINEP_DFIFO_DEPTH_2 NOTE When the device is operating in non Scatter Gather Internal DMA mode the last locations of the SPRAM are used to store the DMAADDR values of each Endpoint 1 Location per Endpoint When the device is operating in Scatt...

Page 885: ...ead and written by the application Read and Write set to 1 b1 by the core on certain USB events Self Set and cleared to 1 b0 by the core Self Clear Read Self set and Write Clear R SS_WC Register field is read by the application Read set to 1 b1 by the core on certain internal or USB or AHB event Self Set and cleared to 1 b0 by the application with a register write of 1 b1 Write Clear A register wr...

Page 886: ...e XuotgDM Dedicated XusbXTI Input Crystal Oscillator XI XusbXTI Dedicated XusbXTO Output Crystal Oscillator XO XusbXTO Dedicated XuotgREXT Input Output Connection to the External 44 2Ω 1 register XuotgREXT Dedicated XuotgVBUS Input Output USB mini Receptacle VBUS XuotgVBUS Dedicated XuotgID Input USB mini Receptacle Identifier XuotgID Dedicated XuotgDRVVBUS Output Off Chip Charge Pump Enable Xuotg...

Page 887: ...errupt Register 0x0400_0020 GINTMSK 0xEC00_0018 R W Specifies the Core Interrupt Mask Register 0x0000_0000 GRXSTSR 0xEC00_001C R Specifies the Receive Status Debug Read Register GRXSTSP 0xEC00_0020 R Specifies the Receive Status Read Pop Register GRXFSIZ 0xEC00_0024 R W Specifies the Receive FIFO Size Register 0x0000_1F00 GNPTXFSIZ 0xEC00_0028 R W Specifies the Non Periodic Transmit FIFO Size Regi...

Page 888: ...gisters HCFG 0xEC00_0400 R W Specifies the Host Configuration Register 0x0020_0000 HFIR 0xEC00_0404 R W Specifies the Host Frame Interval Register 0x0000_0B8F HFNUM 0xEC00_0408 R Specifies the Host Frame Number Frame Time Remaining Register 0x0000_0000 HPTXSTS 0xEC00_0410 R Specifies the Host Periodic Transmit FIFO Queue Status Register 0x0008_0300 HAINT 0xEC00_0414 R Specifies the Host All Channe...

Page 889: ...fies the Host Channel 2 Transfer Size Register 0x0000_0000 HCDMA2 0xEC00_0554 R W Specifies the Host Channel 2 DMA Address Register 0x0000_0000 HCCHAR3 0xEC00_0560 R W Specifies the Host Channel 3 Characteristics Register 0x0000_0000 HCSPLT3 0xEC00_0564 R W Specifies the Host Channel 3 Spilt Control Register 0x0000_0000 HCINT3 0xEC00_0568 R W Specifies the Host Channel 3 Interrupt Register 0x0000_...

Page 890: ...r 0x0000_0000 HCDMA6 0xEC00_05D4 R W Specifies the Host Channel 6 DMA Address Register 0x0000_0000 HCCHAR7 0xEC00_05E0 R W Specifies the Host Channel 7 Characteristics Register 0x0000_0000 HCSPLT7 0xEC00_05E4 R W Specifies the Host Channel 7 Spilt Control Register 0x0000_0000 HCINT7 0xEC00_05E8 R W Specifies the Host Channel 7 Interrupt Register 0x0000_0000 HCINTMSK7 0xEC00_05EC R W Specifies the ...

Page 891: ..._0000 HCDMA10 0xEC00_0654 R W Specifies the Host Channel 10 DMA Address Register 0x0000_0000 HCCHAR11 0xEC00_0660 R W Specifies the Host Channel 11 Characteristics Register 0x0000_0000 HCSPLT11 0xEC00_0664 R W Specifies the Host Channel 11 Spilt Control Register 0x0000_0000 HCINT11 0xEC00_0668 R W Specifies the Host Channel 11 Interrupt Register 0x0000_0000 HCINTMSK11 0xEC00_066C R W Specifies the...

Page 892: ...HCTSIZ14 0xEC00_06D0 R W Specifies the Host Channel 14 Transfer Size Register 0x0000_0000 HCDMA14 0xEC00_06D4 R W Specifies the Host Channel 14 DMA Address Register 0x0000_0000 HCCHAR15 0xEC00_06E0 R W Specifies the Host Channel 15 Characteristics Register 0x0000_0000 HCSPLT15 0xEC00_06E4 R W Specifies the Host Channel 15 Spilt Control Register 0x0000_0000 HCINT15 0xEC00_06E8 R W Specifies the Hos...

Page 893: ...ecifies the Device IN Endpoint 0 DMA Address Register 0x0000_0000 DTXFSTS0 0xEC00_0918 R Specifies the Device IN Endpoint Transmit FIFO Status Register 0x0000_0100 DIEPDMAB0 0xEC00_091C R Specifies the Device IN Endpoint 0 DMA Buffer Address Register 0x0000_0000 DIEPCTL1 0xEC00_0920 R W Specifies the Device Control IN Endpoint 1 Control Register 0x0000_0000 DIEPINT1 0xEC00_0928 R W Specifies the D...

Page 894: ...000_0000 DIEPINT4 0xEC00_0988 R W Specifies the Device IN Endpoint 4 Interrupt Register 0x0000_0080 DIEPTSIZ4 0xEC00_0990 R W Specifies the Device IN Endpoint 4 Transfer Size Register 0x0000_0000 DIEPDMA4 0xEC00_0994 R W Specifies the Device IN Endpoint 4 DMA Address Register 0x0000_0000 DTXFSTS4 0xEC00_0998 R Specifies the Device IN Endpoint Transmit FIFO Status Register 0x0000_0100 DIEPDMAB4 0xE...

Page 895: ...0 DTXFSTS7 0xEC00_09F8 R Specifies the Device IN Endpoint Transmit FIFO Status Register 0x0000_0100 DIEPDMAB7 0xEC00_09FC R Specifies the Device IN Endpoint 7 DMA Buffer Address Register 0x0000_0000 DIEPCTL8 0xEC00_0A00 R W Specifies the Device Control IN Endpoint 8 Control Register 0x0000_0000 DIEPINT8 0xEC00_0A08 R W Specifies the Device IN Endpoint 8 Interrupt Register 0x0000_0080 DIEPTSIZ8 0xE...

Page 896: ...000 DIEPINT11 0xEC00_0A68 R W Specifies the Device IN Endpoint 11 Interrupt Register 0x0000_0080 DIEPTSIZ11 0xEC00_0A70 R W Specifies the Device IN Endpoint 11 Transfer Size Register 0x0000_0000 DIEPDMA11 0xEC00_0A74 R W Specifies the Device IN Endpoint 11 DMA Address Register 0x0000_0000 DTXFSTS11 0xEC00_0A78 R Specifies the Device IN Endpoint Transmit FIFO Status Register 0x0000_0100 DIEPDMAB11 ...

Page 897: ...000_0000 DTXFSTS14 0xEC00_0AD8 R Specifies the Device IN Endpoint Transmit FIFO Status Register 0x0000_0100 DIEPDMAB14 0xEC00_0ADC R Specifies the Device IN Endpoint 14 DMA Buffer Address Register 0x0000_0000 DIEPCTL15 0xEC00_0AE0 R W Specifies the Device Control IN Endpoint 15 Control Register 0x0000_0000 DIEPINT15 0xEC00_0AE8 R W Specifies the Device IN Endpoint 15 Interrupt Register 0x0000_0080...

Page 898: ...TSIZ2 0xEC00_0B50 R W Specifies the Device OUT Endpoint 2 Transfer Size Register 0x0000_0000 DOEPDMA2 0xEC00_0B54 R W Specifies the Device OUT Endpoint 2 DMA Address Register 0x0000_0000 DOEPDMAB2 0xEC00_0B5C R Specifies the Device OUT Endpoint 2 DMA Buffer Address Register 0x0000_0000 DOEPCTL3 0xEC00_0B60 R W Specifies the Device Control OUT Endpoint 3 Control Register 0x0000_0000 DOEPINT3 0xEC00...

Page 899: ...MA6 0xEC00_0BD4 R W Specifies the Device OUT Endpoint 6 DMA Address Register 0x0000_0000 DOEPDMAB6 0xEC00_0BDC R Specifies the Device OUT Endpoint 6 DMA Buffer Address Register 0x0000_0000 DOEPCTL7 0xEC00_0BE0 R W Specifies the Device Control OUT Endpoint 7 Control Register 0x0000_0000 DOEPINT7 0xEC00_0BE8 R W Specifies the Device OUT Endpoint 7 Interrupt Register 0x0000_0000 DOEPTSIZ7 0xEC00_0BF0...

Page 900: ..._0C5C R Specifies the Device OUT Endpoint 10 DMA Buffer Address Register 0x0000_0000 DOEPCTL11 0xEC00_0C60 R W Specifies the Device Control OUT Endpoint 11 Control Register 0x0000_0000 DOEPINT11 0xEC00_0C68 R W Specifies the Device OUT Endpoint 11 Interrupt Register 0x0000_0000 DOEPTSIZ11 0xEC00_0C70 R W Specifies the Device OUT Endpoint 11 Transfer Size Register 0x0000_0000 DOEPDMA11 0xEC00_0C74 ...

Page 901: ...Z14 0xEC00_0CD0 R W Specifies the Device OUT Endpoint 14 Transfer Size Register 0x0000_0000 DOEPDMA14 0xEC00_0CD4 R W Specifies the Device OUT Endpoint 14 DMA Address Register 0x0000_0000 DOEPDMAB14 0xEC00_0CDC R Specifies the Device OUT Endpoint 14 DMA Buffer Address Register 0x0000_0000 DOEPCTL15 0xEC00_0CE0 R W Specifies the Device Control OUT Endpoint 15 Control Register 0x0000_0000 DOEPINT15 ...

Page 902: ... Apply Suspend signal to save power 1 b0 Disables Normal Operation 1 b1 Enables R W 1 b1 Reserved 5 Reserved but should be 0x1 1 b1 otg_disable_0 4 USBPHY0 OTG block power down 1 b0 OTG block power up 1 b1 OTG block power down If the application does not use OTG functionality you can set this input high to save power 1 b1 Analog _powerdown_0 3 USBPHY0 Analog block power down 1 b0 Analog block powe...

Page 903: ...de R W 1 b0 Reserved 6 5 common_on_n0 4 USBPHY0 Force XO Bias Bandgap and PLL to Remain Powered During a Suspend This bit controls the power down signals of sub blocks in the Common block if the USB PHY0 is suspended 1 b0 48MHz clock on clk48m_ohci is available at all times except in Suspend mode 1 b1 48MHz clock on clk48m_ohci is available at all times even in Suspend mode R W 1 b0 Reserved 3 1 b...

Page 904: ...host_sw_rst 4 USB Host LINK S W Reset R W 1 b0 phy_sw_rst1 3 USB PHY1 USB Host LINK S W Reset The phy1_sw_rst signal must by asserted for at least 10us R W 1 b1 phylnk_sw_rst 2 OTG Link Core phy_clock domain S W Reset R W 1 b0 link_sw_rst 1 OTG Link Core hclk domain S W Reset R W 1 b0 phy_sw_rst0 0 USBPHY0 LINK 2 0 S W Reset The phy_sw_rst0 signal must be asserted for at least 10us R W 1 b1 ...

Page 905: ... R W Initial State Reserved 31 21 11 h0 Reserved 20 17 Reserved but should be 4 b0100 4 b0100 Otgtune 16 14 VBUS Valid Threshold Adjustment This bit adjusts the voltage level for the VBUS Valid threshold in USBPHY n 111 Reserved 110 Reserved 101 Reserved 100 Design default 011 Reserved 010 Reserved 001 Reserved 000 6 R W 3 b100 Reserved 13 0 Reserved but should be 0x19B3 14 h19B3 ...

Page 906: ...nce Time Indicates the Debounce time of a detected connection 1 b0 Long Debounce time used for physical connections 1 b1 Short Debounce time used for soft connections R 1 b0 ConIDSts 16 Connector ID Status Indicates the connector ID status 1 b0 The OTG core is in A device mode 1 b1 The OTG core is in B device mode R 1 b1 Reserved 15 12 4 h0 DevHNPEn 11 Device HNP Enable The application sets the bi...

Page 907: ...negotiation failure 1 b1 Host negotiation success R 1 b0 Reserved 7 2 6 h0 SesReq 1 Session Request The application sets this bit to initiate a session request on the USB The core clears this bit if the HstNegSucStsChng bit is cleared 1 b0 No session request 1 b1 Session request R W 1 b0 SesReqScs 0 Session Request Success The core sets this bit if a session request initiation is successful 1 b0 S...

Page 908: ... Device Timeout Change The core sets this bit to indicate that the A device has timed out while waiting for the B device to connect R_SS_ WC 1 b0 HstNegDet 17 Host Negotiation Detected The core sets this bit if it detects a host negotiation request on the USB R_SS_ WC 1 b0 Reserved 16 10 7 h0 HstnegSuc StsChng 9 Host Negotiation Success Status Change The core sets this bit on the success or failur...

Page 909: ...he Periodic TxFIFO is completely empty R W 1 b0 NPTxFEmp Lvl 7 Non Periodic TxFIFO Empty Level This bit is used only in Slave mode This bit indicates when IN endpoint Transmit FIFO empty interrupt DIEPINTn TxFEmp is triggered 1 b0 DIEPINTn TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty 1 b1 DIEPINTn TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty R ...

Page 910: ...e Host Mode After setting the force bit the application must wait at least 25 ms before the change to take effect R W 1 b0 Reserved 28 14 15 h0 USBTrdTim 13 10 USB Turnaround Time Sets the turnaround time in PHY clocks Specifies the response time for a MAC request to the Packet FIFO Controller PFC to fetch data from the DFIFO SPRAM This must be programmed to 4 h5 When the MAC interface is 16 bit U...

Page 911: ...3 PHY Interface The application uses this bit to configure the core to support a UTMI PHY with an 8 or 16 bit interface Only 16 bit interface is supported This bit must be set to 1 1 b0 8 bits 1 b1 16 bits R W 1 b1 TOutCal 2 0 HS FS Timeout Calibration Set this bit to 3 h7 R W 3 h0 ...

Page 912: ...ransmit FIFOs but cannot flush if the core is in the middle of a transaction The application must only write this bit after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO The application must wait until the core clears this bit before performing any operations This bit takes 8 clocks to clear R_WS _SC 1 b0 RxFFlsh 4 RxFIFO Flush The application flushes the enti...

Page 913: ...ll the CSR registers except the following register bits HCFG FSLSPclkSel DCFG DevSpd All module state machines except the AHB Slave Unit are reset to the IDLE state and all the transmit FIFOs and the receive FIFO are flushed Any transactions on the AHB Master are terminated as soon as possible after gracefully completing the last data phase of an AHB transfer Any transactions on the USB are termin...

Page 914: ...ction with a non ERRORed response The interrupt is asserted in Host mode when the device responds to an LPM token with a non ERRORed response or when the host core has completed LPM transactions for the programmed number of times GLPMCFG RetryCnt This field is valid only if OTG_ENABLE_LPM is set to 1 and the Global Core LPM Configuration register s LPM Capable LPMCap field is set to 1 R_SS _WC 1 b...

Page 915: ...non periodic IN NAK handshake Disables In endpoints Flushes the FIFO Determines the token sequence from the IN Token Sequence Learning Queue Re enables the endpoints Clears the global non periodic IN NAK handshake If the global non periodic IN NAK is cleared the core has not yet fetched data for the IN endpoint and the IN token received the core generates an IN token received when FIFO empty inter...

Page 916: ... that an interrupt is pending on one of the IN endpoints of the core in Device mode The application must read the Device All Endpoints Interrupt DAINT register to determine the exact number of the IN endpoint on which the interrupt occurred and then read the corresponding Device IN Endpoint n Interrupt DIEPINTn register to determine the exact cause of the interrupt The application must clear the a...

Page 917: ... Clear Global Non periodic IN NAK bit in the Device Control register DCTL CGNPInNak This interrupt does not necessarily mean that a NAK handshake is sent out on the USB The STALL bit takes precedence over the NAK bit R 1 b0 NPTxFEmp 5 Non periodic TxFIFO Empty This interrupt is valid only when OTG_EN_DED_TX_FIFO 0 This interrupt is asserted when the Non periodic TxFIFO is either half or completely...

Page 918: ... this interrupt The application must clear the appropriate status bit in the GOTGINT register to clear this bit R 1 b0 ModeMis 1 Mode Mismatch Interrupt The core sets this bit if the application is trying to access A Host mode register if the core is operating in Device mode A Device mode register if the core is operating in Host mode R_SS _WC 1 b0 CurMod 0 Current Mode Of Operation Indicates the ...

Page 919: ...ask R W 1 b0 PrtIntMsk 24 Host Port Interrupt Mask R W 1 b0 ResetDetMsk 23 Reset Detected Interrupt Mask R W 1 b0 FetSuspMsk 22 Data Fetch Suspended Mask R W 1 b0 Incomplete Periodic Transfer Mask R W incomplPMsk incompISOOUTMsk 21 Incomplete Isochronous OUT Transfer Mask 1 b0 incompISOINMsk 20 Incomplete Isochronous IN Transfer Mask R W 1 b0 OEPIntMsk 19 OUT Endpoints Interrupt Mask R W 1 b0 INEP...

Page 920: ...ister returns the contents of the top of the Receive FIFO A read to the Receive Status Read and Pop register additionally pops the top data entry out of the RxFIFO The receive status contents must be interpreted differently in Host and Device modes The core ignores the receive status pop read if the receive FIFO is empty and returns a value of 32 h0000_0000 The application must only pop the Receiv...

Page 921: ...t 4 b0010 IN data packet received 4 b0011 IN transfer completed triggers an interrupt 4 b0101 Data toggle error triggers an interrupt 4 b0111 Channel halted triggers an interrupt others Reserved R DPID 16 15 Data PID Indicates the Data PID of the received packet 2 b00 DATA0 2 b10 DATA1 2 b01 DATA2 2 b11 MDATA R BCnt 14 4 Byte Count Indicates the byte count of the received IN data packet R ChNum 3 ...

Page 922: ... b0110 SETUP data packet received others Reserved R 4 b1111 DPID 16 15 Data PID Indicates the Data PID of the received OUT data packet 2 b00 DATA0 2 b10 DATA1 2 b01 DATA2 2 b11 MDATA R 2 b11 BCnt 14 4 Byte Count Indicates the byte count of the received data packet R 11 h3FF EPNum 3 0 Endpoint number Indicates the endpoint number to which the current received packet belongs R 4 hF 5 8 3 11 Receive ...

Page 923: ...is field Programmed values must not exceed the power on value set INEPTxF0Dep 31 16 IN Endpoint TxFIFO 0 Depth For Device mode This value is in terms of 32 bit words Minimum value is 16 Maximum value is 7936 R W 16 h1F00 NPTxFStAddr Non Periodic Transmit Start Address For host mode This field contains the memory start address for Non Periodic Transmit FIFO RAM The power on reset value of this regi...

Page 924: ...alt command Bit 24 Terminate last entry for selected channel endpoint R 7 h0 NPTxQSpcAvail 23 16 Non Periodic Transmit Request Queue Space Available Indicates the amount of free space available in the Non Periodic Transmit Request Queue This queue holds both IN and OUT requests in Host mode Device mode has only IN requests 8 h0 Non Periodic Transmit Request Queue is full 8 h1 1 location available ...

Page 925: ...ce Based on the LPM channel index the core automatically inserts the device address and endpoint number programmed in the corresponding channel into the LPM transaction R W 4 b0 L1ResumeOK 16 Indicates that the application or host can start a resume from the Sleep state This bit is valid in the LPM Sleep L1 state It is set in Sleep mode after a delay of 50 μs TL1Residency The bit is reset when Slp...

Page 926: ...00 ERROR No handshake response CoreL1Res 14 13 Device Mode The core s response to the received LPM transaction is reflected in these two bits R 2 b0 HIRD_Thres 12 8 Host Mode The core asserts L1SuspendM to put the PHY into Deep Low Power mode in L1 when HIRD_Thres 4 is set to 1 b1 HIRD_Thres 3 0 specifies the time for which resume signaling is to be reflected by the host TL1HubDrvResume2 on the US...

Page 927: ...vice application software The response depends on GLPMCFG LPMCap If GLPMCFG LPMCap is 1 b0 the core always responds with a NYET If GLPMCFG LPMCap is 1 b1 the core responds as follows 1 ACK Even though an ACK is pre programmed the core responds with an ACK only on a successful LPM transaction The LPM transaction is successful if There are no PID CRC5 errors in both the EXT token and the LPM token e...

Page 928: ...e IN Endpoint Transmit FIFO n Size Register DIEPTXFn R W Address 0xEC00_0104 n 1 04h FIFO_number 1 n 15 This register holds the memory start address of IN endpoint TxFIFOs to implement in Device mode Each FIFO holds the data for one IN endpoint FIFOs This register is repeated for IN endpoint FIFO instantiated DIEPTXFn Bit Description R W Initial State INEPnTxFDep 31 16 IN Endpoint TxFIFO Depth INE...

Page 929: ...t Description R W Initial State Reserved 31 3 29 h0040000 FSLSSupp 2 FS and LS Only Support The application uses this bit to control the core s enumeration speed Using this bit the application makes the core enumerate as a FS host even if the connected device supports HS traffic Do not make changes to this field after initial programming 1 b0 HS FS LS based on the maximum speed supported by the co...

Page 930: ...s programmed the core calculates the value based on the PHY clock specified in the FS LS PHY Clock Select field of the Host Configuration register HCFG FSLSPclkSel Do not change the value of this field after the initial configuration 125 μs PHY clock frequency for HS 1 ms PHY clock frequency for FS LS R W 16 h0B8F 5 8 4 3 Host Frame Number Frame Time Remaining Register HFNUM R Address 0xEC00_0408 ...

Page 931: ...ber Bits 26 25 Type 2 b00 IN OUT 2 b01 Zero length packet 2 b10 CSPLIT 2 b11 Disable channel command Bit 24 Terminate R 8 h0 PTxQSpcAvail 23 16 Periodic Transmit Request Queue Space Available Indicates the number of free locations available to be written in the Periodic Transmit Request Queue This queue holds both IN and OUT requests 8 h0 Periodic Transmit Request Queue is full 8 h1 1 location ava...

Page 932: ...r HAINT Bit Description R W Initial State Reserved 31 16 16 h0 HAINT 15 0 Channel Interrupts One bit per channel Bit 0 for Channel 0 bit 15 for Channel 15 R 16 h0 5 8 4 6 Host All Channels Interrupt Mask Register HAINTMSK R W Address 0xEC00_0418 The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt the application if an event occurs on a chann...

Page 933: ...1 19 13 h0 PrtSpd 18 17 Port Speed Indicates the speed of the device attached to this port 2 b00 High speed 2 b01 Full speed 2 b10 Low speed 2 b11 Reserved R 2 b0 PrtTstCtl 16 13 Port Test Control The application writes a nonzero value to this field to put the port into a Test mode and the corresponding pattern is signaled on the port 4 b0000 Test mode disabled 4 b0001 Test_J mode 4 b0010 Test_K m...

Page 934: ...a remote wakeup signal is detected or the application sets the Port Reset bit or Port Resume bit in this register or the Resume Remote Wakeup Detected Interrupt bit or Disconnect Detected Interrupt bit in the Core Interrupt register 1 b0 Port not in Suspend mode 1 b1 Port in Suspend mode R_WS _SC 1 b0 PrtRes 6 Port Resume The application sets this bit to drive resume signaling on the port The core...

Page 935: ...application cannot set this bit by a register write It clears it to disable the port This bit does not trigger any interrupt to the application 1 b0 Port disabled 1 b1 Port enabled R_SS_ SC_ WC 1 b0 PrtConn Det 1 Port Connect Detected The core sets this bit if a device connection is detected to trigger an interrupt to the application using the Host Port Interrupt bit of the Core Interrupt register...

Page 936: ...ctions 1 b0 Even micro frame 1 b1 Odd micro frame R W 1 b0 DevAddr 28 22 Device Address This field selects the specific device serving as the data source or sink R W 7 h0 MC EC 21 20 Multi Count Error Count If the Split Enable bit of the Host Channel n Split Control register is reset 1 b0 this field indicates to the host the number of transactions that must be executed per microframe for this endp...

Page 937: ...at this channel is enabled to perform split transactions R W 1 b0 Reserved 30 17 14 h0 CompSplt 16 Do Complete Split The application sets this field to request the OTG host to perform a complete split transaction R W 1 b0 XactPos 15 14 Transaction Position This field is used to determine whether to send all first middle or last payloads with each OUT transaction 2 b11 All This is the entire data p...

Page 938: ...ial State Reserved 31 11 21 h0 DataTglErr 10 Data Toggle Error R_SS_WC 1 b0 FrmOvrun 9 Frame Overrun R_SS_WC 1 b0 BblErr 8 Babble Error R_SS_WC 1 b0 XactErr 7 Transaction Error R_SS_WC 1 b0 NYET 6 NYET Response Received Interrupt R_SS_WC 1 b0 ACK 5 ACK Response Received Interrupt R_SS_WC 1 b0 NAK 4 NAK Response Received Interrupt R_SS_WC 1 b0 STALL 3 STALL Response Received Interrupt R_SS_WC 1 b0 ...

Page 939: ... 21 h0 DataTglErrMsk 10 Data Toggle Error Mask R W 1 b0 FrmOvrunMsk 9 Frame Overrun Mask R W 1 b0 BblErrMsk 8 Babble Error Mask R W 1 b0 XactErrMsk 7 Transaction Error Mask R W 1 b0 NyetMsk 6 NYET Response Received Interrupt Mask R W 1 b0 AckMsk 5 ACK Response Received Interrupt Mask R W 1 b0 NakMsk 4 NAK Response Received Interrupt Mask R W 1 b0 StallMsk 3 STALL Response Received Interrupt Mask R...

Page 940: ...ication is interrupted to indicate normal completion R W 10 b0 XferSize 18 0 Transfer Size For an OUT this field is the number of data bytes the host sends during the transfer For an IN this field is the buffer size that the application has reserved for the transfer The application is expected to program this field as an integer multiple of the maximum packet size for IN transactions R W 19 b0 NOT...

Page 941: ...Int vl 25 24 Periodic Scheduling Interval PerSchIntvl must be programmed only for Scatter Gather DMA mode This field specifies the amount of time the Internal DMA engine must allocate for fetching periodic IN endpoint data Based on the number of periodic endpoints this value must be specified as 25 50 or 75 of micro frame When any periodic endpoints are active the internal DMA engine allocates the...

Page 942: ...ction of a control transfer s Status stage 1 b0 Sends a STALL handshake on a nonzero length status OUT transaction and do not send the received OUT packet to the application 1 b1 Sends the received OUT packet to the application and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register R W 1 b0 DevSpd 1 0 Device Speed Indicates the speed at which ...

Page 943: ...s bit is enabled the packets are not flushed when a ISOC IN token is received for an elapsed frame R W 1 b0 GMC 14 13 Global Multi Count GMC must be programmed only once after initialization Applicable only for Scatter Gather DMA mode This indicates the number of packets to be serviced for that end point before moving to the next end point It is only for non periodic end points 2 b00 Invalid 2 b01...

Page 944: ... is written to the RxFIFO irrespective of space availability Sends a NAK handshake on all packets except on SETUP transactions All isochronous OUT packets are dropped R 1 b0 GNPINNakSts 2 Global Non Periodic IN NAK Status 1 b0 A handshake is sent based on the data availability in the transmit FIFO 1 b1 A NAK handshake is sent out on all non periodic IN endpoints irrespective of the data availabili...

Page 945: ...e following table lists the minimum duration under various conditions for which the SoftDisconnect bit must be set for the USB host to detect a device disconnect To accommodate clock jitter it is recommended that the application add some extra delay to the specified minimum duration Operating Speed Device state Minimum Duration High speed Suspended 1ms 2 5μs High speed Idle 3ms 2 μs High speed Not...

Page 946: ...to the application with Early Suspend bit of the Core Interrupt register If the early suspend is asserted due to an erratic error the application performs a soft disconnect recover R 1 b0 EnumSpd 2 1 Enumerated Speed Indicates the speed at which the OTG core has come up after speed detection through a chirp sequence 2 b00 High speed PHY clock is 30 MHz 2 b01 Full speed PHY clock is 30 MHz 2 b10 Lo...

Page 947: ...register Status bits are masked by default Mask interrupt 1 b0 Unmask interrupt 1 b1 DIEPMSK Bit Description R W Initial State Reserved 31 10 22 h0 BNAInIntrMsk 9 BNA interrupt Mask R W 1 b0 TxfifoUndrnMsk 8 Fifo Underrun Mask R W 1 b0 Reserved 7 1 b0 INEPNakEffMsk 6 IN Endpoint NAK Effective Mask R W 1 b0 Reserved 5 1 b0 INTknTXFEmpMsk 4 IN Token received with TxFIFO Empty mask R W 1 b0 TimeOUTMs...

Page 948: ... to control endpoints only R W 1 b0 AHBErrMsk 2 AHB Error R W 1 b0 EPDisbldMsk 1 Endpoint Disabled Interrupt Mask R W 1 b0 XferComplMsk 0 Transfer Completed Interrupt Mask R W 1 b0 5 8 7 6 Device ALL Endpoints Interrupt Register DAINT R Address 0xEC00_0818 If a significant event occurs on an endpoint a Device All Endpoints Interrupt register interrupts the application using the Device OUT Endpoint...

Page 949: ...ts One bit per IN endpoint Bit 0 for IN EP 0 bit 15 for IN EP 15 R W 16 h0 5 8 7 8 Device VBUS Discharge Time Register DVBUSDIS R W Address 0xEC00_0828 This register specifies the VBUS discharge time after VBUS pulsing during SRP DVBUSDIS Bit Description R W Initial State Reserved 31 16 16 h0 DVBUSDis 15 0 Device VBUS Discharge Time Specifies the VBUS discharge time after VBUS pulsing during SRP T...

Page 950: ...eceive direction R W 1 b0 Reserved 15 13 AHBThrRatio 12 11 AHB Threshold Ratio AHBThrRatio These bits define the ratio between the AHB threshold and the MAC threshold for the transmit path only The AHB threshold always remains less than or equal to the USB threshold because this does not increase overhead Both the AHB and the MAC threshold must be DWORD aligned If the AHB threshold value is not DW...

Page 951: ...s the programmed AHB Burst Length GAHBCFG HBstLen ISOThrEn 1 ISO IN Endpoints Threshold Enable When this bit is set the core enables thresholding for isochronous IN endpoints R W 1 b0 NonISOThrEn 0 Non ISO IN Endpoints Threshold Enable When this bit is set the core enables thresholding for Non Isochronous IN endpoints R W 1 b0 ...

Page 952: ...Interrupt Mask Bits These bits acts as mask bits for DIEPINTn TxFEmp interrupt One bit per IN Endpoint Bit 0 for IN EP 0 bit 15 for IN EP 15 R W 16 h0 5 8 7 12 Device Logical Endpoint Specific Registers A logical endpoint is unidirectional it is either IN or OUT To represent a bidirectional endpoint two logical endpoints are required one for the IN direction and the other for the OUT direction Thi...

Page 953: ...e core clears this bit before setting the Endpoint Disabled Interrupt The application must set this bit only if Endpoint Enable is already set for this endpoint R_WS_ SC 1 b0 Reserved 29 28 2 b0 SetNAK 27 Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit the application controls the transmission of NAK handshakes on an endpoint The core also sets this bit for an endpoint...

Page 954: ...ata available in the TxFIFO Irrespective of this bit s setting the core always responds to SETUP data packets with an ACK handshake R 1 b0 Reserved 16 1 b0 USBActEP 15 USB Active Endpoint This bit is always set to 1 indicating that control endpoint 0 is always active in all configurations and interfaces R 1 b1 Reserved 14 2 13 h0 MPS 1 0 Maximum Packet Size Applies to IN and OUT endpoints The appl...

Page 955: ...mory R_WS_ SC 1 b0 EPDis 30 Endpoint Disable The application cannot disable control OUT endpoint 0 R 1 b0 Reserved 29 28 2 b0 SetNAK 27 Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit the application controls the transmission of NAK handshakes on an endpoint The core sets this bit on a Transfer Completed interrupt or after a SETUP is received on the endpoint W 1 b0 CNA...

Page 956: ...the RxFIFO to accommodate the incoming packet Irrespective of this bit s setting the core always responds to SETUP data packets with an ACK handshake R 1 b0 Reserved 16 1 b0 USBActEP 15 USB Active Endpoint This bit is always set to 1 indicating that a control endpoint 0 is always active in all configurations and interfaces R 1 b1 Reserved 14 2 13 h0 MPS 1 0 Maximum Packet Size The maximum packet s...

Page 957: ...sfer Completed Note For control endpoints in DMA mode this bit must be set to be able to transfer SETUP data packets in memory R_WS _SC 1 b0 EPDis 30 Endpoint Disable Applies to IN and OUT endpoints The application sets this bit to stop transmitting receiving data on an endpoint even before the transfer for that endpoint is complete The application must wait for the Endpoint Disabled interrupt bef...

Page 958: ...mber These bits specify the FIFO number associated with this endpoint Each active IN endpoint must be programmed to a separate FIFO number This field is valid only for IN endpoints R W 4 h0 Stall 21 STALL Handshake Applies to non control non isochronous IN and OUT endpoints only The application sets this bit to stall all tokens from the USB host to this endpoint If a NAK bit Global Non periodic IN...

Page 959: ...am the PID of the first packet to be received or transmitted on this endpoint after the endpoint is activated The applications use the SetD1PID and SetD0PID fields of this register to program either DATA0 or DATA1 PID 1 b0 DATA0 1 b1 DATA1 This field is applicable both for Scatter Gather DMA mode and non Scatter Gather DMA mode R 1 b0 EO_FrNum Even Odd Micro Frame In non Scatter Gather DMA mode Ap...

Page 960: ...erface commands the application must program endpoint registers accordingly and set this bit Reserved 14 11 R W 4 h0 MPS 10 0 Maximum Packet Size Applies to IN and OUT endpoints The application must program this field with the maximum packet size for the current logical endpoint This value is in bytes R W 11 h0 ...

Page 961: ...e interrupt gets generated when a zero length packet is transmitted due to un availability of data in the TXFifo R_SS _WC 1 b0 BbleErrIntrpt 12 BbleErr Babble Error interrupt BbleErrIntrpt The core generates this interrupt when babble is received for the endpoint R_SS _WC 1 b0 Packet Dropped Status 11 PktDrpSts Packet Dropped Status This bit indicates to the application that an ISOC OUT packet has...

Page 962: ...ular endpoint For information about handling this interrupt R W INTknEPMis IN Token Received with EP Mismatch Applies to non periodic IN endpoints only Indicates that the data in the top of the non periodic TxFIFO belongs to an endpoint other than the one for which the IN token was received This interrupt is asserted on the endpoint for which the IN token was received StsPhseRcvd 5 Status Phase Re...

Page 963: ...BErr 2 AHB Error Applies to IN and OUT endpoints This is generated only in Internal DMA mode if there is an AHB error during an AHB read write The application reads the corresponding endpoint DMA address register to get the error address R_SS _WC 1 b0 EPDisbld 1 Endpoint Disabled Interrupt Applies to IN and OUT endpoints This bit indicates that the endpoint is disabled per the application s reques...

Page 964: ...the application reads this register when Scatter Gather DMA mode is enabled the core returns all zeros DIEPTSIZ0 Bit Description R W Initial State Reserved 31 21 11 h0 PktCnt 20 19 Packet Count Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0 This field is decremented every time a packet is read from the TxFIFO R W 2 b0 Reserved 18 7 12 h0 X...

Page 965: ...h0 Reserved 28 21 9 h0 PktCnt 20 19 Packet Count This field is decremented to zero after a packet is written into the RxFIFO R W 2 b0 Reserved 18 7 12 h0 XferSize 6 0 Transfer Size Indicates the transfer size in bytes for endpoint 0 The core interrupts the application only after it has exhausted the transfer size amount of data The transfer size can be set to the maximum packet size of the endpoin...

Page 966: ...tted per microframe on the USB The core uses this field to calculate the data PID for isochronous IN endpoints 2 b01 1 packet 2 b10 2 packets 2 b11 3 packets R W For non periodic IN endpoints this field is valid only in Internal DMA mode It specifies the number of packets the core must fetch for an IN endpoint before it switches to the endpoint pointed to by the Next Endpoint field of the Device E...

Page 967: ...e Endpoint n DMA Address DIEPDMAn DOEPDMAn R W Address 0xEC00_0914 n 20h 0xEC00_0B14 n 20h Endpoint_number 0 n 15 The starting DMA address must be DWORD aligned DIEPDMAn DOEPDMAn Bit Description R W Initial State DMAAddr 31 0 DMA Address Holds the start address of the external memory for storing or fetching endpoint data Note For control endpoints this field stores control OUT data packets as well...

Page 968: ...s full 16 h1 1 word available 16 h2 2 words available 16 hn n words available where 0 n 32 768 16 h8000 32 768 words available Others Reserved R 16 h100 5 8 7 22 Device Endpoint n DMA Buffer Address Register DIEPDMABn DOEPDMABn R W Address 0xEC00_091C n 20h 0xEC00_B1C n 20h Endpoint_number 0 n 15 These fields are present only in case of Scatter Gather DMA DIEPDMABn D OEPDMABn Bit Description R W I...

Page 969: ... in data buffer and then clears the interrupt In the same manner AP writes data in the data buffer and then asserts interrupt to modem chip to notify Modem Chip Modem Modem Chip Chip Mo MSM Modem I F SRAM I F Internal dual port SRAM buffer 2048 x 32 2 units 16KByte AP I F AHB Slave I F Modem Interface module Modem Interface module S5PC110 S5PC110 Interrupt Controller Interrupt Request to AP AHB bu...

Page 970: ...st 1 to MSMINTCLR register in MODEM IF 2 To Modem AP writes 1 to 0xED00_3FFC through internal chip AHB bus Modem chip writes 1 to the bits at 0x1FFE through ADR NOTE 1 There are two address views for MODEMIF namely MSM address ADR for MODEM chip and AHB address for S5PC110 AHB address is twice the size of ADR For example 0x3FFC at AHB bus is 0x1FFE at ADR helps you to understand it This is default...

Page 971: ...ot 8191 Slot 8190 16 bit data width ADR MODEM view AHB ARM view 0 1 2 1FFE 1FFF 0 MSBM 0xED000000 2 MSBM 0xED000002 4 MSBM 0xED000004 3FFC MSBM 0xED003FFC 3FFE MSBM 0xED003FFE Internal DPSRAM 2 byte 16 bit addressing 1 byte 8 bit addressing Figure 6 2 MODEM I F Address Mapping ...

Page 972: ...re 6 3 Modem Interface Write Timing Diagram Standard Mode Table 6 2 Modem Interface Write Timing Standard Mode Parameter Description Min ns Max ns Notes tAVWR Address valid to address invalid 16 ns tCSVWR Chip select active 16 ns tAWR Address valid to write active 4 ns tWR Write active 8 ns tDSUWR Write data setup 8 ns tDHWR Write data hold 4 ns ...

Page 973: ...tandard Mode Parameter Description Min ns Max ns Notes tAVRD Address valid to address invalid 50 ns tADH Address hold 0 ns tCSVRD Chip select active 50 ns tCSRD Chip select active to read active 14 ns tRD Read active 36 ns tRDDV Read active to data valid 35 ns tRDH Read data hold 6 ns tACSDV Address and chip select active to data valid 49 ns NOTE Output load is 30pF in room temperature 25 Degree ...

Page 974: ...e 6 4 Modem Interface Write Timing Address Muxed mode Parameter Description Min ns Max ns Notes tAVDS Address valid setup 15 ns tAVDH Address valid hold 5 ns tAV Address valid duration 15 ns tAVWR Address valid to write enable 0 ns tCSV Chip select duration 20 ns tWR Write enable duration 5 ns tDSWR Write data setup 8 ns tDHWR Write data hold 4 ns ...

Page 975: ...ress Muxed mode Parameter Description Min ns Max ns Notes tAVDS Address valid setup 15 ns tAVDH Address valid hold 5 ns tAV Address valid duration 15 ns tAVOE Address valid to read enable 5 ns tCSVOE Chip select duration Read mode 45 ns tOE Output enable Read Active to data valid 35 ns NOTE Output load is 30pF in room temperature 25 Degree ...

Page 976: ...n muxed ADVn Input Address Valid from MODEM Chip Only Address Muxed mode XmsmADVn muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals 6 7 SOFTWARE INTERFACE AND REGISTERS This modem interface provides a generic data exchange method This interface does not implement any other complex features except for the interrupt request clea...

Page 977: ..._8004 R W Specifies the Interrupt Request to MSM Modem Register 0x00003FFC MIFCON 0xED00_8008 R W Specifies the Modem Interface Control Register 0x00100008 MIFPCON 0xED00_800C R W Specifies the Modem Interface Port Control register 0x00000000 MSMINTCLR 0xED00_8010 W Specifies the MSM Modem Interface Pending Interrupt Request Clear DMA_TX_ADR 0xED00_8014 R W Specifies the DMA TX Request Address Reg...

Page 978: ...s this interrupt 0x3FFE 6 8 1 2 Interrupt Request to Modem Register INT2MSM R W Address 0xED00_8004 INT2MSM Bit Description Initial State Reserved 31 14 Reserved 0 INT2MSM_ADR 13 0 Modem interface in this module requests the interrupt to modem chip if AP writes this address and clears the interrupt if modem chip write 1 to the corresponding bit field 0x3FFC NOTE It is recommended that S5PC110 writ...

Page 979: ...DMA Controller 0 DMATXREQEN_0 16 Enables MSM Read DMA Request TX 0 to AP DMA Controller 0 Reserved 15 4 0 INT2MSMEN 3 Enables Interrupt to MSM Modem MSM_nIRQ is interrupt signal enable 0 Disables 1 Enables 1 INT2APEN 2 Enables MSM Modem write interrupt to AP 0 Disable s 1 Enables 0 Reserved 1 Reserved 0 Fixed 0 Fixed to 0 0 6 8 1 4 Modem Interface Port Control Register MIFPCON R W Address 0xED00_8...

Page 980: ...xED00_8014 INT2AP Bit Description Initial State Reserved 31 30 Reserved 0 DMA_TX_ADR_1 29 16 Modem interface requests the DMA to AP DMA Controller if modem chip reads this address Source DMA_MSM_Req 1 0x17FE Reserved 15 14 Reserved 0 DMA_TX_ADR_0 13 0 Modem interface requests the DMA to AP DMA Controller if modem chip reads this address Source DMA_MSM_Req 0 0x13FE 6 8 1 7 DMA Request RX Address Re...

Page 981: ...troller is a interface between system and SD MMC The performance of this host is very powerful as clock rate is 48 MHz and access 8 bit data pin simultaneously 7 2 KEY FEATURES OF SD MMC CONTROLLER The High Speed MMC controller supports SD Standard Host Specification Version 2 0 standard SD Memory Card Specification Version 2 0 High Speed MMC Specification Version 4 3 standard SDIO Card Specificat...

Page 982: ...LLER SFR SDCLK Domain HCLK Domain System Bus AHB CMD ARG Control Status AHB slave I F DMA controller AHB master FIFO DATA packet Status Control CMDRSP packet Status Control RSP Line Control Pad I F INTREQ BaseCLK Clock Control DPSRAM Control Figure 7 1 SDMMC Clock Domain ...

Page 983: ...tion Status Enable ENSTACARDNS in the Normal Interrupt Status Enable register Card Insertion Signal Enable ENSIGCARDNS in the Normal Interrupt Signal Enable register Card Removal Status Enable ENSTACARDREM in the Normal Interrupt Status Enable register Card Removal Signal Enable ENSIGCARDREM in the Normal Interrupt Signal Enable register 2 If Host Driver detects the card insertion or removal it cl...

Page 984: ...o a SD card 1 Calculate a divisor to determine SD Clock frequency for SD Clock by reading Base Clock Frequency Refer to clock control register 9 15 2 Set Internal Clock Enable ENINTCLK and SDCLK Frequency Select in the Clock Control register in accordance with the calculated result of step 1 3 Check Internal Clock Stable STBLINTCLK in the Clock Control register Repeat this step until Clock Stable ...

Page 985: ...k is shown in Figure 7 4 The Host Driver does not stop the SD Clock if a SD transaction takes place on the SD Bus namely either Command Inhibit DAT or Command Inhibit CMD in the Present State register is set to 1 1 Set SD Clock Enable ENSDCLK in the Clock Control register to 0 After ENSDCLK is set the Host Controller stops SD Clock ...

Page 986: ...e 7 5 SD Clock Frequency Change Sequence The sequence to change SD Clock frequency is shown in Figure 7 5 If SD Clock is still off skip step 1 The steps to change SD Clock frequency 1 Perform SD Clock Stop Sequence Refer to 7 4 2 SD Clock Supply Sequence 2 Perform SD Clock Supply Sequence Refer to 7 4 3 SD Clock Stop Sequence ...

Page 987: ...egulator optional with maximum voltage that the Host Controller supports 3 Set SD Bus Power PWRON in the Power Control register to 1 4 Get the OCR value of all function internal of SD card 5 Judge whether SD Bus voltage must be changed or not If SD Bus voltage must be changed continue with step 6 If SD Bus voltage is not to be changed go to End 6 Set SD Bus Power in the Power Control register to 0...

Page 988: ...able STACARDINT in the Normal Interrupt Status Enable register to 0 2 If SD memory card is used go to step 4 In case of other card go to step 3 3 Use CMD52 to set IENM of the CCCR in a SDIO or SD combo card to 0 4 Change the bit mode for a SD card To change SD memory card bus width by ACMD6 Set bus width and SDIO card bus width set Bus Width of Bus Interface Control register in CCCR 5 If you want ...

Page 989: ...igure 7 8 Timeout Setting Sequence In order to detect timeout errors on DAT line the Host Driver executes the following two steps before any SD transaction 1 To calculate a divisor for detecting timeout refer to Timeout Control Register 9 16 2 Set Data Timeout Counter Value TIMEOUTCON in the Timeout Control register in accordance with the value of step 1 ...

Page 990: ...use the DAT line for transferring data In this specification the first and the second case s transactions are classified as Transaction Control without Data Transfer using DAT Line the third case s transaction is classified as Transaction Control with Data Transfer using DAT Line Refer to the specifications below for the detailed specifications on the SD Command itself SD Memory Card Specification...

Page 991: ...d Check Command Inhibit CMD CMD Line free Issue the Command with the Busy 2 yes Issue Abort Command 3 no 4 Check Command Inhibit DAT DAT Line used DAT Line free yes no New command can be issued Set Argument Reg Set Command Reg 5 6 Command Complete Sequence 7 Figure 7 9 Timeout Setting Sequence ...

Page 992: ... without busy signal go to step 5 3 If the Host Driver issues an abort command go to step 5 If no abort command is issued go to step 4 4 Check Command Inhibit DAT in the Present State register Repeat this step until Command Inhibit DAT is 0 5 Set the value corresponding to the issued command in the Argument register 6 Set the value corresponding to the issued command in the Command register NOTE I...

Page 993: ... 5 If not go to step 7 5 Wait for the Transfer Complete Interrupt If the Transfer Complete Interrupt occurs go to step 6 6 Write 1 to Transfer Complete STATRANCMPLT in the Normal Interrupt Status register to clear this bit 7 Check for errors in Response Data If there is no error proceed with step 8 If there is an error go to step 9 8 Return Status of No Error 9 Return Status of Response Contents E...

Page 994: ...omplete Status Get Response Data Command with Transfer Complete Int Wait for Transfer Complete Int Clear Transfer Complete Status Transfer Complete Int occur Check Response Data no No error Return Status No Error Return Status Response Contents Error Error END 1 2 3 4 5 6 7 8 9 Figure 7 10 Command Complete Sequence ...

Page 995: ...cation are as follows 1 Single Block Transfer The number of blocks is specified to the Host Controller before the transfer The number of blocks specified is always one 2 Multiple Block Transfer The number of blocks is specified to the Host Controller before the transfer The number of blocks specified is one or more 3 Infinite Block Transfer The number of blocks is not specified to the Host Control...

Page 996: ...ffer Write Ready Int occur Clear Buffer Write Ready Status Set Block Data More Blocks write read 9 10 W 11 W 12 W 13 W yes no Wait for Buffer Read Ready Interrupt Buffer Read Ready Int occur Clear Buffer Read Ready Status Get Block Data 11 R 12 R 10 R More Blocks yes 13 R no Single Multi Infinite Block Transfer Single or Multi block transfer Infinite block transfer Wait for Transfer Complete Inter...

Page 997: ...ead from a card go to step 10 R 10 10 W Wait for Buffer Write Ready Interrupt 11 11 W Write 1 to the Buffer Write Ready STABUFWTRDY in the Normal Interrupt Status register to clear this bit 12 12 W Write block data in according to the number of bytes specified at the step 1 to Buffer Data Port register 13 13 W Repeat until all blocks are sent and then go to step 14 14 10 R Wait for the Buffer Read...

Page 998: ...n Control with Data Transfer Using DAT Line Sequence Using DMA 1 Set the system address for DMA in the System Address register 2 Set the value corresponding to the executed data byte length of one block in the Block Size register 3 Set the value corresponding to the executed data block count in the Block Count register BLKCNT 4 Set the value corresponding to the issued command in the Argument regi...

Page 999: ... STATRANCMPLT is set 1 go to Step 14 else if DMA Interrupt is set to 1 proceed to Step 12 Transfer Complete is higher priority than DMA Interrupt 12 Write 1 to the DMA Interrupt in the Normal Interrupt Status register to clear this bit 13 Set the next system address of the next data position to the System Address register and go to Step 10 14 Write 1 to the Transfer Complete and DMA Interrupt in t...

Page 1000: ...he second case is if the Host Driver stops transfers while a Multiple Block Transfer is executing There are two ways to issue an Abort Command namely asynchronous abort and synchronous abort In an asynchronous abort sequence the Host Driver issues an Abort Command at anytime unless Command Inhibit CMD in the Present State register is set to 1 In a synchronous abort the Host Driver issues an Abort ...

Page 1001: ...ing non DAT line commands during a DMA transfer The result of a DMA transfer is same regardless of the system bus transaction method DMA does not support infinite transfers DMA transfers are stopped and restarted using control bits in the Block Gap Control register If the Stop At Block Gap Request is set DMA transfers is suspended If the Continue Request is set or a Resume Command is issued DMA co...

Page 1002: ... bit address registers Support of SDMA and ADMA are optional for the Host Controller ADMA improves the restriction so that data of any location and any size can be transferred in system memory The format of Descriptor Table is different between them The Host Controller Specification Ver2 00 defines ADMA as standard ADMA 7 7 1 BLOCK DIAGRAM OF ADMA Figure 7 13 Block Diagram of ADMA Figure 7 13 show...

Page 1003: ...d In this case the transfer should be aborted by data timeout Block Count register is defined as 16 bit register and it limits the maximum of 65535 blocks transfer If ADMA operation is less than or equal 65535 blocks transfer Block Count register can be used In this case total length of Descriptor Table shall be equivalent to multiply block size and block count If ADMA operation is more than 65535...

Page 1004: ...n is used to connect separated two descriptors The address field of link points to next Descriptor Table The combination of Act2 0 and Act1 1 is reserved and defined the same operation as Nop A future version of controller may use this field and redefine a new operation 32 bit address is stored in the lower 32 bit of 64 bit address registers Address field shall be set on 32 bit boundary Lower 2 bi...

Page 1005: ...STATES Figure 7 16 shows state diagram of ADMA Four states are defined namely Fetch Descriptor state Change Address state Transfer Data state and Stop ADMA state Operation of each state is explained in Table 7 2 Figure 7 16 State Diagram of the ADMA ...

Page 1006: ...and register go to ST_FDS state ADMA does not support suspend resume function but stop and continue are available When the Stop at Block Gap Request in the Block Gap Control register is set during the ADMA operation the Block Gap Event Interrupt is generated when ADMA is stopped at block gap The Host Controller shall stop ADMA read operation by using Read Wait or stopping SD Clock While stopping A...

Page 1007: ...DATA 1 muxed SD_1_DATA 2 IN OUT Data for SDMMC1 Xmmc1DATA 2 muxed SD_1_DATA 3 IN OUT Data for SDMMC1 Xmmc1DATA 3 muxed SD_1_CDn INPUT Card Detect for SDMMC1 Xmmc1CDn muxed SD_2_CLK OUTPUT Clock for SDMMC2 Xmmc2CLK muxed SD_2_CMD IN OUT Command for SDMMC2 Xmmc2CMD muxed SD_2_DATA 0 IN OUT Data for SDMMC2 Xmmc2DATA 0 muxed SD_2_DATA 1 IN OUT Data for SDMMC2 Xmmc2DATA 1 muxed SD_2_DATA 2 IN OUT Data ...

Page 1008: ...cription Pad Type SD_3_CDn INPUT Card Detect for SDMMC3 Xmmc3CDn muxed NOTE SDMMC external pads are shared with CAMIF or SPI In order to use these pads for SDMMC set the GPIO before the SDMMC started Refer to the GPIO chapter for correct GPIO settings ...

Page 1009: ...PRNSTS0 0xEB00_0024 R ROC Present State Register Channel 0 0x000A0000 HOSTCTL0 0xEB00_0028 R W Present State Register Channel 0 0x0 PWRCON0 0xEB00_0029 R W Present State Register Channel 0 0x0 BLKGAP0 0xEB00_002A R W Block Gap Control Register Channel 0 0x0 WAKCON0 0xEB00_002B R W Wakeup Control Register Channel 0 0x0 CLKCON0 0xEB00_002C R W Command Register Channel 0 0x0 TIMEOUTCON0 0xEB00_002E R...

Page 1010: ...B10_0008 R W Command Argument Register Channel 1 0x0 TRNMOD1 0xEB10_000C R W Transfer Mode Setting Register Channel 1 0x0 CMDREG1 0xEB10_000E R W Command Register Channel 1 0x0 RSPREG0_1 0xEB10_0010 ROC Response Register 0 Channel 1 0x0 RSPREG1_1 0xEB10_0014 ROC Response Register 1 Channel 1 0x0 RSPREG2_1 0xEB10_0018 ROC Response Register 2 Channel 1 0x0 RSPREG3_1 0xEB10_001C ROC Response Register...

Page 1011: ...L4_1 0xEB10_008C R W Control register 4 Channel 1 0x0 HCVER1 0xEB10_00FE HWInit Host Controller Version Register Channel 1 0x2401 SDMASYSAD2 0xEB20_0000 R W SDMA System Address register Channel 2 0x0 BLKSIZE2 0xEB20_0004 R W Host DMA Buffer Boundary and Transfer Block Size Register Channel 2 0x0 BLKCNT2 0xEB20_0006 R W Blocks count for current transfer channel 2 0x0 ARGUMENT2 0xEB20_0008 R W Comma...

Page 1012: ...nel 2 0x0000 FEERR2 0xEB20_0052 W Force Event Error Interrupt Register Error Interrupt Channel 2 0x0000 ADMAERR2 0xEB20_0054 R W ADMA Error Status Register Channel 2 0x00 ADMASYSADDR2 0xEB20_0058 R W ADMA System Address Register Channel 2 0x00 CONTROL2_2 0xEB20_0080 R W Control register 2 Channel 2 0x0 CONTROL3_2 0xEB20_0084 R W FIFO Interrupt Control Control Register 3 Channel 2 0x7F5F3F1F CONTRO...

Page 1013: ...x0 ERRINTSTSEN3 0xEB30_0036 R W Error Interrupt Status Enable Register Channel 3 0x0 NORINTSIGEN3 0xEB30_0038 R W Normal Interrupt Signal Enable Register Channel 3 0x0 ERRINTSIGEN3 0xEB30_003A R W Error Interrupt Signal Enable Register Channel 3 0x0 ACMD12ERRSTS3 0xEB30_003C ROC Auto CMD12 error status register channel 3 0x0 CAPAREG3 0xEB30_0040 HWInit Capabilities Register Channel 3 0x05E80080 MA...

Page 1014: ... has stopped Read operations during transfers can return an invalid value The Host Driver initializes this register before starting a DMA transaction After DMA has stopped the next system address of the next contiguous data position is read from this register The DMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register The Host Controller gener...

Page 1015: ...ister is set to 0 buffer size 4K bytes lower 12 bit of byte address points data in the contiguous buffer and the upper 20 bit points the location of the buffer in the system memory The DMA transfer stops if the Host Controller detects carry out of the address from bit 11 to 12 These bits are supported if the SDMA Support in the Capabilities register is set to 1 and this function is active if DMA E...

Page 1016: ...between 1 and the maximum block count The Host Controller decrements the block count after each block transfer and stops if the count reaches zero Setting the block count to 0 results in no data blocks being transferred This register must be accessed if no transaction is in progress i e after transactions are stopped During data transfer read operations on this register returns an invalid value an...

Page 1017: ...MENT1 R W Address 0xEB10_0008 ARGUMENT2 R W Address 0xEB20_0008 ARGUMENT3 R W Address 0xEB30_0008 This register contains the SD Command Argument ARGUMENT Bit Description Initial State ARGUMENT 31 0 Command Argument The SD Command Argument is specified as bit 39 8 of Command Format in the SD Memory Card Physical Layer Specification 0 ...

Page 1018: ...5 14 Reserved 0 BOOTACK 13 Boot ACK Receive Enable when Boot mode 0 BOOTCMD 12 Boot Command mode Enable Note In boot mode Do Not Enable Auto CMD12 Enable 0 Reserved 11 10 Reserved 0 CCSCON 9 8 Command Completion Signal Control 00 No CCS Operation Normal operation and No CE ATA mode 01 Read or Write data transfer CCS enable Only CE ATA mode 10 Without data transfer CCS enable Only CE ATA mode 11 Ab...

Page 1019: ... register which is only relevant for multiple block transfers If this bit is 0 the Block Count register is disabled which is useful in executing an infinite transfer Refer to the Table below Determination of Transfer Type 1 Enable 0 Disable 0 ENDMA 0 DMA Enable This bit enables DMA functionality DMA is enabled if it is supported as indicated in the DMA Support in the Capabilities register If DMA i...

Page 1020: ...ot use Auto Command 12 operation and set Response Type Select field to 2 b00 No Response 2 This Host Controller do not support alternative boot operation using CMD0 with the argument of 0xFFFFFFFA 3 After boot code transfer is done perform byte write of address 0xD and set it to 0 so that CMD line goes back to HIGH Make clear BOOTCMD BOOTACK field Then wait for minimum of 56 SDCLK cycles as shown ...

Page 1021: ...s are set to 00b for all other commands Suspend Command If the Suspend command succeeds the Host Controller assumes that the SD Bus has been released and it is possible to issue the next command which uses the DAT line The Host Controller de asserts Read Wait for read transactions and stops checking busy for write transactions The interrupt cycle starts in 4 bit mode If the Suspend command fails t...

Page 1022: ...e Host Controller checks the Index field in the response to see if it has the same value as the command index If it is not it is reported as a Command Index Error If this bit is set to 0 the Index field is not checked 1 Enable 0 Disable ENC MDCRC 3 Command CRC Check Enable If this bit is set to 1 the Host Controller checks the CRC field in the response If an error is detected it is reported as a C...

Page 1023: ...1b R5b These bits determine Response types NOTE 1 In the SDIO specification response type notation of R5b is not defined R5 includes R5b in the SDIO specification But R5b is defined in this specification to specify the Host Controller checks busy after receiving response For example usually CMD52 is used as R5 but I O abort command is used as R5b 2 For CMD52 to read BS after writing Bus Suspend Co...

Page 1024: ...G0_2 ROC Address 0xEB20_0010 Response Register 1 Channel 2 RSPREG1_2 ROC Address 0xEB20_0014 Response Register 2 Channel 2 RSPREG2_2 ROC Address 0xEB20_0018 Response Register 3 Channel 2 RSPREG3_2 ROC Address 0xEB20_001C Response Register 0 Channel 3 RSPREG0_3 ROC Address 0xEB30_0010 Response Register 1 Channel 3 RSPREG1_3 ROC Address 0xEB30_0014 Response Register 2 Channel 3 RSPREG2_3 ROC Address...

Page 1025: ...esponse register at REP 119 0 To be able to read the response status efficiently the Host Controller only stores part of the response data in the Response register This enables the Host Driver to efficiently read 32 bits of response data in one read cycle on a 32 bit bus system Parts of the response the Index field and the CRC are checked by the Host Controller as specified by the Command Index Ch...

Page 1026: ...W Address 0xEB20_0020 BDATA3 R W Address 0xEB30_0020 32 bit data port register to access internal buffer BDATA Bit Description Initial State BUFDAT 31 0 Buffer Data The Host Controller buffer is accessed through this 32 bit single port SRAM memory Write and Read memories are separated Not fixed NOTE Detailed documents are to be copied from SD Host Standard Specification ...

Page 1027: ...served 1 PRNTCD 18 Card Detect Pin Level RO This bit reflects the inverse value of the SDCD pin Debouncing is not performed on this bit This bit is valid if Card State Stable is set to 1 but it is not guaranteed because of propagation delay Use of this bit is limited to testing since it must be debounced by software 1 Card present SDCD 0 0 No card present SDCD 1 Note SDCD port is mapped to SD0_nCD...

Page 1028: ... buffer A change of this bit from 1 to 0 occurs if all the block data is read from the buffer A change of this bit from 0 to 1 occurs if block data is ready in the buffer and generates the Buffer Read Ready interrupt 1 Enables Read 0 Disables Read 0 BUFWTRDY 10 Buffer Write Enable ROC This status is used for non DMA write transfers The Host Controller implements multiple buffers to transfer data e...

Page 1029: ... Reserved 0 DATLINEACT 2 DAT Line Active ROC This bit indicates whether one of the DAT line on SD Bus is in use a In the case of read transactions This status indicates if a read transfer is In progress on the SD Bus Change in this value from 1 to 0 between data blocks generates a Block Gap Event interrupt in the Normal Interrupt Status register This bit is set in either of the following cases 1 A...

Page 1030: ...to 0 generates a Transfer Complete interrupt in the Normal Interrupt Status register Note The SD Host Driver saves registers in the range of 000 00Dh for a suspend transaction after this bit has changed from 1 to 0 1 Cannot issue command which uses the DAT line 0 Issues command which uses the DAT line 0 CMDINHCMD 0 Command Inhibit CMD ROC If this bit is 0 it indicates the CMD line is not in use an...

Page 1031: ...cing clock becomes valid Card Inserted No Card SDCD 1 SDCD 0 Stable Stable Figure 7 17 Card Detect State The above Figure 7 17 shows the state definitions of hardware that handles Debouncing Figure 7 18 Timing of Command Inhibit DAT and Command Inhibit CMD with Data Transfer ...

Page 1032: ...S5PC110_UM 7 SD MMC CONTROLLER 7 52 Figure 7 19 Timing of Command Inhibit DAT for the Case of Response with Busy Figure 7 20 Timing of Command Inhibit CMD for the Case of No Response Command ...

Page 1033: ...es by referring the Capabilities register Use of selected DMA is determined by DMA Enable of the Transfer Mode register 00 Selects SDMA 01 Reserved 10 Selects 32 bit Address ADMA2 11 Selects 64 bit Address ADMA2 Not supported 0 OUTEDGEINV 2 Output Edge Inversion If this bit is set to 0 default the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock If this bit is set...

Page 1034: ...s are set the Host Driver selects the voltage level for the SD card Before setting this register the Host Driver checks the Voltage Support bits in the Capabilities register If an unsupported voltage is selected the Host System does not supply SD Bus voltage 111b 3 3V Typ 110b 3 0V Typ 101b 1 8V Typ 100b 000b Reserved 0 PWRON 0 SD Bus Power Before setting this bit the SD Host Driver sets SD Bus Vo...

Page 1035: ...If the card supports read wait set this bit to enable use of the read wait protocol to stop read data using the DAT 2 line Otherwise the Host Controller has to stop the SD Clock to hold read data which restricts commands generation If the Host Driver detects an SD card insertion it sets this bit according to the CCCR of the SDIO card If the card does not support read wait this bit will never be se...

Page 1036: ...s not write data to Buffer Data Port register This bit affects Read Transfer Active Write Transfer Active DAT Line Active and Command Inhibit DAT in the Present State register Regarding detailed control of bits D01 and D00 RW 1 Stop 0 Transfer 0 There are three cases to restart the transfer after stop at the block gap Appropriate case depends on whether the Host Controller issues a Suspend command...

Page 1037: ...ted Removed or Card Interrupt Stop mode Wakeup Event Occurred ROC RW1C 1 Wakeup Interrupt Occurred 0 Wakeup Interrupt Not occurred or Cleared 0 ENWKUPREM 2 Wakeup Event Enable On SD Card Removal This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status register FN_WUS Wake Up Support in CIS does not affect this bit RW 1 Enables 0 Disables 0 ENWKUPINS 1 Wakeup Event En...

Page 1038: ...clock divided by 2 00h base clock 10MHz 63MHz Setting 00h specifies the highest frequency of the SD Clock Setting multiple bits the most significant bit is used as the divisor But multiple bits must not be set The two default divider values are calculated by the frequency that is defined by the Base Clock Frequency For SD Clock in the Capabilities register 1 25MHz divider value 2 400kHz divider va...

Page 1039: ...gister is cleared this clears the bit RW 1 Enables 0 Disables 0 STBLINTCLK 1 Internal Clock Stable This bit is set to 1 if SD Clock is stable after writing to Internal Clock Enable in this register to 1 The SD Host Driver waits to set SD Clock Enable until this bit is set to 1 Note This is useful if PLL is used for a clock oscillator that requires setup time ROC 1 Ready 0 Not Ready 0 ENINTCLK 0 In...

Page 1040: ...al State Reserved 7 4 Reserved 0 TIMEOUTCON 3 0 Data Timeout Counter Value This value determines the interval by which DAT line timeouts are detected Refer to the Data Timeout Error in the Error Interrupt Status register for information on factors that dictate timeout generation Timeout clock frequency is generated by dividing the base clock TMCLK value by this value While setting this register pr...

Page 1041: ...t RWAC The following registers and bits are cleared by this bit Buffer Data Port register Buffer is cleared and initialized Present State register Buffer Read Enable Buffer Write Enable Read Transfer Active Write Transfer Active DAT Line Active Command Inhibit DAT Block Gap Control register Continue Request Stop At Block Gap Request Normal Interrupt Status register Buffer Read Ready Buffer Write R...

Page 1042: ...Init are cleared to 0 During its initialization the Host Driver sets this bit to 1 to reset the Host Controller The Host Controller reset this bit to 0 if capabilities registers are valid and the Host Driver reads them If this bit is set to 1 the SD card resets itself and must be reinitialized by the Host Driver RWAC 1 Reset 0 Work ...

Page 1043: ... set Therefore the Host Driver checks this bit first to efficiently tests for an error This bit is read only ROC 0 No Error 1 Error 0 STAFIA3 14 FIFO SD Address Pointer Interrupt 3 Status RW1C 0 Occurred 1 Not Occurred If the FIFO Address of the SD clock side reaches the FIFO Interrupt Address register 3 values this status bit is asserted 0 STAFIA2 13 FIFO SD Address Pointer Interrupt 2 Status RW1...

Page 1044: ...d in the Host Controller and to stop driving the interrupt signal to the Host System After completion of the card interrupt service It must reset interrupt factors in the SD card and the interrupt signal may not be asserted write 1 to clear this register field RW1C and set Card Interrupt Signal Enable to 1 to re start sampling the interrupt signal The Card Interrupt Status Enable must remain set t...

Page 1045: ...nerates DMA Interrupt 0 No DMA Interrupt 0 STABLKGAP 2 Block Gap Event If the Stop At Block Gap Request in the Block Gap Control register is set this bit is set if both read write transaction is stopped at a block gap If Stop At Block Gap Request is not set to 1 this bit is not set to 1 RW1C 1 In the case of a Read Transaction This bit is set at the falling edge of the DAT Line Active Status When ...

Page 1046: ...or 0 1 Timeout occur during transfer 1 Don t care Data transfer complete 1 Data Transfer Complete 0 No Transfer Complete STACMDCMPLT 0 Command Complete This bit is set when receive the end bit of the command response Except Auto CMD12 Refer to Command Inhibit CMD in the Present State register The table below shows that Command Timeout Error has higher priority than Command Complete If both bits ar...

Page 1047: ...rs during ADMA based data transfer The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register In addition the Host Controller generates this Interrupt if it detects invalid descriptor data Valid 0 at the ST_FDS state ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state The Host Driver may find that Valid bit is not set at the error d...

Page 1048: ...turned and the Command Timeout Error is set to 0 indicating no timeout this bit is set to 1 if it detects a CRC error in the command response 2 The Host Controller detects a CMD line conflict by monitoring the CMD line if a command is issued If the Host Controller drives the CMD line to 1 level but detects 0 levels on the CMD line at the next SDCLK edge then the Host Controller aborts the command ...

Page 1049: ... CRC Error and Command Timeout Error is shown in Table below The Relation Between Command CRC Error and Command Timeout Error Command CRC Error Command Timeout Error Kinds of Error 0 0 No Error 0 1 Response Timeout Error 1 0 Response CRC Error 1 1 CMD line conflict ...

Page 1050: ... Masked 0 ENSTAFIA1 12 FIFO SD Address Pointer Interrupt 1 Status Enable 1 Enabled 0 Masked 0 ENSTAFIA0 11 FIFO SD Address Pointer Interrupt 0 Status Enable 1 Enabled 0 Masked 0 ENSTARWAIT 10 Read Wait interrupt status enable 1 Enabled 0 Masked 0 ENSTACCS 9 CCS Interrupt Status Enable 1 Enabled 0 Masked 0 ENSTACARDINT 8 Card Interrupt Status Enable If this bit is set to 0 the Host Controller clear...

Page 1051: ...eady Status Enable 1 Enabled 0 Masked 0 ENSTABUFWTRDY 4 Buffer Write Ready Status Enable 1 Enabled 0 Masked 0 ENSTADMA 3 DMA Interrupt Status Enable 1 Enabled 0 Masked 0 ENSTABLKGAP 2 Block Gap Event Status Enable 1 Enabled 0 Masked 0 ENSTASTANSCMPLT 1 Transfer Complete Status Enable 1 Enabled 0 Masked 0 ENSTACMDCMPLT 0 Command Complete Status Enable 1 Enabled 0 Masked 0 ...

Page 1052: ...d 0 ENSTAACMDERR 8 Auto CMD12 Error Status Enable 1 Enabled 0 Masked 0 ENSTACURERR 7 Current Limit Error Status Enable This function is not implemented in this version 1 Enabled 0 Masked 0 ENSTADENDERR 6 Data End Bit Error Status Enable 1 Enabled 0 Masked 0 ENSTADATCRCERR 5 Data CRC Error Status Enable 1 Enabled 0 Masked 0 ENSTADATTOUTERR 4 Data Timeout Error Status Enable 1 Enabled 0 Masked 0 ENS...

Page 1053: ...rupts using the Error Interrupt Signal Enable register 0 ENSIGFIA3 14 FIFO SD Address Pointer Interrupt 3 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA2 13 FIFO SD Address Pointer Interrupt 2 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA1 12 FIFO SD Address Pointer Interrupt 1 Signal Enable 1 Enabled 0 Masked 0 ENSIGFIA0 11 FIFO SD Address Pointer Interrupt 0 Signal Enable 1 Enabled 0 Masked 0 ENSIGRW...

Page 1054: ...asked 0 ENSIGBUFWTRDY 4 Buffer Write Ready Signal Enable 1 Enabled 0 Masked 0 ENSIGDMA 3 DMA Interrupt Signal Enable 1 Enabled 0 Masked 0 ENSIGBLKGAP 2 Block Gap Event Signal Enable 1 Enabled 0 Masked 0 ENSIGSTANSCMPLT 1 Transfer Complete Signal Enable 1 Enabled 0 Masked 0 ENSIGCMDCMPLT 0 Command Complete Signal Enable 1 Enabled 0 Masked 0 ...

Page 1055: ...Reserved 0 ENSIGBOOTACKERR 10 Boot Ack Error Signal Enable 1 Enabled 0 Masked 0 ENSIGADMAERR 9 ADMA Error Signal Enable 1 Enabled 0 Masked 0 ENSIGACMDERR 8 Auto CMD12 Error Signal Enable 1 Enabled 0 Masked 0 ENSIGCURERR 7 Current Limit Error Signal Enable This function is not implemented in this version 1 Enabled 0 Masked 0 ENSIGDENDERR 6 Data End Bit Error Signal Enable 1 Enabled 0 Masked 0 ENSIG...

Page 1056: ...SD MMC CONTROLLER 7 76 ERRINTSIGEN Bit Description Initial State ENSIGCMDTOUTERR 0 Command Timeout Error Signal Enable 1 Enabled 0 Masked 0 NOTE Detailed documents must be copied from SD Host Standard Specification ...

Page 1057: ...ommand Index error occurs in response to a command 1 Error 0 No Error 0 STACMDEBITAER 3 Auto CMD12 End Bit Error Occurs it detects that the end bit of command response is 0 1 End Bit Error Generated 0 No Error 0 STACMDCRCAER 2 Auto CMD12 CRC Error Occurs if it detects a CRC error in the command response 1 CRC Error Generated 0 No Error 0 STACMDTOUTAER 1 Auto CMD12 Timeout Error Occurs if no respon...

Page 1058: ...o 0 if Auto CMD12 is issued 2 At the end bit of an Auto CMD12 response Check received responses by checking the error bits D01 D02 D03 and D04 Set to 1 if error is detected Set to 0 if error is not detected 3 Before reading the Auto CMD12 Error Status bit D07 Set D07 to 1 if there is a command cannot be issued Set D07 to 0 if there is no command to issue Timing to generate the Auto CMD12 Error and...

Page 1059: ...ot Supported 1 CAPAV30 25 Voltage Support 3 0V HWInit 1 3 0V Supported 0 3 0V Not Supported 0 CAPAV33 24 Voltage Support 3 3V HWInit 1 3 3V Supported 0 3 3V Not Supported 1 CAPASUSRES 23 Suspend Resume Support HWInit This bit indicates whether the Host Controller supports Suspend Resume functionality If this bit is 0 the Suspend and Resume mechanism are not supported and the Host Driver does not i...

Page 1060: ...ger value is set to 01 0001b 17MHz because the Host Driver use this value to calculate the clock divider value Refer to the SDCLK Frequency Select in the Clock Control register and it does not exceed upper limit of the SD Clock frequency The supported clock range is 10MHz to 63MHz If these bits are all 0 the Host System has to get information via another method Not 0 1MHz to 63MHz 000000b Get info...

Page 1061: ...gful if Voltage Support is set in the Capabilities register If this information is supplied by the Host System via another method all Maximum Current Capabilities register will be 0 MAXCURR Bit Description Initial State Reserved 31 24 Reserved MAXCURR18 23 16 Maximum Current for 1 8V HWInit 0 MAXCURR30 15 8 Maximum Current for 3 0V HWInit 0 MAXCURR33 7 0 Maximum Current for 3 3V HWInit 0 This regi...

Page 1062: ...egister 0 no effect D15 D12 FEAER Bit Description Initial State Reserved 15 8 Reserved 0x0 FENCMDAER 7 Force Event for Command Not Issued By Auto CMD12 Error 1 Generates Interrupt 0 No Interrupt 0 Reserved 6 5 Reserved 0 FECMDIDXERR 4 Force Event for Auto CMD12 Index Error 1 Interrupt 0 No Interrupt 0 FECMDEBITAER 3 Force Event for Auto CMD12 End Bit Error 1 Generates Interrupt 0 No Interrupt 0 FE...

Page 1063: ...r Interrupt can be set in the Error Interrupt Status register In order to generate interrupt signal both the Error Interrupt Status Enable and Error Interrupt Signal Enable must be set FEERR Bit Description Initial State Reserved 15 11 Reserved 0x0 FEBOOTACKERR 10 Force Event for Boot Ack Error 1 Interrupt is generated 0 No Interrupt 0 FEADMAERR 9 Force Event for ADMA Error 1 Generates Interrupt 0...

Page 1064: ...ROLLER 7 84 FEERR Bit Description Initial State FECMDCRCERR 1 Force Event for Command CRC Error 1 Generates Interrupt 0 No Interrupt 0 FECMDTOUTERR 0 Force Event for Command Timeout Error 1 Generates Interrupt 0 No Interrupt 0 ...

Page 1065: ... in the Host Controller The Host Controller generates the ADMA Error Interrupt if it detects invalid descriptor data Valid 0 at the ST_FDS state In this case ADMA Error State indicates that an error occurs at ST_FDS state The Host Driver finds that the Valid bit is not set in the error descriptor ADMAERR Bit Description Initial State Reserved 31 11 Reserved 0x00 STAADMAFINBLK 10 ADMA Final Block T...

Page 1066: ...e of ADMA when error is occurred during ADMA data transfer This field never indicates 10 because ADMA never stops in this state D01 D00 ADMA Error State when error is occurred Contents of SYS_SDR register 00 ST_STOP Stop DMA Points next of the error descriptor 01 ST_FDS Fetch Descriptor Points the error descriptor 10 Never set this state Not used 11 ST_TFR Transfer Data Points the next of the erro...

Page 1067: ...tart of ADMA the Host Driver sets start address of the Descriptor table The ADMA increments this register address which points to next line if having fetched a Descriptor line If the ADMA Error Interrupt is generated this register holds valid Descriptor address depending on the ADMA state The Host Driver programs Descriptor Table on 32 bit boundary and set 32 bit boundary address to this register ...

Page 1068: ...k Disable 1 Mask Enable Note If the OUTEDGEINV field in the Host Control Register is set High Speed data transfer this field should be enabled to prevent from command conflict status alarm 0 Reserved 29 Reserved must be 1 b0 0 SELCARDOUT 28 Card Removed Condition Selection 0 Card Removed condition is Not Card Insert State When the transition from Card Inserted state to Debouncing state in Figure 7...

Page 1069: ... 1 Enable 0 DFCNT 10 9 Debounce Filter Count Debounce Filter Count setting register for Card Detect signal input SDCD 00 No use debounce filter 01 4 x iFLTCLK 10 16 x iFLTCLK 11 64 x iFLTCLK 0 ENCLKOUTHOLD 8 SDCLK Hold Enable Enter and exit of the SDCLK Hold state is done by Host Controller 0 Disable 1 Enable Note This field should be 1 0 RWAITMODE 7 Read Wait Release Control 0 Read Wait state is ...

Page 1070: ...s not implemented in this version 0 Reserved 2 Reserved 0 ENCLKOUTMSKCON 1 SDCLK output clock masking when Card Insert cleared If this field is High it is used not to stop SDCLK if No Card state 0 Disable 1 Enable 0 HWINITFIN 0 SD Host Controller Hardware Initialization Finish 0 Not Finish 1 Finish 0 NOTE 1 Ensure to set SDCLK Hold Enable EnSCHold if the card does not support Read Wait to guarante...

Page 1071: ...rd position 0x5F FCSEL1 15 Feedback Clock Select 1 Reference 2 0x0 FIA1 14 8 FIFO Interrupt Address register 1 FIFO 512Byte Buffer memory word address unit Initial value 0x3F generates at 256 byte 64 word position 0x3F FCSEL0 7 Feedback Clock Select 0 Reference 2 0x0 FIA0 6 0 FIFO Interrupt Address register 0 FIFO 512Byte Buffer memory word address unit Initial value 0x1F generates at 128 byte 32 ...

Page 1072: ...Clock Output PAD Drive Strength Select 00 2mA 01 4mA 10 7mA 11 9mA Note This function is not implemented in this version 0x3 Reserved 15 2 Reserved STABLKGAPBUSY 1 Status Block Gap Access Busy This bit is High when the clock domain crossing HCLK to SDCLK operation is processing when the write operation to the BLKGAP register This bit is status bit and Read Only RO 0 STABUSY 0 Status Busy This bit ...

Page 1073: ...t HCVER Bit Description Initial State VENVER 15 8 Vendor Version Number This status is reserved for the vendor version number The Host Driver should not use this status 0x24 SDMMC4 2 Host Controller 0x24 SPECVER 7 0 Specification Version Number This status indicates the Host Controller Specification Version The upper and lower 4 bits indicate the version 00 SD Host Specification Version 1 0 01 SD ...

Page 1074: ...e SDRAM full interrupt occurs 8 1 1 KEY FEATURES OF TRANSPORT STREAM INTERFACE Writes transport stream received from channel chip to output buffer supports 1 4 8 beat burst word aligned Supports TS interface in DVB H DVB T ISDB T T DMB DAB mode Supports TS_CLK falling rising edge data fetch mode Supports active high or active low mode for TS signals TS_VALID TS_SYNC and TS_ERROR Supports MSB to LS...

Page 1075: ...ip and TSI stores it into output buffer Then TS De Packet PSI Analyzer DVB SI and PED De Packet blocks de multiplex individual PSI from the transport stream and transfer it to audio and video decoders PSI comprises of Program Association Table PAT Program Map Table PMT and Conditional Access Table CAT defined in MPEG 2 PAT Transmits the PID information of PMT and NID and information about various ...

Page 1076: ...eristics of Several Mobile TV Standard Modes Mobile TV Standard Video Codec Characteristics DVB T MPEG 2 MP ML 10Mbps 720 480 30fps H 264 Up to Baseline 352 288 15fps 384kbps DVB H WMV9 Up to SP ML 356 288 15fps 384kbps T DMB H 264 Up to Baseline Profile 352 288 30fps 768kbps ISDB T H 264 Up to Baseline Profile 320 240 15fps 384kbps ...

Page 1077: ...annel chip via five signals such as TS_CLK TS_SYNC TS_VALID TS_DATA and TS_ERROR TSI controller receives transport stream data by capturing the five signals with TSI synchronizer and TSI sync detector The received transport stream data is stored on TSI FIFO and TSI TX module transfers the transport stream data into output buffer using AHB master interface User can control operations of TSI by sett...

Page 1078: ...Source Destination ts_clk DI Specifies the TSI system clock 66MHz Channel chip Buffer ts_sync DI Specifies the TSI synchronization control signal Channel chip Buffer ts_val DI Specifies the TSI valid signal Channel chip Buffer ts_data DI Specifies the TSI input data Channel chip Buffer ts_error DI Specifies the TSI error indicate signal Channel chip Buffer where DI Digital Input Signal ...

Page 1079: ...188 bytes and it consists of the header adaptation field and payload The TS header includes a packet identifier PID sync byte and several control signals such as transport scrambling adaptation field and continuity control Figure 8 3 shows the transport stream packet data format Figure 8 3 Transport Stream Packet Data Format ...

Page 1080: ... and TS_DATA as active high or active low The active mode of each signal can be set independently Figure 8 4 shows the timing diagram of transport stream signals and describes the timing operation of each signal Figure 8 4 Transport Stream Signals 8 1 5 3 Sync Detection The sync detection of transport stream is done using TS_SYNC signal and sync byte ...

Page 1081: ...he sync detection using TS_SYNC signal Sync byte check 0 1 TS_CLK TS_SYNC TS_VALID TS_ERROR TS_DATA Packet Start TS_CLK Inverting 8 bit TS_VALID Active_low TS_ERROR Active_low 1 0 0 0 1 1 a Consecutive 8 bit TS_SYNC Detecting Sync byte check 0 1 TS_CLK TS_SYNC TS_VALID TS_ERROR TS_DATA Packet Start TS_CLK Inverting 1 bit TS_VALID Active_low TS_ERROR Active_low 1 0 0 0 1 1 b Only 1 bit TS_SYNC Dete...

Page 1082: ...er is equal to 187 bytes If the sync byte is inputted it initializes the data counter by zero and increases the sync detecting counter by one On the other hand if the inputted data is not the sync byte it disables the data counter and initializes the sync detecting counter by zero Consider the enabled total data counter to be less than 187 If the sync byte is inputted it enables the data counter a...

Page 1083: ...enabled csdc2 1 3 Sync byte input data count1 187 Data count1 set to 0 csdc1 2 4 Sync byte input data count2 187 Data count2 set to 0 csdc2 2 5 Sync byte input data count1 187 data count2 187 Data count3 enabled csdc3 1 6 Sync byte not input data count1 187 Data count1 disabled csdc1 0 7 Sync byte input data count2 187 data count3 187 Data count1 enabled csdc1 1 8 Sync byte input data count2 187 D...

Page 1084: ...mode Sync byte is not received at the start of packet 2 Packet size underflow only in TS_SYNC mode TS_SYNC signal is activated when the packet reception does not end TS_SYNC mode TS_SYNC signal is deactivated at the start of packet 3 Packet size overflow Sync byte mode Sync byte is not received at the start of packet Bit detecting TS_ERROR signal is activated when the packet reception is operating...

Page 1085: ...S5PC110_UM 8 TRANSPORT STREAM INTERFACE 8 12 Figure 8 7 TSI Error Cases with SKIP mode TS_VALID TS_SYNC TS_ERROR is active high ...

Page 1086: ... filter and 33MHz with TS_CLK filter Figure 8 8 shows the block diagram of TS_CLK filter CK D Q CK D Q CK D Q TS_CLK HCLK Noise Filter Synchronizer A B S0 Y TS_CLK_1dff TS_CLK_2dff TS_CLK_3dff Figure 8 8 Block Diagram of TS_CLK Filter 8 1 5 6 Transport Stream Write After the transport stream is received from the channel chip it is stored in internal FIFO 32 word The TSI sends the transport stream ...

Page 1087: ...rt stream is treated as normal and stored to output buffer However if the PID filter mode is disabled the PID filter value is not checked and all transport streams are recognized as normal 8 1 5 8 TSI Control FSM TSI has several operating modes As shown in Figure 8 9 the TSI can switch from one mode to another according to the condition state of control signals S T O P m o d e S T O P m o d e P a ...

Page 1088: ...n address to store received packet data Example of Shadow Base Address usage 1 Set the first address in TS_BASE register 2 Start TSI the first address is set as destination address 3 Set the second address in TS_BASE register right after TSI starts Output buffer becomes full the second address is set as new destination address 4 Set the third address in TS_BASE register when output buffer full int...

Page 1089: ...TSI PID filter4 32 h0000_0000 TS_PID5 0xEB40_0038 R W Specifies the TSI PID filter5 32 h0000_0000 TS_PID6 0xEB40_003C R W Specifies the TSI PID filter6 32 h0000_0000 TS_PID7 0xEB40_0040 R W Specifies the TSI PID filter7 32 h0000_0000 TS_PID8 0xEB40_0044 R W Specifies the TSI PID filter8 32 h0000_0000 TS_PID9 0xEB40_0048 R W Specifies the TSI PID filter9 32 h0000_0000 TS_PID10 0xEB40_004C R W Speci...

Page 1090: ... filter26 32 h0000_0000 TS_PID27 0xEB40_0090 R W Specifies the TSI PID filter27 32 h0000_0000 TS_PID28 0xEB40_0094 R W Specifies the TSI PID filter28 32 h0000_0000 TS_PID29 0xEB40_0098 R W Specifies the TSI PID filter29 32 h0000_0000 TS_PID30 0xEB40_009C R W Specifies the TSI PID filter30 32 h0000_0000 TS_PID31 0xEB40_00A0 R W Specifies the TSI PID filter31 32 h0000_0000 BYTE_SWAP 0xEB40_00BC R W ...

Page 1091: ... 2 2 1 TSI Clock Control Register TS_CLKCON R W Address 0xEB40_0000 TS_CLKCON Bit Description R W Initial State Reserved 31 2 TSI clock down ready 1 If this field is set to 1 TSI block is ready to be down 0 Not ready 1 Ready R 1 b1 TSI on 0 TSI on off 0 TSI off 1 TSI on R W 1 b0 ...

Page 1092: ...nt_mode 25 24 Sets the sync mismatch interrupt mode 0x Disable 10 Enable with skip mode 11 Enable with stop mode R W 2 b00 psuf_int_mode 23 22 Sets the packet size underflow interrupt mode 0x Disable 10 Enable with skip mode 11 Enable with stop mode R W 2 b00 psof_int_mode 21 20 Sets the packet size overflow interrupt mode 0x Disable 10 Enable with skip mode 11 Enable with stop mode R W 2 b00 ts_c...

Page 1093: ...pecifies the TS_DATA byte ordering 0 MSB to LSB 1 LSB to MSB R W 1 b0 ts_valid_active 4 Specifies the TS_VALID active mode 0 Active high 1 Active low R W 1 b0 ts_sync_active 3 Specifies the TS_SYNC active mode 0 Active high 1 Active low R W 1 b0 ts_clk_invert 2 Specifies the TS_CLK inverting mode 0 Non inverting falling edge data fetch 1 Inverting ringing edge data fetch R W 1 b0 Reserved 1 0 ...

Page 1094: ...it 1x Using sync byte 0x47 2 b00 8 2 2 4 TSI Clock Count Register TS_CNT R W Address 0xEB40_000C TS_CNT Bit Description R W Initial State ts_clk_error_cnt 31 0 Specifies the TS_CLK timeout period If the ts_clk does not toggle for n times of hclk ts_clk_timeout interrupt is generated TS_CLK timeout period HCLK 7 5ns n R W 32 h00FF_FFFF 8 2 2 5 TS Buffer Base Address Register TS_BASE R W Address 0xE...

Page 1095: ...es the TSI interrupt mask output buffer full 0 Masking 1 Not masking R W 1 b0 int_fifo_full_mask 5 Specifies the TSI interrupt mask internal FIFO full 0 Masking 1 Not masking R W 1 b0 sync_mismatch_mask 4 Specifies the TSI interrupt mask sync mismatch 0 Masking 1 Not masking R W 1 b0 packet_size_underflo w_mask 3 Specifies the TSI interrupt mask packet size underflow 0 Masking 1 Not masking R W 1 ...

Page 1096: ...no effect R W 1 b0 sync_mismatch_ flag 4 Specifies the Sync mismatch interrupt flag 0 Interrupt is not generated 1 Interrupt is generated Writing 1 clears this field and writing 0 has no effect R W 1 b0 psuf_flag 3 Specifies the Packet underflow interrupt flag 0 Interrupt is not generated 1 Interrupt is generated Writing 1 clears this field and writing 0 has no effect R W 1 b0 psof_flag 2 Specifie...

Page 1097: ...I PID Filter3 Address Register TS_PID3 R W Address 0xEB40_0030 8 2 2 14 TSI PID Filter4 Address Register TS_PID4 R W Address 0xEB40_0034 8 2 2 15 TSI PID Filter5 Address Register TS_PID5 R W Address 0xEB40_0038 8 2 2 16 TSI PID Filter6 Address Register TS_PID6 R W Address 0xEB40_003C 8 2 2 17 TSI PID Filter7 Address Register TS_PID7 R W Address 0xEB40_0040 8 2 2 18 TSI PID Filter8 Address Register...

Page 1098: ...ress Register TS_PID19 R W Address 0xEB40_0070 8 2 2 30 TSI PID Filter20 Address Register TS_PID20 R W Address 0xEB40_0074 8 2 2 31 TSI PID Filter21 Address Register TS_PID21 R W Address 0xEB40_0078 8 2 2 32 TSI PID Filter22 Address Register TS_PID22 R W Address 0xEB40_007C 8 2 2 33 TSI PID Filter23 Address Register TS_PID23 R W Address 0xEB40_0080 8 2 2 34 TSI PID Filter24 Address Register TS_PID...

Page 1099: ...TS_PID30 R W Address 0xEB40_009C 8 2 2 41 TSI PID Filter31 Address Register TS_PID31 R W Address 0xEB40_00A0 8 2 2 42 TSI TX Byte SWAP Register BYTE_SWAP R W Address 0xEB40_00BC BYTE_SWAP Bit Description R W Initial State Reserved 31 0 R W byte_swap 0 Specifies the TSI tx byte swap enable register for little endian 0 Disable big endian 1 Enable little endian 1 b1 ...

Page 1100: ...Section 9 MULTIMEDIA ...

Page 1101: ...er Map 1 58 1 5 2 Palette Memory PalRam 1 66 1 5 3 Gamma LUT Data 1 134 2 Camera Interface 2 1 2 1 Overview of Camera Interface 2 1 2 2 Key Features of CAMIF 2 3 2 3 External Interface 2 5 2 4 Input Output Description 2 6 2 5 Timing Diagram and Data Alignment of Camera 2 7 2 5 1 Timing Diagram of ITU Camera 2 7 2 5 2 MIPI CSI Data Alignment from MIPI Camera 2 10 2 6 External Connection Guide 2 11 ...

Page 1102: ...O Description 4 5 4 6 Register Description 4 6 4 6 1 Register Map 4 6 5 G3D 5 1 5 1 Overview of G3D 5 1 5 1 1 Key Features of G3D 5 1 5 1 2 3D Features in G3D 5 2 5 1 3 USSE Features in G3D 5 3 5 1 4 2D Features in G3D 5 4 5 1 5 Block Diagram of SGX540 5 5 5 1 6 Block Diagram of Integration Information 5 10 5 1 7 Register Map 5 11 6 Multi Format Codec 6 1 6 1 Introduction 6 1 6 1 1 Supported Stand...

Page 1103: ...8 Illegal Color Compensation CVBS module 7 17 7 9 Oversampling DAC Compensation Filter Osf Module 7 18 7 10 Register Control CTRL Module 7 21 7 11 I O DesCription 7 21 7 12 Register Description 7 22 7 12 1 Register Map 7 22 7 12 2 Shadow Registers 7 58 7 13 Video DAC 7 60 7 13 1 General Description 7 60 7 13 2 Features 7 60 7 13 3 Core Port Description 7 60 7 13 4 Full Scale Voltage Modification 7...

Page 1104: ...10 1 9 BLOCK Diagram of Clock Strategy for HDMI TX 10 12 10 2 SPDIF auxiliary information 10 14 10 2 1 Frame Format 10 14 10 3 Registrs Description 10 20 10 3 1 Register Map 10 21 10 3 2 Control Register 10 31 10 3 3 HDMI Core Register 10 35 10 3 4 SPDIF Register 10 75 10 3 5 I2S Register 10 90 10 3 6 Timing Generator RegisteR TG Configure Status Register 10 100 11 Image Rotator 11 1 11 1 Overview...

Page 1105: ...PEG Huffman and Quantization Register Tables 12 26 13 G2D 13 1 13 1 Introduction 13 1 13 2 Features 13 1 13 3 Color Format Conversion 13 2 13 4 Rendering Pipeline 13 3 13 4 1 Primitive Drawing 13 3 13 4 2 Rotation and Addressing Direction Flip 13 5 13 4 3 Clipping 13 7 13 4 4 Color Key 13 7 13 4 5 Raster Operation 13 8 13 4 6 Alpha Blending 13 9 13 5 Register Description 13 10 13 5 1 Register Map ...

Page 1106: ...ce Timing RGB skip 1 48 Figure 1 23 LCD RGB Interface Timing RGB serial Dummy disable 1 49 Figure 1 24 LCD RGB Interface Timing RGB serial Dummy insertion 1 50 Figure 1 25 LCD RGB Output Order 1 51 Figure 1 26 Delta Structure and LCD RGB Interface Timing 1 52 Figure 1 27 Indirect i80 System Interface WRITE Cycle Timing 1 54 Figure 2 1 Subset of Visual System in S5PC110 2 2 Figure 2 2 Camera Interf...

Page 1107: ... Video Mode 3 5 Figure 3 4 Block Timing Diagram of HSA Mode HSA mode reset DSIM_CONFIG 20 0 3 6 Figure 3 5 Block Timing Diagram of HSA Mode HSA mode set DSIM_CONFIG 20 1 3 6 Figure 3 6 Block Timing Diagram of HBP Mode HBP Mode Reset DSIM_CONFIG 21 0 3 7 Figure 3 7 Block Timing Diagram of HBP Mode HBP Mode Set DSIM_CONFIG 21 1 3 7 Figure 3 8 Block Timing Diagram of HFP Mode HFP Mode Reset DSIM_CONF...

Page 1108: ...sage Cases 8 15 Figure 8 6 Endian Mode 8 18 Figure 8 7 Video Scaling Positioning on TV Display 8 21 Figure 8 8 Image Brightness Contrast Control 8 43 Figure 8 9 4 Tap Vertical Poly phase Filter 8 45 Figure 8 10 Pixel Repetition at Picture Boundary 8 46 Figure 9 1 Block Diagram of Mixer 9 3 Figure 9 2 TV Sub System Block Diagram and Usage Frequency 9 4 Figure 9 3 Mixer Horizontal Scale and Blank ke...

Page 1109: ...12 4 Figure 12 4 Decimation and 1 2 Interpolation in Vertical Direction 12 4 Figure 12 5 YCbCr4 2 2 Color Format 12 5 Figure 12 6 Access Order in Quantizer Table 12 6 Figure 12 7 Bitstream of Compressed File 12 10 Figure 13 1 Color Format 13 2 Figure 13 2 FIMG 2D Rendering Pipeline 13 3 Figure 13 3 Rotation and Flip Example 13 6 ...

Page 1110: ... Address Map 3 10 Table 3 3 Relation Between Input Transactions and DSI Transactions 3 12 Table 3 4 MIPI DPHY Interface Slave Signal 3 14 Table 3 5 PMS and Frequency Constraint 3 31 Table 3 6 AFC Code 3 31 Table 3 7 Band Control Setting 3 32 Table 4 1 Timing Diagram of Output Data 4 3 Table 4 2 Data Order of YUV422 Alignment 4 4 Table 5 1 Glossary of Terms 5 6 Table 5 2 Power Mode Summary About G3...

Page 1111: ...Register Address Map 10 20 Table 12 1 Registers that Must be Configured Before Compression 12 7 Table 12 2 Relationship between Block Size and Color Format 12 8 Table 12 3 Markers in JPEG Codec 12 10 Table 12 4 JPEG Codec Control Registers 12 13 Table 12 5 Bitwise Expression of COEFxx 12 22 Table 12 6 JPEG Codec Table Assignment 12 26 ...

Page 1112: ...ler supports various color formats such as RGB 1 bpp to 24 bpp and YCbCr 4 4 4 only local bus It is programmed to support the different requirements on screen related to the number of horizontal and vertical pixels data line width for the data interface interface timing and refresh rate The display controller transfers the video data and generates the necessary control signals such as RGB_VSYNC RG...

Page 1113: ...ormat Window 0 Supports 1 2 4 or 8 bpp bit per pixel palletized color Supports 16 18 or 24 bpp non palletized color Supports RGB 8 8 8 local input from Local Bus FIMC0 Window 1 Supports 1 2 4 or 8 bpp bit per pixel palletized color Supports 16 18 or 24 bpp non palletized color Supports RGB 8 8 8 local input from Local Bus FIMC1 Window 2 Supports 1 2 4 or 8 bpp bit per pixel palletized color Suppor...

Page 1114: ...nction Supports simultaneously color key and blending function Partial Display Supports LCD partial display function through i80 interface Supports Gamma control Supports Hue control Supports color gain control Image Enhancement Supports pixel compensation only for delta structure ...

Page 1115: ...n Using the display controller data you can select one of the above data paths by setting DISPLAY_PATH_SEL 1 0 0xE010_7008 For more information refer to Chapter 02 03 S5PC110_CMU 1 3 2 DATA FLOW FIFO is in the VDMA If FIFO is empty or partially empty the VDMA requests data fetching from frame memory based on burst memory transfer mode The data transfer rate determines the size of FIFO The display ...

Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...

Page 1117: ... and data sync clock The second type is the indirect i80 Interface which uses address data chip select read write control and register status indicating signal The LCD driver using i80 Interface contains a frame buffer and can self refresh so the display controller updates one still image by writing only one time to the LCD The third type is FIFO interface with CAMIF2 for writeback Figure 1 3 Bloc...

Page 1118: ...play mode 1 3 3 2 25BPP Display A888 NOTE 1 AEN Specifies the transparency value selection bit AEN 0 Selects ALPHA0 AEN 1 Selects ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by SFR as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G and ALPHA1_B For more information refer to the section on SFR 2 D 23 16 Red data D 15 8 Green data ...

Page 1119: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 8 1 3 3 2 1 32BPP 8888 Mode Pixel data contains Alpha value ...

Page 1120: ...my Bit P4 Dummy Bit P6 D 55 AEN AEN AEN D 31 24 D 22 0 Dummy Bit P1 Dummy Bit P3 Dummy Bit P5 D 23 AEN AEN AEN P1 P2 P3 P4 P5 LCD Panel NOTE 1 AEN Specifies the transparency value selection bit AEN 0 Selects ALPHA0 AEN 1 Selects ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by SFR as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G ...

Page 1121: ... 55 32 Dummy Bit P1 P3 P5 BSWP 0 HWSWP 0 WSWP 0 Dummy Bit Dummy Bit Dummy Bit P2 P4 P6 Dummy Bit Dummy Bit D 31 24 D 23 0 BSWP 0 HWSWP 0 WSWP 1 000H 008H 010H D 63 56 D 55 32 Dummy Bit P2 P4 P6 Dummy Bit Dummy Bit Dummy Bit P1 P3 P5 Dummy Bit Dummy Bit D 31 24 D 23 0 P1 P2 P3 P4 P5 LCD Panel ...

Page 1122: ... 51 D 49 32 Dummy Bit P2 Dummy Bit P4 Dummy Bit P6 D 50 AEN AEN AEN D 31 19 D 17 0 Dummy Bit P1 Dummy Bit P3 Dummy Bit P5 D 18 AEN AEN AEN P1 P2 P3 P4 P5 LCD Panel NOTE 1 AEN Specifies the transparency value selection bit AEN 0 Selects ALPHA0 AEN 1 Selects ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by SFR as ALPHA0_R ALPHA0_G...

Page 1123: ... 49 32 Dummy Bit P1 P3 P5 BSWP 0 HWSWP 0 WSWP 0 Dummy Bit Dummy Bit D 31 18 D 17 0 Dummy Bit P2 P4 P6 Dummy Bit Dummy Bit BSWP 0 HWSWP 0 WSWP 1 000H 008H 010H D 63 50 D 49 32 Dummy Bit P2 P4 P6 Dummy Bit Dummy Bit D 31 18 D 17 0 Dummy Bit P1 P3 P5 Dummy Bit Dummy Bit P1 P2 P3 P4 P5 LCD Panel ...

Page 1124: ...fies the transparency value selection bit AEN 0 Selects ALPHA0 AEN 1 Selects ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by SFR as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G and ALPHA1_B For more information refer to the section on SFR 2 D 14 10 Red data D 9 5 Green data and D 4 0 Blue data ...

Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...

Page 1126: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 15 1 3 3 2 8 D 14 10 D 15 Red data D 9 5 D 15 Green data and D 4 0 D 15 Blue data 6BPP Display 565 P1 P2 P3 P4 P5 LCD Panel ...

Page 1127: ... per pixel blending is set then this pixel blends with alpha value selected by AEN 2 D 11 8 Red data D 7 4 Green data and D 3 0 Blue data 3 16BPP 4444 mode For more information refer to the section on SFR Data has Alpha value BYSWP 0 HWSWP 0 WSWP 0 000H 004H 008H D 59 48 P1 P5 P9 D 63 60 ALPHA1 ALPHA5 ALPHA9 D 43 32 P2 P6 P10 D 47 44 ALPHA2 ALPHA6 ALPHA10 D 27 16 P3 P7 P11 D 31 28 ALPHA3 ALPHA7 AL...

Page 1128: ...nsparency value selection bit AEN 0 Selects ALPHA0 AEN 1 Selects ALPHA1 If per pixel blending is set then this pixel blends alpha value selected by AEN Alpha value is selected by SFR as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G and ALPHA1_B For more information refer to the section on SFR 2 D 6 5 Red data D 4 2 Green data and D 1 0 Blue data ...

Page 1129: ... the transparency value selection bit with WPALCON Palette output format AEN 0 Selects ALPHA0 AEN 1 Selects ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by SFR as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G and ALPHA1_B For more information refer to the section on SFR ...

Page 1130: ...election bit with WPALCON Palette output format AEN 0 Selects ALPHA0 AEN 1 Selects ALPHA1 If per pixel blending is set then this pixel blends with alpha value selected by AEN Alpha value is selected by SFR as ALPHA0_R ALPHA0_G ALPHA0_B ALPHA1_R ALPHA1_G and ALPHA1_B For more information refer to the section on SFR ...

Page 1131: ... D 23 22 D 21 20 D 19 18 D 17 16 000H 008H D 15 14 D 13 12 D 11 10 D 9 8 D 7 6 D 5 4 D 3 2 D 1 0 000H 008H P17 P49 P18 P50 P19 P51 P20 P52 P21 P53 P22 P54 P23 P55 P24 P56 P25 P57 P26 P58 P27 P59 P28 P60 P29 P61 P30 P62 P31 P63 P32 P64 NOTE AEN Specifies the transparency value selection bit with WPALCON Palette output format AEN 0 Selects ALPHA0 AEN 1 Selects ALPHA1 If per pixel blending is set the...

Page 1132: ...A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 R4 B3 B2 B1 B0 I 1 2 3 4 5 LCD Panel 16BPP 5 6 5 Format Non Palette A 31 A 30 A 29 A 28 A 27 A 26 A 25 A 24 A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 F...

Page 1133: ... Coefficient approximation 1 164 2 7 2 4 2 2 2 0 7 1 596 2 7 2 6 2 3 2 2 7 1 793 2 7 2 6 2 5 2 2 2 1 7 0 813 2 6 2 5 2 3 7 0 534 2 6 2 2 7 0 391 2 5 2 4 2 1 7 0 213 2 4 2 3 2 1 2 0 7 2 018 2 8 2 1 7 2 115 2 8 2 3 2 2 2 1 2 0 7 1 371 2 8 2 6 2 4 2 3 2 2 2 1 2 0 8 1 540 2 8 2 7 2 3 2 1 8 0 698 2 7 2 5 2 4 2 1 2 0 8 0 459 2 6 2 5 2 4 2 2 2 1 8 0 336 2 6 2 4 2 2 2 1 8 0 183 2 5 2 3 2 2 2 1 2 0 8 1 732...

Page 1134: ...ominal range from 0 to 255 Coefficient approximation 0 257 2 6 2 1 8 0 183 2 5 2 3 2 2 2 1 2 0 8 0 504 2 7 2 0 8 0 614 2 7 2 4 2 3 2 2 2 0 8 0 098 2 4 2 3 2 0 8 0 062 2 4 8 0 148 2 5 2 2 2 1 8 0 101 2 4 2 3 2 1 8 0 291 2 6 2 3 2 1 8 0 338 2 6 2 4 2 2 2 1 2 0 8 0 439 2 6 2 5 2 4 8 0 368 2 7 2 5 2 1 8 0 399 2 6 2 5 2 2 2 1 8 0 071 2 4 2 1 8 0 040 2 3 2 1 8 0 299 2 6 2 3 2 2 2 0 8 0 213 2 5 2 4 2 2 2...

Page 1135: ...RAM Palette supports 8 8 8 6 6 6 5 6 5 R G B and other formats For Example See A 5 5 5 format write palette as shown in Table 1 2 Connect VD pin to TFT LCD panel R 5 VD 23 19 G 5 VD 15 11 and B 5 VD 7 3 AEN bit controls the blending function enable or disable Finally set WPALCON W1PAL case window0 register to 0 b101 The 32 bit 8 8 8 8 format has an alpha value directly without using alpha value re...

Page 1136: ...6 6 Palette Data Format Table 1 4 16BPP A 5 5 5 Palette Data Format 1 3 5 2 Palette Read Write You should not access palette memory when the Vertical Status VSTATUS register has an ACTIVE status VSTATUS must be checked to do Read Write operation on the palette ...

Page 1137: ... as caption win 4 as channel information win3 and win4 have color limitation while using color index with Color LUT This feature enhances the system performance by reducing the data rate of total system Example of Total Five Windows win 0 base Local YCbCr RGB without palette win 1 Overlay1 RGB with palette win 2 Overlay2 RGB with palette win 3 Caption RGB 1 2 4 with 16 level Color LUT win 4 Cursor...

Page 1138: ...01 AR G B 0 x q1 AR G B 1 x p1 AR G B 012 AR G B 01 x q2 AR G B 2 x p2 AR G B 0123 AR G B 012 x q3 AR G B 3 x p3 where AR0 Window 0 s Red blending factor AG0 Window 0 s Green blending factor AB0 Window 0 s Blue blending factor AR1 Window 1 s Red blending factor AR01 Window01 s Red blending factor alpha value blending between AR0 and AR1 AG01 Window01 s Green blending factor alpha value blending be...

Page 1139: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 28 Figure 1 5 Blending Equation Default blending equation Data blending B B x 1 alphaA A x alphaA Alpha value blending alphaB 0 alphaB x 0 alphaA x 0 ...

Page 1140: ...indow All windows have two kinds of alpha blending value Alpha value for transparency enable AEN value 1 Alpha value for transparency disable AEN value 0 If WINEN_F and BLD_PIX are enabled and ALPHA_SEL is disabled then AR is chosen using the following equation AR Pixel R s AEN value 1 b1 Reg ALPHA1_R Reg ALPHA0_R AG Pixel G s AEN value 1 b1 Reg ALPHA1_G Reg ALPHA0_G AB Pixel B s AEN value 1 b1 Re...

Page 1141: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 30 Figure 1 6 Blending Diagram Example Window n s blending factor decision n 0 1 2 3 4 For more information refer to the section on SFR ...

Page 1142: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 31 Figure 1 7 Blending Factor Decision NOTE If DATA 15 12 BPPMODE_F b 1110 ARGB4444 format is used to blend alpha value is DATA 15 12 DATA 15 12 4 bit 8 bit expanding ...

Page 1143: ... display controller supports various effects for image mapping For special functionality the Color Key register that specifies the color image of OSD layer is substituted by the background image either as cursor image or preview image of the camera Figure 1 8 Color Key Function Configurations ...

Page 1144: ...ROLLER 1 33 1 3 6 4 Blending and COLOR KEY Function The display controller supports simultaneous blending function with two transparency factors and Color Key function in the same window Figure 1 9 Blending and Color Key Function ...

Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...

Page 1146: ...AGE ENHANCEMENT 1 3 7 1 Overview of Image Enhancement One of the main functions of the VPRCS module is Image Enhancement The display controller supports Gamma Hue Color Gain and Pixel Compensation Control functions Figure 1 11 Image Enhancement Flow ...

Page 1147: ...operation between two LUT registers The output value saturates at 255 LUT64 255 0 LUT00 LUT01 4 LUT02 8 4 8 255 251 252 LUT63 248 Input 7 0 Output 7 0 sat ur at ed x y X L X R Y L Y R y x x X L x X L flo at x 4 4 x m od4 x y Y L y y Y R Y L X R X L x 4 0 x 255 0 y 25 5 Y L L UT_ X L 4 X R ceil x 4 4 Y R LUT _ X R 4 roun d Figure 1 12 Image Enhancement Flow ...

Page 1148: ... 2 bit integer and 8 bit fraction Maximum value is approximately 4 with 8 bit resolution The output value saturates at 255 1 3 7 4 Hue Control Hue Control comprises of eight registers for coefficients of Hue matrix Cb hue CBG0 Cb OFFSET_IN CBG1 Cr OFFSET_IN OFFSET_OUT Cr hue CRG0 Cb OFFSET_IN CRG1 Cr OFFSET_IN OFFSET_OUT In general OFFSET_IN is 128 and OFFSET_OUT is 128 CBG0 Cb OFFSET_IN 0 CBG0_P ...

Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...

Page 1150: ...Control The purpose of Pixel Compensation Control is to compensate data for delta structure Figure 1 15 Example1 RGBSPSEL 1 b0 RGB_SKIP 1 b1 PIXCOMPEN_DIR 1 b0 Figure 1 16 Example2 RGBSPSEL 1 b1 PIXCOMPEN_DIR 1 b0 Figure 1 17 Example3 RGBSPSEL 1 b1 PIXCOMPEN_DIR 1 b1 ...

Page 1151: ...e following equations the size of the LCD panel determines HOZVAL and LINEVAL HOZVAL Horizontal display size 1 LINEVAL Vertical display size 1 The CLKVAL field in VIDCON0 register controls the rate of RGB_VCLK signal Table 1 5 defines the relationship of RGB_VCLK and CLKVAL The minimum value of CLKVAL is 1 RGB_VCLK Hz HCLK CLKVAL 1 where CLKVAL 1 Table 1 5 Relation 16BPP Between VCLK and CLKVAL TF...

Page 1152: ...PU style LDI VTIME_I80 does not support this function in hardware logic This function is implemented by SFR setting LINEVAL HOZVAL OSD_LeftTopX_F OSD_LeftTopY_F OSD_RightBotX_F OSD_RightBotY_F PAGEWIDTH and OFFSIZE 1 3 8 5 LDI Command Control LDI receives both command and data Command specifies an index for selecting the SFR in LDI In control signal for command and data only SYS_RS signal has a sp...

Page 1153: ...commands are available 1 3 9 2 Normal Command To execute Normal command follow these steps Put commands into LDI_CMD0 11 maximum 12 commands Set CMDx_EN in LDI_CMDCON0 to enable normal command x For example if you want to enable command 4 you have to set CMD4_EN to 0x01 Set NORMAL_CMD_ST in I80IFCONB0 1 The display controller has the following characteristics for command operations Auto Normal Aut...

Page 1154: ...MD3_RS 1 and CMD4_RS 0 RSPOL 0 1 Auto Command C0 VD 17 0 NORMAL_CMD_START SFR VD 17 0 pending C1 C3 C0 C1 C3 RS 2 Normal Command ENVIDS auto clear auto clear F n F n 1 F n 2 F n 3 F n 4 F n 5 F n 6 F n 7 C4 C3 C2 C1 F m C4 C3 C2 C1 F n F n 1 RS F m 1 F n 9 F n 8 Figure 1 18 Sending Command 1 2 7 2 2 Indirect I80 Interface Trigger VTIME_I80 starts its operation when a software trigger occurs There ...

Page 1155: ...IDCON0 Table 1 6 i80 Output Mode VIDCON0 Register Value BPP Bus Width Split DATA Command DSI_EN 1 24 24 X R 7 0 G 7 0 B 7 0 CMD 23 0 000 16 16 X R 7 3 G 7 2 B 7 3 CMD 15 0 001 18 16 O 1st 2nd R 7 2 G 7 2 B 7 4 14 b0 B 3 2 CMD 15 0 010 18 9 O 1st 2nd R 7 2 G 7 5 G 4 2 B 7 2 CMD 17 9 CMD 8 0 011 24 16 O 1st 2nd R 7 0 G 7 0 B 7 0 8 b0 100 18 18 X R 7 2 G 7 2 B 7 2 CMD 17 0 L0 1_DATA 101 16 8 O 1st 2n...

Page 1156: ...rtual screen This is the data of line 10 of virtual screen This is the data of line 10 of virtual screen This is the data of line 11 of virtual screen This is the data of line 11 of virtual screen Before Scrolling View Port The same size of LCD panel LINEVAL 1 OFFSIZE PAGEWIDTH This is the data of line 1 of virtual screen This is the data of line 1 of virtual screen This is the data of line 2 of v...

Page 1157: ...CLK Muxed LCD_VDEN Output Data Enable XvVDEN Muxed LCD_VD 23 0 Output YCbCr data output XvVD 23 0 Muxed NOTE Type field indicates whether pads are dedicated to signal or pads are connected to multiplexed signals 1 3 11 2 LCD RGB Interface Timing V S Y N C H S Y N C V D E N V S P W 1 V B P D 1 V F P D 1 L IN E V A L 1 1 F R A M E V D E N H S P W 1 H B P D 1 H F P D 1 H O Z V A L 1 H S Y N C V C L K...

Page 1158: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 47 1 3 11 3 Parallel Output 1 3 11 3 1 General 24 bit Output RGBSPSEL 0 RGB_SKIP_EN 0 Figure 1 21 LCD RGB Interface Timing RGB parallel ...

Page 1159: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 48 1 3 11 3 2 RGB SKIP 8 bit output Color sub sampling RGBSPSEL 0 RGB_SKIP_EN 1 Figure 1 22 LCD RGB Interface Timing RGB skip ...

Page 1160: ...0_UM 1 0BDISPLAY CONTROLLER 1 49 1 3 11 4 Serial 8 bit Output 1 3 11 4 1 General 8 bit output RGBSPSEL 1 RGB_DUMMY_EN 0 InValid Data Invalid Data Figure 1 23 LCD RGB Interface Timing RGB serial Dummy disable ...

Page 1161: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 50 1 3 11 4 2 Dummy Insertion Output RGBSPSEL 1 RGB_DUMMY_EN 1 Figure 1 24 LCD RGB Interface Timing RGB serial Dummy insertion ...

Page 1162: ...LER 1 51 1 3 11 5 Output Configuration Structure 1 3 11 5 1 Color Order Control RGB_ORDER_O controls odd line color structure On the other hand RGB_ORDER_E VIDCON2 controls even line color structure Figure 1 25 LCD RGB Output Order ...

Page 1163: ... 0BDISPLAY CONTROLLER 1 52 1 3 11 5 2 Example of Delta Structure For more information refer to register RGB_ORDER_O E Example RGB_ORDER_O 000 RGB_ORDER_E 001 Figure 1 26 Delta Structure and LCD RGB Interface Timing ...

Page 1164: ... Output Chip select for LCD1 XvVSYNC Muxed SYS_WE Output Write enable XvVCLK Muxed SYS_OE Output Output enable XvVD 23 Muxed SYS_RS SYS_ADD 0 Output Address Output SYS_ADD 0 is Register State select XvVDEN Muxed NOTE Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals MIPI DSI mode when VIDCON0 30 1 SYS_ADD 1 SYS_ST 0 when VDOUT is from Fr...

Page 1165: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 54 1 3 12 2 Indirect i80 System Interface WRITE Cycle Timing Figure 1 27 Indirect i80 System Interface WRITE Cycle Timing ...

Page 1166: ...2 R 6 R 4 R 3 D 6 D 4 VD 21 R 5 R 3 R 2 D 5 D 3 VD 20 R 4 R 2 R 1 D 4 D 2 VD 19 R 3 R 1 R 0 D 3 D 1 VD 18 R 2 R 0 D 2 D 0 VD 17 R 1 D 1 VD 16 R 0 D 0 VD 15 G 7 G 5 G 5 VD 14 G 6 G 4 G 4 VD 13 G 5 G 3 G 3 VD 12 G 4 G 2 G 2 VD 11 G 3 G 1 G 1 VD 10 G 2 G 0 G 0 VD 9 G 1 VD 8 G 0 VD 7 B 7 B 5 B 4 VD 6 B 6 B 4 B 3 VD 5 B 5 B 3 B 2 VD 4 B 4 B 2 B 1 VD 3 B 3 B 1 B 0 VD 2 B 2 B 0 VD 1 B 1 VD 0 B 0 ...

Page 1167: ...4 R 5 R 7 B 7 R 3 VD 14 R 3 R 4 R 6 B 6 R 2 VD 13 R 2 R 3 R 5 B 5 R 1 VD 12 R 1 R 2 R 4 B 4 R 0 VD 11 R 0 R 1 R 3 B 3 G 5 VD 10 G 5 R 0 R 2 B 2 G 4 VD 9 G 4 G 5 R 1 B 1 G 3 VD 8 G 3 G 4 R 5 G 2 R 0 B 0 G 2 VD 7 G 2 G 3 R 4 G 1 G 7 G 1 R 4 G 2 VD 6 G 1 G 2 R 3 G 0 G 6 G 0 R 3 G 1 VD 5 G 0 G 1 R 2 B 5 G 5 B 5 R 2 G 0 VD 4 B 4 G 0 R 1 B 4 G 4 B 4 R 1 B 4 VD 3 B 3 B 5 R 0 B 3 G 3 B 3 R 0 B 3 VD 2 B 2 ...

Page 1168: ...ecifies window position setting 9 VIDOSDxC D Specifies OSD size setting 10 VIDWxALPHA0 1 Specifies alpha value setting 11 BLENDEQx Specifies blending equation setting 12 VIDWxxADDx Specifies source image address setting 13 WxKEYCONx Specifies color key setting register 14 WxKEYALPHA Specifies color key alpha value setting 15 WINxMAP Specifies window color control 16 GAMMALUT_xx Specifies gamma val...

Page 1169: ...INCON4 0xF800_0030 R W Specifies window control 4 register 0x0000_0000 SHADOWCON 0xF800_0034 R W Specifies window shadow control register 0x0000_0000 VIDOSD0A 0xF800_0040 R W Specifies video window 0 s position control register 0x0000_0000 VIDOSD0B 0xF800_0044 R W Specifies video window 0 s position control register 0x0000_0000 VIDOSD0C 0xF800_0048 R W Specifies video window 0 s size control regis...

Page 1170: ... Window 1 s buffer start address register buffer 1 0x0000_0000 VIDW01ADD0B2 0xF800_20A8 R W Specifies Window 1 s buffer start address register buffer 2 0x0000_0000 VIDW02ADD0B0 0xF800_00B0 R W Specifies Window 2 s buffer start address register buffer 0 0x0000_0000 VIDW02ADD0B1 0xF800_00B4 R W Specifies Window 2 s buffer start address register buffer 1 0x0000_0000 VIDW02ADD0B2 0xF800_20B0 R W Speci...

Page 1171: ...B2 0xF800_20E8 R W Specifies window 3 s buffer end address register buffer 2 0x0000_0000 VIDW04ADD1B0 0xF800_00F0 R W Specifies window 4 s buffer end address register buffer 0 0x0000_0000 VIDW04ADD1B1 0xF800_00F4 R W Specifies window 4 s buffer end address register buffer 1 0x0000_0000 VIDW04ADD1B2 0xF800_20F0 R W Specifies window 4 s buffer end address register buffer 2 0x0000_0000 VIDW00ADD2 0xF...

Page 1172: ...90 R W Specifies window 4 s color control 0x0000_0000 WPALCON_H 0xF800_019c R W Specifies window palette control register 0x0000_0000 WPALCON_L 0xF800_01A0 R W Specifies window palette control register 0x0000_0000 TRIGCON 0xF800_01A4 R W Specifies i80 RGB trigger control register 0x0000_0000 I80IFCONA0 0xF800_01B0 R W Specifies i80 interface control 0 for main LDI 0x0000_0000 I80IFCONA1 0xF800_01B...

Page 1173: ...lue 1 register 0x0000_0000 BLENDEQ1 0xF800_0244 R W Specifies window 1 s blending equation control register 0x0000_00c2 BLENDEQ2 0xF800_0248 R W Specifies window 2 s blending equation control register 0x0000_00c2 BLENDEQ3 0xF800_024c R W Specifies window 3 s blending equation control register 0x0000_00c2 BLENDEQ4 0xF800_0250 R W Specifies window 4 s blending equation control register 0x0000_00c2 B...

Page 1174: ... W Specifies Gamma LUT data of the index 8 9 0x0090_0080 GAMMALUT_11_ 10 0xF800_0390 R W Specifies Gamma LUT data of the index 10 11 0x00b0_00a0 GAMMALUT_13_ 12 0xF800_0394 R W Specifies Gamma LUT data of the index 12 13 0x00d0_00c0 GAMMALUT_15_ 14 0xF800_0398 R W Specifies Gamma LUT data of the index 14 15 0x00f0_00e0 GAMMALUT_17_ 16 0xF800_039C R W Specifies Gamma LUT data of the index 16 17 0x0...

Page 1175: ...xF800_03e4 R W Specifies Gamma LUT data of the index 52 53 0x0350_0340 GAMMALUT_55_ 54 0xF800_03e8 R W Specifies Gamma LUT data of the index 54 55 0x0370_0360 GAMMALUT_57_ 56 0xF800_03ec R W Specifies Gamma LUT data of the index 56 57 0x0390_0380 GAMMALUT_59_ 58 0xF800_03f0 R W Specifies Gamma LUT data of the index 58 59 0x03b0_03a0 GAMMALUT_61_ 60 0xF800_03f4 R W Specifies Gamma LUT data of the i...

Page 1176: ...fies window 3 s buffer end address register shadow 0x0000_0000 SHD_VIDW04AD D1 0xF800_40F0 R Specifies window 4 s buffer end address register shadow 0x0000_0000 SHD_VIDW00AD D2 0xF800_4100 R Specifies window 0 s buffer size register shadow 0x0000_0000 SHD_VIDW01AD D2 0xF800_4104 R Specifies window 1 s buffer size register shadow 0x0000_0000 SHD_VIDW02AD D2 0xF800_4108 R Specifies window 2 s buffer...

Page 1177: ... 255 entry palette data Undefined Win1 PalRam 0xF800_2800 0xF800_0800 0xF800_2BFC 0xF800_0BFC R W Specifies 0 255 entry palette data Undefined Win2 PalRam 0xF800_2C00 0xF800_2FFC R W Specifies 0 255 entry palette data Undefined Win3 PalRam 0xF800_3000 0xF800_33FC R W Specifies 0 255 entry palette data Undefined Win4 PalRam 0xF800_3400 0xF800_37FC R W Specifies 0 255 entry palette data Undefined ...

Page 1178: ...IDOUT 1 0 2 b11 000 16 bit mode 16 bpp 001 16 2 bit mode 18 bpp 010 9 9 bit mode 18 bpp 011 16 8 bit mode 24 bpp 100 18 bit mode 18bpp 101 8 8 bit mode 16bpp 000 L0_DATA16 22 20 Selects output data format mode of indirect i80 interface LDI0 VIDOUT 1 0 2 b10 000 16 bit mode 16 bpp 001 16 2 bit mode 18 bpp 010 9 9 bit mode 18 bpp 011 16 8 bit mode 24 bpp 100 18 bit mode 18bpp 101 8 8 bit mode 16bpp ...

Page 1179: ...lock for display controller For more information refer to Chapter 02 03 CLOCK CONTROLLER 0 ENVID 1 Enables disables video output and logic immediately 0 Disables the video output and display control signal 1 Enables the video output and display control signal 0 ENVID_F 0 Enables disables video output and logic at current frame end 0 Disables the video output and display control signal 1 Enables th...

Page 1180: ...NC 01 BACK Porch 10 ACTIVE 11 FRONT Porch 0 Reserved 12 11 Reserved 0 FIXVCLK 10 9 Specifies the VCLK hold scheme at data under flow 00 VCLK hold 01 VCLK running 11 VCLK running and VDEN disable 0 Reserved 8 Reserved 0 IVCLK 7 Controls the polarity of the VCLK active edge 0 Video data is fetched at VCLK falling edge 1 Video data is fetched at VCLK rising edge 0 IHSYNC 6 Specifies the HSYNC pulse p...

Page 1181: ...y insertion mode only where RGBSPSEL 1 b1 0 Disables 1 Enables 0 Reserved 23 22 Reserved should be 0 0 RGB_ORDER_E 21 19 Controls RGB interface output order Even line line 2 4 6 8 where RGBSPSEL 1 b0 000 RGB 001 GBR 010 BRG 100 BGR 101 RBG 110 GRB where RGBSPSEL 1 b1 or RGBSPSEL 1 b0 and RGB_SKIP_EN 1 b1 000 RÆGÆB 001 GÆBÆR 010 BÆRÆG 100 BÆGÆR 101 RÆBÆG 110 GÆRÆB Note PNR0 0 VIDCON0 should be 0 wh...

Page 1182: ...at of YUV data 00 Reserved 01 YUV422 1x YUV444 0 Reserved 11 9 Reserved 0 OrgYCbCr 8 Specifies the order of YUV data 0 Y CbCr 1 CbCr Y 0 YUVOrd 7 Specifies the order of Chroma data 0 Cb Cr 1 Cr Cb 0 Reserved 6 5 Reserved 0 WB_FRAME_SKIP 4 0 Controls the WB frame skip rate The maximum rate is up to 1 30 only where VIDOUT 2 0 3 b001 or 3 b100 TV encoder interface INTERLACE_F 1 b0 and TV422 or TVRGB ...

Page 1183: ...ow 0 HUE_CSC_F_EQ709 13 Controls HUE_CSC_F parameter 0 Eq 601 1 Eq 709 0 HUE_CSC_F_ON 12 Enables HUE_CSC_F 0 Disables 1 Enables when HUE_ON 1 b1 0 Reserved 11 Reserved 0 HUE_CSC_B_Narrow 10 Controls HUE CSC_B Narrow Wide 0 Wide 1 Narrow 0 HUE_CSC_B_EQ709 9 Controls HUE_CSC_B parameter 0 Eq 601 1 Eq 709 0 HUE_CSC_B_ON 8 Enables HUE_CSC_B 0 Disables 1 Enables when HUE_ON 1 b1 0 HUE_ON 7 Enables Cont...

Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...

Page 1185: ...VSPW 7 0 Vertical sync pulse width determines the high level width of VSYNC pulse by counting the number of inactive lines 0x00 1 5 2 6 Video Time Control 1 Register VIDTCON1 R W Address 0xF800_0014 VIDTCON1 Bit Description Initial State VFPDE 31 24 Vertical front porch specifies the number of inactive lines at the end of a frame before vertical synchronization period Only for the even field of YV...

Page 1186: ...ON3 R W Address 0xF800_001C VIDTCON3 Bit Description Initial State VSYNCEN 31 Enables VSYNC Signal Output 0 Disables 1 Enables VBPD VFPD VSPW 1 LINEVAL when VSYNCEN 1 0 Reserved 30 Reserved should be 0 0 FRMEN 29 Enables the FRM signal output 0 Disables 1 Enables 0 INVFRM 28 Controls the polarity of FRM pulse 0 Active HIGH 1 Active LOW 0 FRMVRATE 27 24 Controls the FRM issue rate Maximum rate up t...

Page 1187: ...arrow 27 26 Chooses the color space conversion equation from YCbCr to RGB according to input value range 2 00 for YCbCr Wide range and 2 11 for YCbCr Narrow range Wide Range Y Cb Cr 255 0 Narrow Range Y 235 16 Cb Cr 240 16 00 TRGSTATUS 25 Specifies the Trigger Status read only 0 No trigger is issued 1 Trigger is issued 0 Reserved 24 23 Reserved 00 ENLOCAL_F 22 Selects the Data access method 0 Dedi...

Page 1188: ... 4 word burst 0 Reserved 8 7 0 BLD_PIX_F 6 Selects the blending category In case of window0 this is only required for deciding window 0 s blending factor 0 Per plane blending 1 Per pixel blending 0 BPPMODE_F 5 2 Selects the Bits Per Pixel BPP mode for Window image 0000 1 bpp 0001 2 bpp 0010 4 bpp 0011 8 bpp palletized 0100 8 bpp non palletized A 1 R 2 G 3 B 2 0101 16 bpp non palletized R 5 G 6 B 5...

Page 1189: ...ding ALPHA_SEL_F 1 Selects the Alpha value When per plane blending case BLD_PIX 0 0 Using ALPHA0_R G B values 1 Using ALPHA1_R G B values When per pixel blending BLD_PIX 1 0 Selected by AEN A value 1 Using DATA 31 24 data in word boundary only when BPPMODE_F 4 b1101 DATA 31 28 15 12 data in word boundary only when BPPMODE_F 4 b1110 0 ENWIN_F 0 Enables disables video output and logic immediately 0 ...

Page 1190: ... the color space conversion equation from YCbCr to RGB based on input value range 2 00 for YCbCr Wide range and 2 11 for YCbCr Narrow range Wide Range Y Cb Cr 255 0 Narrow Range Y 235 16 Cb Cr 240 16 00 TRGSTATUS 25 Specifies Window 0 Software Trigger Update Status read only 0 Update 1 Not Update If the Software Trigger in window 1 occurs this bit is automatically set to 1 This value is cleared on...

Page 1191: ...Lcal enable 0 RGB 1 YCbCr 0 12 11 Reserved should be 0 0 BURSTLEN 10 9 Specifies the DMA s Burst Maximum Length selection 00 16 word burst 01 8 word burst 10 4 word burst 0 8 Reserved should be 0 0 ALPHA_MUL_F 7 Specifies the Multiplied Alpha value mode 0 Disables 1 Enables multiplied mode When ALPHA_MUL is 1 set BLD_PIX 1 ALPHA_SEL 1 and BPPMODE_F 5 2 4 b1101 or 4 b1110 Note Alpha value alpha_pix...

Page 1192: ... Note 1101 supports unpacked 32 bpp non palletized A 8 R 8 G 8 B 8 for per pixel blending 1110 supports 16 bpp non palletized A 4 R 4 G 4 B 4 for per pixel blending 16 level blending ALPHA_SEL_F 1 Selects the Alpha value When Per plane blending case BLD_PIX 0 0 Using ALPHA0_R G B values 1 Using ALPHA1_R G B values When Per pixel blending BLD_PIX 1 0 Selected by AEN A value 1 Using DATA 31 24 data ...

Page 1193: ...ut 0 nWide Narrow 27 26 Chooses color space conversion equation from YCbCr to RGB based on the input value range 2 00 for YCbCr Wide range and 2 11 for YCbCr Narrow range Wide Range Y Cb Cr 255 0 Narrow Range Y 235 16 Cb Cr 240 16 00 Reserved 25 24 Reserved 00 Reserved 23 Should be 0 0 ENLOCAL_F 22 Selects the Data access method 0 Dedicated DMA 1 Local Path 0 BUFSTATUS_L 21 Specifies the Buffer St...

Page 1194: ... Alpha value mode 0 Disables 1 Enables multiplied mode When ALPHA_MUL is 1 set BLD_PIX 1 ALPHA_SEL 1 and BPPMODE_F 5 2 4 b1101 or 4 b1110 Note Alpha value alpha_pixel from data ALPHA0_R G B 0 BLD_PIX_F 6 Selects the blending category 0 Per plane blending 1 Per pixel blending 0 BPPMODE_F 5 2 Selects the Bits Per Pixel BPP mode in Window image 0000 1 bpp 0001 2 bpp 0010 4 bpp 0011 8 bpp palletized 0...

Page 1195: ...l blending 16 level blending ALPHA_SEL_F 1 Selects the Alpha value When Per plane blending case BLD_PIX 0 0 Using ALPHA0_R G B values 1 Using ALPHA1_R G B values When Per pixel blending BLD_PIX 1 0 Selected by AEN A value 1 Using DATA 31 24 data in word boundary only when BPPMODE_F 4 b1101 DATA 31 28 15 12 data in word boundary only when BPPMODE_F 4 b1110 0 ENWIN_F 0 Enables disables the video out...

Page 1196: ...e 0 BUFSTATUS_L 21 Specifies the Buffer Status read only Note BUFSTATUS BUFSTATUS_H BUFSTATUS_L BUFSEL_L 20 Selects the Buffer set Note BUFSEL BUFSEL_H BUFSEL_L BUFAUTOEN 19 Specifies the Double Buffer Auto control bit 0 Fixed by BUFSEL 1 Auto changed by Trigger Input BITSWP_F 18 Specifies the Bit swap control bit 0 Swap Disable 1 Swap Enable 0 BYTSWP_F 17 Specifies the Byte swaps control bit 0 Sw...

Page 1197: ... G 6 B 5 1010 Unpacked 19 bpp non palletized A 1 R 6 G 6 B 6 1011 Unpacked 24 bpp non palletized R 8 G 8 B 8 1100 Unpacked 24 bpp non palletized A 1 R 8 G 8 B 7 1101 Unpacked 25 bpp non palletized A 1 R 8 G 8 B 8 1110 Unpacked 13 bpp non palletized A 1 R 4 G 4 B 4 1111 Unpacked 15 bpp non palletized R 5 G 5 B 5 Note 1101 Supports unpacked 32 bpp non palletized A 8 R 8 G 8 B 8 for per pixel blendin...

Page 1198: ...hould be 00 0 BUFSTATUS_L 21 Specifies the Buffer Status read only Note BUFSTATUS BUFSTATUS_H BUFSTATUS_L 0 BUFSEL_L 20 Selects the Buffer set Note BUFSEL BUFSEL_H BUFSEL_L 0 BUFAUTOEN 19 Specifies the Double Buffer Auto control bit 0 Fixed by BUFSEL 1 Auto changed by Trigger Input 0 BITSWP_F 18 Specifies the Bit swap control bit 0 Swap Disable 1 Swap Enable 0 BYTSWP_F 17 Specifies the Byte swap c...

Page 1199: ...ed A 1 R 6 G 6 B 5 1010 Unpacked 19 bpp non palletized A 1 R 6 G 6 B 6 1011 Unpacked 24 bpp non palletized R 8 G 8 B 8 1100 Unpacked 24 bpp non palletized A 1 R 8 G 8 B 7 1101 Unpacked 25 bpp non palletized A 1 R 8 G 8 B 8 1110 Unpacked 13 bpp non palletized A 1 R 4 G 4 B 4 1111 Unpacked 15 bpp non palletized R 5 G 5 B 5 Note 1101 Support unpacked 32 bpp non palletized A 8 R 8 G 8 B 8 for per pixe...

Page 1200: ...egister at next frame after SHADOW_PROTECT turns to be 1 b0 0 W1_SHADOW _PROTECT 11 Protects to update window 1 s shadow register xxx_F 0 Updates shadow register per frame 1 Protects to update update shadow register at next frame after SHADOW_PROTECT turns to be 1 b0 0 W0_SHADOW _PROTECT 10 Protects to update window 0 s shadow register xxx_F 0 Updates shadow register per frame 1 Protects to update...

Page 1201: ...nnel 2 s channel 001 Window 0 010 Window 1 101 Window 2 110 Window 3 111 Window 4 101 CH1FISEL 21 19 Selects Channel 1 s channel 001 Window 0 010 Window 1 101 Window 2 110 Window 3 111 Window 4 010 CH0FISEL 18 16 Selects Channel 0 s channel 001 Window 0 010 Window 1 101 Window 2 110 Window 3 111 Window 4 001 W4FISEL 14 12 Selects Window 4 s channel 001 Channel 0 010 Channel 1 101 Channel 2 110 Cha...

Page 1202: ...el 1 101 Channel 2 110 Channel 3 111 Channel 4 001 1 5 2 16 Window 0 Position Control A Register VIDOSD0A R W Address 0xF800_0040 VIDOSD0A Bit Description Initial State OSD_LeftTopX_F 21 11 Specifies the horizontal screen coordinate for left top pixel of OSD image 0 OSD_LeftTopY_F 10 0 Specifies the vertical screen coordinate for left top pixel of OSD image For interlace TV output this value must ...

Page 1203: ... 1 2 3 16 BPP mode must have X position by 2 pixel For example X 0 2 4 6 8 BPP mode must have X position by 4 pixel For example X 0 4 8 12 1 5 2 18 Window 0 Position Control C Register VIDOSD0C R W Address 0xF800_0048 VIDOSD0C Bit Description Initial State Reserved 25 24 Reserved should be 0 0 OSDSIZE 23 0 Specifies the Window Size For example Height Width Number of Word 0 1 5 2 19 Window 1 Positi...

Page 1204: ...xample X 0 2 4 6 8 BPP mode must have X position by 4 pixel For example X 0 4 8 12 1 5 2 21 Window 1 Position Control C Register VIDOSD1C R W Address 0xF800_0058 VIDOSD1C Bit Description Initial State Reserved 24 Reserved 0 ALPHA0_R_H_F 23 20 Specifies Red Alpha upper value case AEN 0 0 ALPHA0_G_H_F 19 16 Specifies Green Alpha upper value case AEN 0 0 ALPHA0_B_H_F 15 12 Specifies Blue Alpha upper ...

Page 1205: ...e For interlace TV output this value must be set to half of the original screen y coordinate The original screen y coordinate must be odd value 0 NOTE Registers must have word boundary X position Therefore 24 BPP mode must have X position by 1 pixel For example X 0 1 2 3 16 BPP mode must have X position by 2 pixel For example X 0 2 4 6 8 BPP mode must have X position by 4 pixel For example X 0 4 8...

Page 1206: ... be set to half of the original screen y coordinate The original screen y coordinate must be even value 0 1 5 2 28 Window 3 Position Control B Register VIDOSD3B R W Address 0xF800_0074 VIDOSD3B Bit Description Initial State OSD_RightBotX_F 21 11 Specifies the Horizontal screen coordinate for right bottom pixel of OSD image 0 OSD_RightBotY_F 10 0 Specifies the Vertical screen coordinate for right b...

Page 1207: ... screen coordinate for left top pixel of OSD image 0 OSD_LeftTopY_F 10 0 Specifies the Vertical screen coordinate for left top pixel of OSD image For interlace TV output this value must be set to half of the original screen y coordinate The original screen y coordinate MUST be even value 0 1 5 2 31 Window 4 Position Control B Register VIDOSD4B R W Address 0xF800_0084 VIDOSD4B Bit Description Initi...

Page 1208: ...EN 1 0 NOTE For more information refer to VIDW4ALPHA0 1 register 1 5 2 33 Frame Buffer Address 0 Register VIDW VIDW00ADD0B0 R W Address 0xF800_00A0 VIDW00ADD0B1 R W Address 0xF800_00A4 VIDW00ADD0B2 R W Address 0xF800_20A0 VIDW01ADD0B0 R W Address 0xF800_00A8 VIDW01ADD0B1 R W Address 0xF800_00AC VIDW01ADD0B2 R W Address 0xF800_20A8 VIDW02ADD0B0 R W Address 0xF800_00B0 VIDW02ADD0B1 R W Address 0xF80...

Page 1209: ...0_20D8 VIDW02ADD1B0 R W Address 0xF800_00E0 VIDW02ADD1B1 R W Address 0xF800_00E4 VIDW02ADD1B2 R W Address 0xF800_20E0 VIDW03ADD1B0 R W Address 0xF800_00E8 VIDW03ADD1B1 R W Address 0xF800_00EC VIDW03ADD1B2 R W Address 0xF800_20E8 VIDW04ADD1B0 R W Address 0xF800_00F0 VIDW04ADD1B1 R W Address 0xF800_00F4 VIDW04ADD1B2 R W Address 0xF800_20F0 VIDWxxADD1 Bit Description Initial State VBASEL_F 31 0 Speci...

Page 1210: ...r value than the burst size and the size must be aligned word boundary 0 NOTE PAGEWIDTH OFFSET should be aligned double word aligned 8 byte 1 5 2 36 Video Interrupt Control 0 Register VIDINTCON0 R W Address 0xF800_0130 VIDINTCON0 Bit Description Initial State Reserved 31 26 Reserved 0 FIFOINTERVAL 25 20 Controls the interval of the FIFO interrupt 0 SYSMAINCON 19 Sends complete interrupt enable bit...

Page 1211: ...0 FIFOLEVEL 4 2 Selects the Video FIFO Interrupt Level 000 0 25 001 0 50 010 0 75 011 0 empty 100 100 full 0 INTFIFOEN 1 Specifies the Video FIFO Interrupt Enable Control Bit 0 Disables Video FIFO Level Interrupt 1 Enables Video FIFO Level Interrupt Note This bit is meaningful if INTEN is high 0 INTEN 0 Specifies the Video Interrupt Enable Control Bit 0 Disables Video Interrupt 1 Enables Video Int...

Page 1212: ...F800_0140 W1KEYCON0 Bit Description Initial State KEYBLEN_F 26 Enables blending 0 Disables blending 1 Enables blending using original Alpha for non key area and KEY_ALPHA for key area 0 KEYEN_F 25 Enables Disables Color Key Chroma key 0 Disables color key 1 Enables color key 0 DIRCON_F 24 Controls color key Chroma key direction 0 If the pixel value matches foreground image with COLVAL the pixel fr...

Page 1213: ...l value matches foreground image with COLVAL the pixel from background image is displayed only in OSD area 1 If the pixel value matches background image with COLVAL the pixel from foreground image is displayed only in OSD area 0 COMPKEY_F 23 0 Each bit corresponds to COLVAL 23 0 If some position bit is set then it disables the position bit of COLVAL 0 NOTE Set BLD_PIX 1 ALPHA_SEL 0 A_FUNC 0x2 and ...

Page 1214: ...alpha blending using color key 1 5 2 43 Win3 Color key 1 Register W3KEYCON1 R W Address 0xF800_0154 W3KEYCON1 Bit Description Initial State COLVAL_F 23 0 Specifies the color key value for transparent pixel effect 0 1 5 2 44 Win4 Color Key 0 Register W4KEYCON0 R W Address 0xF800_0158 W4KEYCON0 Bit Description Initial State KEYBLEN_F 26 Enables blending 0 Disables blending 1 Enables blending using o...

Page 1215: ...r data in all BPP modes BPP24 mode 24 bit color value is valid A COLVAL Red COLVAL 23 17 Green COLVAL 15 8 Blue COLVAL 7 0 B COMPKEY Red COMPKEY 23 17 Green COMPKEY 15 8 Blue COMPKEY 7 0 BPP16 5 6 5 mode 16 bit color value is valid A COLVAL Red COLVAL 23 19 Green COLVAL 15 10 Blue COLVAL 7 3 B COMPKEY Red COMPKEY 23 19 Green COMPKEY 15 10 Blue COMPKEY 7 3 COMPKEY 18 16 must be 0x7 COMPKEY 9 8 must...

Page 1216: ...y alpha R value 0 KEYALPHA_G_F 15 8 Specifies the Key alpha G value 0 KEYALPHA_B_F 7 0 Specifies the Key alpha B value 0 1 5 2 48 Win3 Color Key ALPHA Control Register W3KEYALPHA R W Address 0xF800_0168 W3KEYALPHA Bit Description Initial State 31 14 Reserved 0 KEYALPHA_R_F 23 0 Specifies the Key alpha R value 0 KEYALPHA_G_F 15 8 Specifies the Key alpha G value 0 KEYALPHA_B_F 7 0 Specifies the Key ...

Page 1217: ...es dithering 1 Enables dithering 0 1 5 2 51 Win0 Color MAP WIN0MAP R W Address 0xF800_0180 WIN0MAP Bit Description Initial State MAPCOLEN_F 24 Specifies window s color mapping control bit If this bit is enabled then Video DMA stops and MAPCOLOR appears on background image instead of original image 0 Disables 1 Enables 0 MAPCOLOR 23 0 Specifies the color value 0 1 5 2 52 Win1 Color MAP WIN1MAP R W ...

Page 1218: ...MA stops and MAPCOLOR appears on background image instead of original image 0 Disables 1 Enables 0 MAPCOLOR 23 0 Specifies the color value 0 1 5 2 55 Win4 Color MAP WIN4MAP R W Address 0xF800_0190 WIN4MAP Bit Description Initial State MAPCOLEN_F 24 Specifies the window s color mapping control bit If this bit is enabled then Video DMA stops and MAPCOLOR appears on background image instead of origin...

Page 1219: ...alette Update 0 W4PAL 3 0 Specifies the size of palette data format of Window 4 000 16 bit 5 6 5 001 16 bit A 5 5 5 010 18 bit 6 6 6 011 18 bit A 6 6 5 100 19 bit A 6 6 6 101 24 bit 8 8 8 110 25 bit A 8 8 8 111 32 bit 8 8 8 8 A 8 bit 0 W3PAL 2 0 Specifies the size of palette data format of Window 3 000 16 bit 5 6 5 001 16 bit A 5 5 5 010 18 bit 6 6 6 011 18 bit A 6 6 5 100 19 bit A 6 6 6 101 24 bi...

Page 1220: ... 8 8 010 19 bit A 6 6 6 011 18 bit A 6 6 5 100 18 bit 6 6 6 101 16 bit A 5 5 5 110 16 bit 5 6 5 111 32 bit 8 8 8 8 A 8 bit 0 W0PAL 2 0 Specifies the size of palette data format of Window 0 000 25 bit A 8 8 8 001 24 bit 8 8 8 010 19 bit A 6 6 6 011 18 bit A 6 6 5 100 18 bit 6 6 6 101 16 bit A 5 5 5 110 16 bit 5 6 5 111 32 bit 8 8 8 8 A 8 bit 0 NOTE The bit map for W0 W1 is different from W2 W3 W4 ...

Page 1221: ...bles Trigger 1 Enables Trigger 0 Reserved 19 17 Reserved 0 SWTRGCMD_W2BUF 16 Specifies Window 2 double buffer trigger 1 Enables Software Trigger Command write only Only when TRGMODE_W2BUF is 1 0 TRGMODE_W2BUF 15 Specifies Window 2 double buffer trigger 0 Disables Trigger 1 Enables Trigger 0 Reserved 14 12 Reserved 0 SWTRGCMD_W1BUF 11 Specifies Window 1 double buffer trigger 1 Enables Software Trig...

Page 1222: ... Clear Condition Read or New Frame Start Only when TRGMODE is 1 0 SWTRGCMD_I80 1 Enables I80 start trigger 1 Software Triggering Command write only Only when TRGMODE is 1 0 TRGMODE_I80 0 Enables I80 start trigger 0 Disables i80 Software Trigger 1 Enables i80 Software Trigger 0 NOTE Two continuous software trigger inputs generated in some video clocks VCLK are recognized as one ...

Page 1223: ...hip select enable 0 LCD_WR _SETUP 15 12 Specifies the numbers of clock cycles for the active period of CS signal enable to write signal enable 0 LCD_WR_ACT 11 8 Specifies the numbers of clock cycles for the active period of chip select enable 0 LCD_WR _HOLD 7 4 Specifies the numbers of clock cycles for the active period of chip select disable to write signal disable 0 Reserved 3 Reserved RSPOL 2 S...

Page 1224: ...MAL_CMD_ST 9 1 Normal Command Start Auto clears after sending out one set of commands 0 Reserved 8 7 Reserved FRAME_SKIP 6 5 Specifies the I80 Interface Output Frame Decimation Factor 00 1 No Skip 01 2 10 3 00 Reserved 4 Reserved 0 AUTO_CMD_RATE 3 0 0000 Disables auto command If you don t use any auto command then you should set AUTO_CMD_RATE as 0000 0001 per 2 Frames 0010 per 4 Frames 0011 per 6 ...

Page 1225: ...0625 1 256 0h002 0 0078125 2 256 0h0FF 0 99609375 255 256 0h100 1 0 0x3FF 3 99609375 max 0x100 CG_GGAIN 19 10 Specifies the color gain value of G data maximum 4 8 bit resolution 0h000 0 0h001 0 00390625 1 256 0h002 0 0078125 2 256 0h0FF 0 99609375 255 256 0h100 1 0 0x3FF 3 99609375 max 0x100 CG_BGAIN 9 0 Specifies the color gain value of B data maximum 4 8 bit resolution 0h000 0 0h001 0 00390625 1...

Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...

Page 1227: ...s Normal and Auto Command 00 CMD7_EN 15 14 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command 00 CMD6_EN 13 12 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command 00 CMD5_EN 11 10 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command 00 CMD4_EN 9 8 00 Disables 01 En...

Page 1228: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 117 LDI_CMDCON0 Bit Description Initial State CMD0_EN 1 0 00 Disables 01 Enables Normal Command 10 Enables Auto Command 11 Enables Normal and Auto Command 00 ...

Page 1229: ... Controls Command 11 RS 0 CMD10_RS 10 Controls Command 10 RS 0 CMD9_RS 9 Controls Command 9 RS 0 CMD8_RS 8 Controls Command 8 RS 0 CMD7_RS 7 Controls Command 7 RS 0 CMD6_RS 6 Controls Command 6 RS 0 CMD5_RS 5 Controls Command 5 RS 0 CMD4_RS 4 Controls Command 4 RS 0 CMD3_RS 3 Controls Command 3 RS 0 CMD2_RS 2 Controls Command 2 RS 0 CMD1_RS 1 Controls Command 1 RS 0 CMD0_RS 0 Controls Command 0 RS...

Page 1230: ...l 0 Disables High 1 Enables Low 0 SYS_nOE_CON 2 Controls LCD i80 System Interface nOE Signal 0 Disables High 1 Enables Low 0 SYS_nWE_CON 1 Controls LCD i80 System Interface nWE Signal 0 Disables High 1 Enables Low 0 SCOMEN 0 Enables LCD i80 System Interface Command Mode 0 Disables Normal Mode 1 Enables Manual Command Mode 1 5 2 65 I80 System Interface Manual Command Control 1 SIFCCON1 R W Address ...

Page 1231: ...cient 00 when cb In_offset is positive Signed 0h000 0 0h001 0 00390625 1 256 0h002 0 0078125 2 256 0h0FF 0 99609375 255 256 0h100 1 0 256 256 0h300 1 0 256 256 0h301 0 99609375 255 256 0h3FF 0 00390625 1 256 0h101 2FF Reserved don t use 0x100 15 10 Reserved 0 CBGx_N 9 0 Specifies the Hue matrix coefficient 00 when cb In_offset is negative Signed 0h000 0 0h001 0 00390625 1 256 0h002 0 0078125 2 256...

Page 1232: ...256 0x1FF 1 0x180 128 15 9 Reserved 0 OFFSET_OUT 8 0 Specifies the Hue matrix output offset signed 0h000 0 0h001 1 0h002 2 0h0FF 255 0h100 256 0x1FF 1 0x080 128 NOTE Generally HUE_OFFSET_IN 128 and HUE_OFFSET_OUT 128 Hue Equation Cb hue CBG0 Cb OFFSET_IN CBG1 Cr OFFSET_IN OFFSET_OUT Cr hue CRG0 Cb OFFSET_IN CRG1 Cr OFFSET_IN OFFSET_OUT Coefficient Decision CBG0 Cb 128 0 CBG0_P CBG0_N CBG1 Cr 128 0...

Page 1233: ... Reserved 0 ALPHA1_R_F 23 16 Specifies the Red Alpha value case AEN 1 0 ALPHA1_G_F 15 8 Specifies the Green Alpha value case AEN 1 0 ALPHA1_B_F 7 0 Specifies the Blue Alpha value case AEN 1 0 1 5 2 71 Window 1 Alpha0 control Register VIDW1ALPHA0 R W Address 0xF800_0208 VIDW1ALPHA0 Bit Description Initial State Reserved 24 Reserved 0 Reserved 23 20 Reserved 0 ALPHA0_R_L_F 19 16 Specifies the Red Al...

Page 1234: ... Reserved 0 Reserved 23 20 Reserved 0 ALPHA0_R_L_F 19 16 Specifies the Red Alpha lower value case AEN 0 0 15 12 Reserved 0 ALPHA0_G_L_F 11 8 Specifies the Green Alpha lower value case AEN 0 0 7 4 Reserved 0 ALPHA0_B_L_F 3 0 Specifies the Blue Alpha lower value case AEN 0 0 NOTE ALPHA0_R G B 7 4 ALPHA0_R G B _H 3 0 VIDOSD2C ALPHA0_R G B 3 0 ALPHA0_R G B _L 3 0 VIDW2ALPHA0 1 5 2 74 Window 2 Alpha1 c...

Page 1235: ...Reserved 0 Reserved 23 16 Reserved 0 ALPHA1_R_L_F 19 16 Specifies the Red Alpha lower value case AEN 1 0 15 12 Reserved 0 ALPHA1_G_L_F 11 8 Specifies the Green Alpha lower value case AEN 1 0 7 4 Reserved 0 ALPHA1_B_L_F 3 0 Specifies the Blue Alpha lower value case AEN 1 0 NOTE ALPHA1_R G B 7 4 ALPHA1_R G B _H 3 0 VIDOSD3C ALPHA1_R G B 3 0 ALPHA1_R G B _L 3 0 VIDW3ALPHA1 1 5 2 77 Window 4 Alpha0 Co...

Page 1236: ... Reserved 0 Reserved 23 20 Reserved 0 ALPHA1_R_L_F 19 16 Specifies the Red Alpha lower value case AEN 1 0 15 12 Reserved 0 ALPHA1_G_L_F 11 8 Specifies the Green Alpha lower value case AEN 1 0 7 4 Reserved 0 ALPHA1_B_L_F 3 0 Specifies the Blue Alpha lower value case AEN 1 0 NOTE ALPHA1_R G B 7 4 ALPHA1_R G B _H 3 0 VIDOSD4C ALPHA1_R G B 3 0 ALPHA1_R G B _L 3 0 VIDW4ALPHA1 ...

Page 1237: ...ed 100x Reserved 1010 A foreground color data 1011 1 A 1100 B background color data 1101 1 B 111x Reserved 0x0 17 16 Reserved 00 P_FUNC_F 15 12 Specifies the constant used in alpha Same as above see COEF_Q 0x0 11 10 Reserved 00 B_FUNC_F 9 6 Specifies the constant used in B Same as above see COEF_Q 0x3 5 4 Reserved 00 A_FUNC_F 3 0 Specifies the constant used in A Same as above see COEF_Q 0x2 NOTE F...

Page 1238: ...d 100x Reserved 1010 A foreground color data 1011 1 A 1100 B background color data 1101 1 B 111x Reserved 0x0 17 16 Reserved 00 P_FUNC_F 15 12 Specifies the constant used in alpha Same as above see COEF_Q 0x0 11 10 Reserved 00 B_FUNC_F 9 6 Specifies the constant used in B Same as above see COEF_Q 0x3 5 4 Reserved 00 A_FUNC_F 3 0 Specifies the constant used in A Same as above see COEF_Q 0x2 NOTE Fo...

Page 1239: ...d 100x Reserved 1010 A foreground color data 1011 1 A 1100 B background color data 1101 1 B 111x Reserved 0x0 17 16 Reserved 00 P_FUNC_F 15 12 Specifies the constant used in alpha Same as above see COEF_Q 0x0 11 10 Reserved 00 B_FUNC_F 9 6 Specifies the constant used in B Same as above see COEF_Q 0x3 5 4 Reserved 00 A_FUNC_F 3 0 Specifies the constant used in A Same as above see COEF_Q 0x2 NOTE Fo...

Page 1240: ...eserved 00 P_FUNC_F 15 12 Specifies the constant used in alpha Same as above see COEF_Q 0x0 11 10 Reserved 00 B_FUNC_F 9 6 Specifies the constant used in B Same as above see COEF_Q 0x3 5 4 Reserved 00 A_FUNC_F 3 0 Specifies the constant used in A Same as above see COEF_Q 0x2 NOTE For more information refer to Figure 1 5 Blending equation background Window 0123 foreground Window 4 in Blend Equation...

Page 1241: ...OS_GATE_DIS 1 Disables the RTQoS output signal gate 0 Gated 1 Not gated 0 0 Reserved should be 0 0 1 5 2 85 Write Back Control Registers WRITEBACK Bit Description Initial State WRITEBACK_EN 31 Write Back enable 0 disable 1 enable 0 1 5 2 86 LCD I80 Interface Command I80IFCONx LDI_CMD0 R W Address 0xF800_0280 LDI_CMD1 R W Address 0xF800_0284 LDI_CMD2 R W Address 0xF800_0288 LDI_CMD3 R W Address 0xF...

Page 1242: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 131 I80IFCONx Bit Description Initial State LDI_CMD 23 0 Specifies the LDI command 0 ...

Page 1243: ..._0804 R W Specifies the Window 1 Palette entry 1 address undefined FF 0xF800_2BFC 0xF800_0BFC R W Specifies the Window 1 Palette entry 255 address undefined 1 5 2 89 Win2 Palette Ram Access Address not SFR Register Address R W Description Initial State 00 0xF800_2C00 R W Specifies the Window 2 Palette entry 0 address undefined 01 0xF800_2C04 R W Specifies the Window 2 Palette entry 1 address undef...

Page 1244: ...address undefined 1 5 2 92 Window RTQOS Control Registers W0RTQOSCON R W Address 0xF800_0264 W1RTQOSCON R W Address 0xF800_0268 W2RTQOSCON R W Address 0xF800_026C W3RTQOSCON R W Address 0xF800_0270 W4RTQOSCON R W Address 0xF800_0274 HUECOEF0x Bit Description Initial State 31 12 Reserved should be 0 0 FIFOLEVEL 11 4 Specifies the real time QoS FIFO level If FIFO depth is less than FIFOLEVEL 7 0 the...

Page 1245: ...29 0X01D0_01C0 GAMMALUT_31_30 0X003B8 R W Specifies the Gamma LUT data of the index 30 31 0X01F0_01E0 GAMMALUT_33_32 0X003BC R W Specifies the Gamma LUT data of the index 32 33 0X0210_0200 GAMMALUT_35_34 0X003C0 R W Specifies the Gamma LUT data of the index 34 35 0X0230_0220 GAMMALUT_37_36 0X003C4 R W Specifies the Gamma LUT data of the index 36 37 0X0250_0240 GAMMALUT_39_38 0X003C8 R W Specifies ...

Page 1246: ...04ADD0 R W Address 0xF800_40C0 SHD_VIDWxxADD0 Bit Description Initial State VBANK_F 31 24 Specifies A 31 24 of the bank location for video buffer in the system memory Shadow 0 VBASEU_F 23 0 Specifies A 23 0 of the start address for video frame buffer Shadow 0 1 5 3 2 Frame Buffer Address 1 Shadow Registers SHD_VIDW00ADD1 R W Address 0xF800_40D0 SHD_VIDW01ADD1 R W Address 0xF800_40D8 SHD_VIDW02ADD1...

Page 1247: ...DD2 R W Address 0xF800_40B0 SHD_VIDW03ADD2 R W Address 0xF800_40B8 SHD_VIDW04ADD2 R W Address 0xF800_40C0 SHD_VIDWxxADD2 Bit Description Initial State OFFSIZE_F 25 13 Specifies the Virtual screen offset size that is the number of byte Shadow 0 PAGEWIDTH_F 12 0 Specifies the Virtual screen page width number of byte This value defines the width of view port in the frame Shadow 0 ...

Page 1248: ... as shown in Figure 2 1 Each of these units is designed to perform different functions as shown in Figure 2 2 T_PatternMux generates test pattern to calibrate input sync signals as HREF and VSYNC Capture specifies the capturing signal and window cut Use the register settings to invert video sync signals and pixel clock polarity in CAMIF Scaler generates various sizes for an image Input DMA read on...

Page 1249: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 2 The key application of these features is in a folder type cellular phone Figure 2 1 Subset of Visual System in S5PC110 ...

Page 1250: ...fect Table 2 1 Maximum Size Maximum Size Item CAMIF0 CAMIF1 CAMIF2 Scaler input Hsize PreDstWidth 4224 pixels 4224 pixels 1920 pixels Scaler Scaler bypass mode 8192 pixels 8192 pixels 8192 pixels TargetHsize without output rotation 4224 pixels 4224 pixels 1920 pixels Output Rotator TargetHsize with output rotation 1920 pixels 1920 pixels 1280 pixels REAL_WIDTH without input rotation 8192 pixels 81...

Page 1251: ..._UM 2 1BCAMERA INTERFACE 2 4 Figure 2 2 Camera Interface Overview NOTE In case of Direct FIFO WriteBack input mode CAMIF does not support cropping capture frame control test pattern and scaler bypass function ...

Page 1252: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 5 2 3 EXTERNAL INTERFACE CAMIF supports three video standards namely ITU R BT 601 YCbCr 8 bit mode ITU R BT 656 YCbCr 8 bit mode MIPI mode ...

Page 1253: ...ed CAM_MCLK_ A O Specifies the Clock for external Camera processor A XciCLKenb Muxed External ITU Camera Processor B Interface Signal PCLK_B I Specifies the Pixel Clock driven by external Camera processor B XmsmADDR 8 Muxed VSYNC_B I Specifies the Frame Sync driven by external Camera processor B XmsmADDR 9 Muxed HREF_B I Specifies the Horizontal Sync driven by external Camera processor B XmsmADDR ...

Page 1254: ... 1 TIMING DIAGRAM OF ITU CAMERA Figure 2 3 ITU R BT 601 Input Timing Diagram ITU 601 VSYNC FIELD Field 1 Field 2 VSYNC HSYNC Field 1 Field 2 Delay cycle FieldMode 1 Field port connects with FIELD FieldMode 0 Field port connects with HSYNC Figure 2 4 ITU R BT 601 Interlace Handling Diagram ...

Page 1255: ...des of ITU 656 8 Bit Format Data Bit Number First Word Second Word Third Word Fourth Word 7 MSB 1 0 0 1 6 1 0 0 F 5 1 0 0 V 4 1 0 0 H 3 1 0 0 P3 2 1 0 0 P2 1 1 0 0 P1 0 1 0 0 P0 NOTE F 0 during field 1 1 during field 2 V 0 elsewhere 1 during field blanking H 0 in SAV Start of Active Video 1 in EAV End of Active Video P0 P1 P2 P3 Protection Bit The camera interface logic catches video sync bits lik...

Page 1256: ...orizontal Line t2 2 Cycles of Pixel Clock 5 Cycles of System Bus Clock t3 2 Cycles of Pixel Clock t4 12 Cycles of Pixel Clock NOTE If rotator is enabled then t4 t1 should be sufficient to finish DMA transactions since DMA transactions for rotator line buffer are delayed by 4 or 8 horizontal lines Figure 2 7 JPEG Input Timing Diagram ITU 601 and Freerun Clock Mode ...

Page 1257: ... Cb or Cr 23 16 Dummy 8 h00 31 Dummy 8 h00 Dummy 8 h00 Dummy 8 h00 0 31 0 31 YCbCr 4 2 2 8bit 32bit CbYCrY DATA 24bit align DATA 32bit align Figure 2 8 MIPI CSI DATA Alignment Table 2 5 DATA Order of YCbCr422 Align Format Stream Order of Content DATA 24 bit Align DATA 32 bit Align YCbCr422 Cb1 Y1 Cr1 Y2 DATA1 23 16 Cb1 DATA2 23 16 Y1 DATA3 23 16 Cr1 DATA4 23 16 Y2 DATA1 31 24 Cb1 DATA1 23 16 Y1 DA...

Page 1258: ... The CAMIF input signals must not result in inter skewing of the pixel clock line Therefore it is recommended to use next pin location and routing Chip IO CAMCLK CAMRST VSYNC_A HREF_A PCLK_A DATA 7 0 Camera CAMIF No Skew No Skew No Skew Figure 2 9 IO Connection Guide ...

Page 1259: ...The Input DMA port reads the image data from memory On the other hand the Output DMA port stores the image data into memory These two master ports support various digital applications such as Digital Steel Camera DSC MPEG 4 video conference video recording and so on CAMIF Frame Memory Input DMA port OutputDMA port Frame Memory YCbCr4 2 0 YCbCr4 2 2 RGB16 18 24bit YCbCr4 2 0 YCbCr4 2 2 RGB16 18 24b...

Page 1260: ...sary for the three clock domains to synchronize Other signals like PCLK should similarly be connected to Schmitt triggered level shifter Figure 2 11 CAMIF Clock Generation NOTE The maximum frequency of core clock is depend on whether user use local path between display controller or not When it comes to local path between Display Controller the maximum frequency of core clock is 133MHz It is recom...

Page 1261: ... be higher than others If the bus traffic is so heavy that a DMA operation cannot complete for one horizontal period plus blank it might result in mal functioning Therefore the priority of CAMIF must be changed to other round robin or circular arbitration priorities It is recommended that the bus that includes CAMIF should have a higher priority than any other buses in the memory matrix system The...

Page 1262: ...mory Cr frame memory Little endian method Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Cb8 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Little endian method Cr8 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Little endian method RGB frame memory 24 18 bit RGB2 RGB1 RGB4 RGB3 RGB6 RGB5 RGB8 RGB7 RGB frame memory 16 bit 2 64 bit 1 R 5 G 6 B 5 16 bit YCbCr 4 2 2 1plane frame memory Cr2 Y4 Cb2 Y3 Cr1 Y2 Cb1 Y1 Little endian method CbCr frame memory Cr4 Cb4 ...

Page 1263: ...g edge Except the first SFR setting all commands should be programmed in the Interrupt Service Routine ISR Size image mirror or rotation windowing and zoom in settings are allowed to change during capturing In case of DMA input mode all command should be programmed after the InputDMA and OutputDMA operation ends as shown in Figure 2 15 VVALID HVALID INTERRUPT SFR setting ImgCptEr Multi frame captu...

Page 1264: ...ture Start for DMA input Read Memory SFR setting Image Capture Enable SEL_DMA_CAM SFR setting SEL_DMA_CAM New command valid timing diagram for DMA input SFR setting ENVID Image Capture Read Memory data New command SFR setting New command OuputDMA end InputDMA end Read start In capturing Figure 2 15 Timing Diagram for DMA input Register Setting ...

Page 1265: ...ompleted per frame The SFR setting ENVID_M 0 1 makes this mode aware of the starting point and therefore this mode does not require IRQ of starting point and LastIRQ FrameCnt is increased by 1 at ENVID_M InputDMA start low to rising 0 1 and ImgCptEn_SC 1 ISR region ISR region ISR region VSYNC ISR region ImgCptEn cmd LastIRQEn Capture O Capture O Capture O Capture X IRQ Last IRQ High ISR region ISR...

Page 1266: ...ting point and therefore this mode does not require IRQ of starting point and LastIRQ FrameCnt is increased by 1 at ENVID_M low to rising 0 1 and ImgCptEn_SC 1 SFR region SFR region SFR region ENVID_M SFR region Preview DMA frame done Capture O Capture O Capture X IRQ SFR region SFR region SFR region FrameCnt 0 1 1 2 3 3 0 Capture O Capture O Frame_3 Frame_0 Frame_2 Frame_3 Capture O Frame_1 ImgCp...

Page 1267: ...path comprises of YCbCr RGB output format through scaler DMA path The LCD controller displays and controls the two images If input DMA reading the memory data is used in the path SEL_DMA_CAM MSCTRL bit 3 signal must be set to 1 This input path is called Memory Scaling DMA path The window zoom function is disabled in Memory Scaling DMA path NOTE The memory image format for input DMA input includes ...

Page 1268: ...t is in ping pong memory designated by SFR However in this mode both field frame data and odd field frame data are stored successively Therefore even field frame data is stored in first and third ping pong memories while odd field frame data is stored second and fourth ping pong memories In case of image capture start frame is always even field frame A AH HB B b bu us s C CAMERA A AH HB B b bu us ...

Page 1269: ... for output DMA 0x0000_0000 CIOCBSA30 0xFB20_0030 R W Specifies Cb 3rd frame start address for output DMA 0x0000_0000 CIOCBSA40 0xFB20_0034 R W Specifies Cb 4th frame start address for output DMA 0x0000_0000 CIOCRSA10 0xFB20_0038 R W Specifies Cr 1st frame start address for output DMA 0x0000_0000 CIOCRSA20 0xFB20_003C R W Specifies Cr 2nd frame start address for output DMA 0x0000_0000 CIOCRSA30 0x...

Page 1270: ...fies Cb frame start address 1 for Input DMA 0x0000_0000 CIICRSA10 0xFB20_014C R W Specifies Cr frame start address 1 for Input DMA 0x0000_0000 CIOYOFF0 0xFB20_0168 R W Specifies output DMA Y offset 0x0000_0000 CIOCBOFF0 0xFB20_016C R W Specifies output DMA Cb offset 0x0000_0000 CIOCROFF0 0xFB20_0170 R W Specifies output DMA Cr offset 0x0000_0000 CIIYOFF0 0xFB20_0174 R W Specifies input DMA Y offse...

Page 1271: ...tput DMA 0x0000_0000 CIOCBSA41 0xFB30_0034 R W Specifies Cb 4th frame start address for output DMA 0x0000_0000 CIOCRSA11 0xFB30_0038 R W Specifies Cr 1st frame start address for output DMA 0x0000_0000 CIOCRSA21 0xFB30_003C R W Specifies Cr 2nd frame start address for output DMA 0x0000_0000 CIOCRSA31 0xFB30_0040 R W Specifies Cr 3rd frame start address for output DMA 0x0000_0000 CIOCRSA41 0xFB30_00...

Page 1272: ...4C R W Specifies Cr frame start address 1 for Input DMA 0x0000_0000 CIOYOFF1 0xFB30_0168 R W Specifies output DMA Y offset 0x0000_0000 CIOCBOFF1 0xFB30_016C R W Specifies output DMA Cb offset 0x0000_0000 CIOCROFF1 0xFB30_0170 R W Specifies output DMA Cr offset 0x0000_0000 CIIYOFF1 0xFB30_0174 R W Specifies input DMA Y offset 0x0000_0000 CIICBOFF1 0xFB30_0178 R W Specifies input DMA Cb offset 0x000...

Page 1273: ...es Cb 3rd frame start address for output DMA 0x0000_0000 CIOCBSA42 0xFB40_0034 R W Specifies Cb 4th frame start address for output DMA 0x0000_0000 CIOCRSA12 0xFB40_0038 R W Specifies Cr 1st frame start address for output DMA 0x0000_0000 CIOCRSA22 0xFB40_003C R W Specifies Cr 2nd frame start address for output DMA 0x0000_0000 CIOCRSA32 0xFB40_0040 R W Specifies Cr 3rd frame start address for output...

Page 1274: ...t DMA 0x0000_0000 CIICRSA12 0xFB40_014C R W Specifies Cr frame start address 1 for Input DMA 0x0000_0000 CIOYOFF2 0xFB40_0168 R W Specifies output DMA Y offset 0x0000_0000 CIOCBOFF2 0xFB40_016C R W Specifies output DMA Cb offset 0x0000_0000 CIOCROFF2 0xFB40_0170 R W Specifies output DMA Cr offset 0x0000_0000 CIIYOFF2 0xFB40_0174 R W Specifies input DMA Y offset 0x0000_0000 CIICBOFF2 0xFB40_0178 R ...

Page 1275: ... 0 0 SrcHsize_CAM 28 16 Specifies the source horizontal pixel number camera or FIFO input For more information refer to gathering extension register SrcHsize_CAM_ext Note 16 s multiple Must be 4 s multiple of PreHorRatio if WinOfsEn is 0 ML XO 0 Order422_CAM 15 14 Specifies the camera input YCbCr order for 8 bit mode 8 bit mode Data Flow 00 Y0Cb0Y1Cr0 01 Y0Cr0Y1Cb0 10 Cb0Y0Cr0Y1 11 Cr0Y0Cb0Y1 ML X...

Page 1276: ...ed in the CIWDOFST2n registers CIWDOFST0 R W Address 0xFB20_0004 CIWDOFST1 R W Address 0xFB30_0004 CIWDOFST2 R W Address 0xFB40_0004 CIWDOFSTn Bit Description Initial State WinOfsEn 31 1 Enables window offset 0 No offset Note If input format is either RAW or WB Write Back this function is not valid ML XO 0 ClrOvFiY 30 1 Clears the overflow indication flag of input FIFO Y 0 Normal ML XX 0 ClrOvRLB ...

Page 1277: ...2 Reserved 0 WinVerOfst 11 0 Specifies window vertical offset by pixel unit In case of interlaced input this value should be 2 s multiple ML XO 0 NOTE Clear bits should be set to zero after clearing the flags Below constraints of Crop HSIZE and Crop Vsize are only for CAMIF0 CAMIF1 CAMIF2 Crop Hsize SourceHsize WinHorOfst WinHorOfst2 must be 16 s multiple Also It should be 4 s multiple of PreHorRa...

Page 1278: ...ng ITU656 case ITU601_656n 1 SwRst 1 SwRst 0 ITU601_656n 0 for first SFR setting Note 1 User should not use SwRst function in the middle of transferring data out by DMA 2 User should disable ImgCptEn and IRQ_Enable bit before using this function ML XX 0 Reserved 30 Should be 0 0 SelCam_ITU 29 Selects external multiple ITU camera 1 Selects ITU Camera A 0 Selects ITU Camera B ML XX 1 TestPattern 28 ...

Page 1279: ... 1 Interrupt enables at Frame end point 0 Interrupt disables at Frame end point default ML XX 0 IRQ_StartEnable 17 This bit is related to Camera or Local FIFO WB input only 1 Interrupt disables at Frame start point 0 Interrupt enables at Frame start point default ML XX 0 IRQ_Enable 16 1 Enables Interrupt default 0 Disables Interrupt Note If the interrupt enables then the bit 20 CIGCTRLn should be ...

Page 1280: ... method 0 ITU601 equation select SD size target method ML XO 0 InvPolHSYNC 4 1 Inverses the polarity of HSYNC this bit is useful only when delay count interlace mode and FIELD port is connected to HSYNC 0 Normal ML XX 0 SelCam_CAMIF 3 Selects the External camera 1 Selects MIPI Camera 0 Selects ITU Camera ML XX 0 FIELDMODE 2 Specifies the ITU601 interlace field mode Do not care this bit in ITU656 m...

Page 1281: ...0014 CIWDOFST21 R W Address 0xFB30_0014 CIWDOFST22 R W Address 0xFB40_0014 CIWDOFST2n Bit Description Initial State Reserved 31 28 Reserved 0 WinHorOfst2 27 16 Specifies the window horizontal offset2 by pixel unit It should be multiple of 2 Note CAMIF0 CAMIF2 SourceHsize WinHorOfst WinHorOfst2 should be multiple of 16 ML XO 0 Reserved 15 12 Reserved 0 ...

Page 1282: ...OYSA1n CIOYSA10 R W Address 0xFB20_0018 CIOYSA11 R W Address 0xFB30_0018 CIOYSA12 R W Address 0xFB40_0018 CIOYSA1n Bit Description Initial State CIOYSA1 31 0 Output format YCbCr 2 3 plane Y 1st frame start address Output format YCbCr 1 plane YCbCr 1st frame start address Output format RGB RGB 1st frame start address Note In tile mode this value should be aligned 4Kbytes That is to say CIOYSA1 11 0...

Page 1283: ...020 CIOYSA32 R W Address 0xFB40_0020 CIOYSA3n Bit Description Initial State CIOYSA3 31 0 Output format YCbCr 2 3 plane Y 3rd frame start address Output format YCbCr 1 plane YCbCr 3rd frame start address Output format RGB RGB 3rd frame start address Note In tile mode this value should be aligned 4Kbytes That is to say CIOYSA1 11 0 shoule be 0x000 ML OX 0 2 8 1 8 Output DMA Y4 Start Address Register...

Page 1284: ...A11 R W Address 0xFB30_0028 CIOCBSA12 R W Address 0xFB40_0028 CIOCBSA1n Bit Description Initial State CIOCBSA1 31 0 Output format YCbCr 3 plane Cb 1st frame start address Output format YCbCr 2 plane CbCr 1st frame start address Note In tile mode this value should be aligned 4Kbytes That is to say CIOYSA1 11 0 shoule be 0x000 ML OX 0 ...

Page 1285: ...SA31 R W Address 0xFB30_0030 CIOCBSA32 R W Address 0xFB40_0030 CIOCBSA3n Bit Description Initial State CIOCBSA3 31 0 Output format YCbCr 3 plane Cb 3rd frame start address Output format YCbCr 2 plane CbCr 3rd frame start address Note In tile mode this value should be aligned 4Kbytes That is to say CIOYSA1 11 0 shoule be 0x000 ML OX 0 2 8 1 12 Output DMA Cb4 Start Address Register CIOCBSA4n CIOCBSA...

Page 1286: ...tart address Note In tile mode this value should be aligned 4Kbytes That is to say CIOYSA1 11 0 shoule be 0x000 ML OX 0 2 8 1 14 Output DMA Cr2 Start Address Register CIOCRSA2n CIOCRSA20 R W Address 0xFB20_003C CIOCRSA21 R W Address 0xFB30_003C CIOCRSA22 R W Address 0xFB40_003C CIOCRSA2n Bit Description Initial State CIOCRSA2 31 0 Output format YCbCr 3 plane Cr 2nd frame start address Note In tile...

Page 1287: ...tart address Note In tile mode this value should be aligned 4Kbytes That is to say CIOYSA1 11 0 shoule be 0x000 ML OX 0 2 8 1 16 Output DMA Cr4 Start Address Register CIOCRSA4n CIOCRSA40 R W Address 0xFB20_0044 CIOCRSA41 R W Address 0xFB30_0044 CIOCRSA42 R W Address 0xFB40_0044 CIOCRSA4n Bit Description Initial State CIOCRSA4 31 0 Output format YCbCr 3 plane Cr 4th frame start address Note In tile...

Page 1288: ...FMT1 R W Address 0xFB30_0048 CITRGFMT2 R W Address 0xFB40_0048 Original image 0 0 0 Rot90 FlipMd 0 MSB LSB X axis flip 0 0 1 Y axis flip 0 1 0 0 1 1 90 clockwise 1 0 0 90 X axis flip 1 0 1 90 Y axis flip 1 1 0 90 XY axis flip 270 clockwise XY axis flip 180 clockwise FlipMd 1 1 1 1 Figure 2 23 Image Mirror and Rotation ...

Page 1289: ...on register for format YCbCr444 ML OO 0 TargetHsize 28 16 Specifies the horizontal pixel number of target image Refer to gathering extension register TargetHsize_ext Note CAMIF0 and CAMIF2 In case of output DMA TargetHsize should be multiple of 16 CAMIF1 In case of interlaced output DMA and 90 degree rotation TargetVsize should be more than 16 ML OO 0 OutFlipMd 15 14 Specifies image mirror and rot...

Page 1290: ... care Caution Only input rotator supports InputDMA image data The output rotator supports Camera or InputDMA image data Input and output rotators should not work at the same time because input and output rotator memories are shared for saving the memory size NOTE If the TargetVsize value is set to an odd number N when output format is YCbCr 4 2 0 the odd numbers N of Y lines and N 1 2 of Cb Cr lin...

Page 1291: ... Weave 2 Norma ML 0X 0 Reserved 30 26 Reserved 0 Order2p_out 25 24 Specifies YCbCr 4 2 0 or 4 2 2 2plane output Chroma memory storing style order should be C_INT_OUT 1 bit MSB LSB 00 Cr3Cb3Cr2Cb2Cr1Cb1Cr0Cb0 01 Cb3Cr3Cb2Cr2Cb1Cr1Cb0Cr0 10 Reserved 11 Reserved ML OO 0 Reserved 23 4 Reserved 0 C_INT_OUT 3 1 YCbCr 4 2 0 or 4 2 2 2plane output format 0 YCbCr 4 2 0 or 4 2 2 3plane output format ML OO 0...

Page 1292: ...RFACE 2 45 YCbCr 3 plane YCbCr 2 plane YCbCr 1 plane Y1Y2Y3Y4Y5Y6Y7Y8 Cb1Cb2Cb3Cb4Cb5Cb6Cb7Cb8 Cr1Cr2Cr3Cr4Cr5Cr6Cr7Cr8 Y1Y2Y3Y4Y5Y6Y7Y8 Cb1Cr1Cb2Cr2Cb3Cr3Cb4Cr4 Y1Cb1Y2Cr1Y3Cb2Y4Cr2 Figure 2 24 YCbCr Plane Memory Storing Style ...

Page 1293: ... YCbCr420 image SourceHsize SourceVsize Original Input SourceHsize Original Input Zoom In TargetHsize TargetVsize TargetHsize Scale Down TargetVsize SourceVsize WinHorOfst WinHorOfst2 WinVerOfst WinVerOfst2 DST_Width TargetHsize DST_Height TargetVsize SRC_Width SourceHsize WinHorOfst WinHorOfst2 SRC_Height SourceVsize WinVerOfst WinVerOfst2 DST_Width TargetHsize DST_Height TargetVsize SRC_Width So...

Page 1294: ...F2 MainHorRatio SRC_Width 8 DST_Width H_Shift CAMIF1 MainHorRatio SRC_Width 14 DST_Width H_Shift If SRC_Height 64 DST_Height Exit 1 Out Of Vertical Scale Range else if SRC_Height 32 DST_Height PreVerRatio 32 V_Shift 5 else if SRC_Height 16 DST_Height PreVerRatio 16 V_Shift 4 else if SRC_Height 8 DST_Height PreVerRatio 8 V_Shift 3 else if SRC_Height 4 DST_Height PreVerRatio 4 V_Shift 2 else if SRC_...

Page 1295: ... 22 16 Specifies the horizontal ratio of pre scaler ML OO 0 Reserved 15 7 Reserved 0 PreVerRatio 6 0 Specifies the vertical ratio of pre scaler ML OO 0 2 8 2 2 Pre Scaler Control Register 2 CISCPREDSTn CISCPREDST0 R W Address 0xFB20_0054 CISCPREDST1 R W Address 0xFB30_0054 CISCPREDST2 R W Address 0xFB40_0054 CISCPREDSTn Bit Description Initial State Reserved 31 30 Reserved 0 PreDstWidth 29 16 Spec...

Page 1296: ...ing color space conversion input DMA mode Write Back mode and RGB format are not allowed If input format is YCbCr4 2 2 the output format should also be YCbCr4 2 2 or YCbCr4 2 0 ML XX 0 ScaleUp_H 30 Specifies horizontal scale up down flag for scaler In 1 1 scale ratio this bit should be 1 1 Up 0 Down ML OO 0 ScaleUp_V 29 Specifies vertical scale up down flag for scaler In 1 1 scale ratio this bit s...

Page 1297: ...essive mode 0 progressive scan out Note If this bit is configured by 0 for interlacced input the output is also interlaced format not converted into progressive one ML OX 0 MainHorRatio 24 16 Specifies horizontal scale ratio for main scaler Note CAMIF1 Refer to the gathering extension register MainHorRatio_ext ML OO 0 ScalerStart 15 Specifies the Scaler start 1 Scaler start 0 Scaler stop or scaler...

Page 1298: ... needs this method if input format are YCbCr4 2 0 and YCbCr4 2 2 Scalerbypass should be set to 0 and don t care plane Caution One2One should be used if input output format and size are same One2One function has size constraints as described in Table 9 2 1 For example input YCbCr4 2 0 2plane output YCbCr4 2 0 3plane O K ML OO 0 MainVerRatio 8 0 Specifies vertical scale ratio for main scaler Note CA...

Page 1299: ...t Input and output format are possible for both Progressive and Interlace format All source and destination image data need to be stored in memory system aligned with double word boundary and should support DMA operation Therefore the width of source and destination image should satisfy the double word boundary condition FIFO Mode Operation DMA Input FIFO Output In FIFO Mode LCDPathEn 1 two types ...

Page 1300: ... an interlaced scan mode is enabled LCDPathEn 1 and Interlace 1 per frame management which consists of even field and odd filed is automatic This means that user interruption is unnecessary to interfield switching in the same frame Therefore the frame management scheme is identical for both progressive and interlaced scan modes Interlace is not supported if camera processor selects the input data ...

Page 1301: ...CE 2 54 Video Graphic 1 Frame Video Graphic Data 1 Frame CAMIF Display Controller FIFO Video Graphic DMA Mode FIFO Mode FIFO Full Data Valid AXI Bus Memory Memory Camera processor WB FIFO OR Figure 2 27 Input Output Modes in CAMIF ...

Page 1302: ...INESKIP1 R W Address 0xFB30_0060 CIOLINESKIP2 R W Address 0xFB40_0060 CIOLINESKIPn Bit Description Initial State Reserved 31 24 Reserved 0 OLINESKIP_Cr 23 20 Specifies Cr Line skip for output DMA If OLINESKIP_Cr is k Cr Line is stored in every k 1 line Note Maximum value can be 8 ML OO 0 Reserved 19 14 Reserved 0 OLINESKIP_Cb 13 10 Specifies Cb Line skip for output DMA If OLINESKIP_Cb is k Cb Line...

Page 1303: ...me number ML XX R 0 WinOfstEn 25 Specifies window offset enable status ML XX R 0 FlipMd 24 23 Specifies flip mode of output DMA ML XX R 0 ImgCptEn 22 Specifies image capture enable of global camera interface ML XX R 0 ImgCptEn_SC 21 Specifies image capture enable of scaler path ML XX R 0 VSYNC_A 20 Specifies external camera A VSYNC Polarity inversion is not adopted ML XX R X VSYNC_B 19 Specifies e...

Page 1304: ...es capture frame control status 1 Enables present capture 0 Disables present capture ML XX R 0 FrameFieldStatus 10 Specifies ITU camera field status and internal value after inverse polarity 1 Present frame Field1 0 Present frame Field0 ML XX R 0 LCD_ENSTATUS 9 Specifies LCD controller enable status 1 Enables 0 Disables ML XX R 0 ENVID_STATUS 8 Specifies Input DMA enable internal status Sometimes ...

Page 1305: ...it under capture enable status ML XO 0 Reserved 24 Reserved 0 Cpt_FrPtr 23 19 Captures sequence turnaround pointer ML XX 0 Cpt_ FrMod 18 Captures frame control mode 1 Applies Cpt_FrCnt mode Captures Cpt_FrCnt frames along Cpt_FrSeq after enabling capture DMA frame control If Cpt_FrCnt 0 then capture ends 0 Apply Cpt_FrEn mode Captures frames along Cpt_FrSeq when Cpt_FrEn is high This sequence repe...

Page 1306: ...FB40_00C4 CICPTSEQn Bit Description Initial State Cpt_FrSeq 31 0 Specifies capture sequence pattern This register is valid if Cpt_FrEn has a high value ML XX FFFF_FFFF 1 1 0 1 0 1 Cpt _ FrPtr 3 1 3 0 2 9 1 0 Cpt _ DMA _ Seq 31 0 Repeat Capture No Capture Capture Capture Figure 2 28 Capture Frame Control For skipped frames IRQ is not generated and FrameCnt is not increased ...

Page 1307: ...e is possible ML XO 0 W_QoS_EN 30 1 QoS Enable for Write DMA channel buffer 0 QoS Disable for Write DMA channel buffer Read DMA QoS Enable and Write DMA QoS Enable cannot set simultaneously Only one QoS Enable is possible ML XO 0 Reserved 29 23 0 RTh_QoS 22 16 Read buffer threshold register related Input DMA If RTh_QoS Buffer write count Read channel is generated no margin signal for bus high perf...

Page 1308: ... mode 0 Before scaling only ITU camera image are applied It applies image effect even though it is in scaler bypass mode ML OO 0 FIN 28 26 Specifies image effect selection 3 d0 Bypass 3 d1 Arbitrary Cb Cr 3 d2 Negative 3 d3 Art Freeze 3 d4 Embossing 3 d5 Silhouette ML OO 0 Reserved 25 21 Reserved 0 PAT_Cb 20 13 Used only for FIN is Arbitrary Cb Cr PAT_Cb Cr 8 d128 for Grayscale Wide CSC Range 0 PA...

Page 1309: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 62 Original Arbitary sepia Negative Art freeze Embossing Silhouette Figure 2 29 Image Effect ...

Page 1310: ...A0n CIICBSA00 R W Address 0xFB20_00D8 CIICBSA01 R W Address 0xFB30_00D8 CIICBSA02 R W Address 0xFB40_00D8 CIICBSA0n Bit Description Initial State CIICBSA0 31 0 Input format YCbCr 3 plane Cb frame start address Input format YCbCr 2 plane CbCr frame start address Note In tile mode this value should be aligned 4Kbytes That is to say CIOYSA1 11 0 shoule be 0x000 ML OX 0 2 8 2 13 Input DMA Cr0 Start Re...

Page 1311: ...P_CB0 R W Address 0xFB20_00F0 CIILINESKIP_CB1 R W Address 0xFB30_00F0 CIILINESKIP_CB2 R W Address 0xFB40_00F0 CIILINESKIP_CBn Bit Description Initial State Reserved 31 28 Reserved 0 ILINESKIP_Cb 27 24 Specifies Cb Line Skip for Input DMA Note Maximum value can be 8 ML OX 0 Reserved 23 0 Reserved 0 2 8 2 16 Input DMA Cr Line Skip Register CIILINESKIP_CRn CIILINESKIP_CR0 R W Address 0xFB20_00F4 CIIL...

Page 1312: ...dress change only software trigger mode At the start of first frame ADDR_CH_DIS should be equal to 0 0 Enables address change 1 Disables address change ML OX 0 REAL_HEIGHT 29 16 Specifies input DMA real image vertical pixel size Minimum 8 Note 1 2 s multiple YCbCr 420 2 4 s multiple Weave in mode and YCbCr 420 input 3 2 s multiple Weave in mode except YCbCr 420 input 4 2 s multiple Input rotator O...

Page 1313: ...hen using input rotator in Weave_in mode output horizontal size should be even value Because vertical data will be converted into horizontal one after rotating ML XX R W 0 Reserved 30 28 Reserved R W 0 Successive_cnt 27 24 Specifies input DMA burst successive count Default is 4 but 3 2 or 1 are also possible This value should not be 0 ML OX R W 4 d4 Reserved 23 20 Reserved R W 0 InBuf_Mode 19 Spec...

Page 1314: ...ange 0 Ping Pong address is changed at interlace even odd field end 1 Ping Pong address is changed at the frame operation end ML OX R W 0 Reserved 9 Reserved RW 0 Buffer_Ptr 8 Specifies the input DMA buffer address selection pointer This register initializes to set the first frame address before starting input DMA This register should not be written under frame operation 0 Buffer address 0 1 Buffe...

Page 1315: ... The hardware clears automatically If data flows from input DMA to local direct FIFO the software can clear this bit when LCD_ENSTATUS is 0 1 SEL_DMA_CAM 0 ENVID_M don t care using external camera signal 2 SEL_DMA_CAM 1 ENVID_M is set 0 1 then Input DMA operation starts ML OX R W 0 NOTE ENVID_M SFR must be set at the end Starting order for using DMA input path SEL_DMA_CAM others SFR setting Image ...

Page 1316: ...ing MODE DMA input FIFO progressive output ENVID_M Next Frame start Frame start 0 1 setting Auto Clear Frame end 0 1 setting MODE DMA input FIFO interlace output Auto Clear Even field end Auto Start Odd field start ENVID_M Next frame start Frame start 0 1 setting Auto Clear Frame end Auto Start if autoload enable 1 MODE DMA input AutoLoad enable mode Figure 2 30 ENVID_M SFR Setting When Input DMA ...

Page 1317: ...Q signal generation SFR SFR RGB start address Target format OutDMA Control etc Figure 2 31 SFR and Operation Related Each DMA When Selected Input DMA Path ENVID Frame start address change ADDR_CH_DIS Start Address 0 1 user setting A 0 F A F Start Address 0 1 for real operation 0 A F Frame start address change Figure 2 32 Input DMA Address Change Timing progressive to progressive ...

Page 1318: ... Even field start address change Figure 2 33 Input DMA Address Change Timing progressive to interlace ENVID ADDR_CH_DIS Start Address user setting A 0 F C Start Address for real operation 0 A F Even field Odd field Even field Odd field Even field C SwUpdate SwUpdate 1 address change Autoclear Even field start address change Even field start address change Figure 2 34 Input DMA Address Change Timin...

Page 1319: ...R2 WRITE ADDR3 Buffer_Ptr 1 Buffer_Ptr 0 pingpong Pingpong by FrameCnt Figure 2 35 Input Ouput DMA pingpong Address Change Scheme Figure 2 36 Input DMA Progressive in to Interlace out only interlace_out setting Figure 2 37 Input DMA Progressive in to Interlace out Weave_in and Interlace_out setting ...

Page 1320: ...SA1n CIICBSA10 R W Address 0xFB20_0148 CIICBSA11 R W Address 0xFB30_0148 CIICBSA12 R W Address 0xFB40_0148 CIICBSA1n Bit Description Initial State CIICBSA1 31 0 Input format YCbCr 3 plane Cb frame start address Input format YCbCr 2 plane CbCr frame start address Note In tile mode this value should be aligned 4Kbytes That is to say CIOYSA1 11 0 shoule be 0x000 ML OX 0 2 8 2 21 Input DMA CR1 Start R...

Page 1321: ... 15 14 Reserved 0 OYOFF_H 13 0 Output DMA horizontal offset for Y component Output format YCbCr 2 3 plane Y width offset Output format YCbCr 1 plane YCbCr width offset Output format RGB RGB width offset Note Offset value is based on pixel unit ML OO 0 2 8 2 23 Output DMA Cb Offset Register CIOCBOFFn CIOCBOFF0 R W Address 0xFB20_016C CIOCBOFF1 R W Address 0xFB30_016C CIOCBOFF2 R W Address 0xFB40_01...

Page 1322: ...MERA INTERFACE 2 75 OCBOFF_H 13 0 Output DMA horizontal offset for Cb component Output format YCbCr 3 plane Cb width offset Output format YCbCr 2 plane CbCr width offset Note Offset value is based on pixel unit ML OO 0 ...

Page 1323: ...et value is based on pixel unit ML OO 0 2 8 2 25 Input DMA Y Offset Register CIIYOFFn CIIYOFF0 R W Address 0xFB20_0174 CIIYOFF1 R W Address 0xFB30_0174 CIIYOFF2 R W Address 0xFB40_0174 CIIYOFFn Bit Description Initial State Reserved 31 30 Reserved 0 IYOFF_V 29 16 Specifies the input DMA vertical offset for Y component Input format YCbCr 2 3 plane Y height offset Input format YCbCr 1 plane YCbCr he...

Page 1324: ...ontal offset for Cb component Input format YCbCr 3 plane Cb width offset Input format YCbCr 2 plane CbCr width offset Note Offset value is based on pixel unit ML OX 0 2 8 2 27 Input DMA Cr Offset Register CIICROFFn CIICRFF0 R W Address 0xFB20_017C CIICRFF1 R W Address 0xFB30_017C CIICRFF2 R W Address 0xFB40_017C CIICROFFn Bit Description Initial State Reserved 31 30 Reserved 0 ICROFF_V 29 16 Speci...

Page 1325: ... REAL_WIDTH Original image height ORG_IN_V Real Image height REAL_HEIGHT Figure 2 38 Input DMA Offset and Image Size OFFSET_H OFFSET_V Real Image height TargetV size DMA Start Address Original image height ORG_OUT_V Original image width ORG_OUT_H Real Image width TargetH size Figure 2 39 Output DMA Offset and Image Size ...

Page 1326: ...hese should be aligned with double word boundary that is ADDRStart_X 2 0 3 b000 DMA OFFSET Offset_H_Y Y offset per a horizontal line 8 s multiple only for CAMIF0 2 Number of pixel or sample in horizontal offset Offset_H_Cb Cb offset per a horizontal line 8 s multiple only for CAMIF0 2 Number of pixel or sample in horizontal offset Offset_H_ Cr Cr offset per a horizontal line 8 s multiple only for ...

Page 1327: ... DMA should follow below equation for input rotator is enabled ORG_IN_V 8 ORG_IN_V OFFSET_V 8 2 8 2 29 Original Output DMA Image Size ORGOSIZEn ORGOSIZE0 R W Address 0xFB20_0184 ORGOSIZE1 R W Address 0xFB30_0184 ORGOSIZE2 R W Address 0xFB40_0184 ORGOSIZEn Bit Description Initial State Reserved 31 30 Reserved 0 ORG_OUT_V 29 16 Specifies the output DMA original image vertical pixel size minimum is 8...

Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...

Page 1329: ...window horizontal offset size 11 0 ML OO 0 Reserved 27 Reserved TargetHsize_ext 26 Specifies the bit value 13 of target image horizontal pixel number register TargetHsize_ext TargetHsize 13 12 0 Thus total target image horizontal size 13 0 ML OO 0 Reserved 25 Reserved 0 TargetVsize_ext 24 Specifies the bit value 13 of target image vertical number register TargetVsize_ext TargetVsize 13 12 0 Thus t...

Page 1330: ...al ratio register MainHorRatio MainHorRatio_ext 14 6 5 0 Thus total Mainscale horizontal ratio register range 14 0 ML OO 0 MainVerRatio_ext 5 0 Bit value 5 0 of the Mainscale vertical ratio register MainVerRatio MainVerRatio_ext 14 6 5 0 Thus total Mainscale vertical ratio register range 14 0 ML OO 0 ...

Page 1331: ...eserved 0 MODE_R 30 29 Specifies the INPUT DMA address access style 0 Linear 1 Reserved 2 Reserved 3 64x32 tile ML OX 0 Reserved 28 15 Reserved 0 MODE_W 14 13 Specifies the OUTPUT DMA address access style 0 Linear 1 Reserved 2 Reserved 3 64x32 tile Note If input format is either CAM_JPEG or MIPI RAW User can not use 64x32 tile mode ML XX 0 Reserved 12 4 Reserved 0 Reserved 3 0 Reserved 0 NOTE Refe...

Page 1332: ...x2B RAW10 0x2C RAW12 ML XX 0x1E NOTE Frame End Address calculation method useful only for TILE 64x32 access mode Note When tile mode is enable lower 13bits of Base_address 31 0 have Zero value So SFRs related to Base_adddress should be zero their lower 13bits When condition is YCbCr4 2 0 3plane In Rotator 90 X XY flip Horizontal size 32 OFFSET_X_Cr 0 Minimum input size is 64x64 Example Image pixel...

Page 1333: ... pixel_y_minus 5 0 pic_range pixel_y_minus 14 6 roundup_x pixel_x_minus 14 8 1 11 10 4 1 115 else pic_range roundup_x roundup_y 2 Chroma case pixel_x_minus pixel_x 1 1279 pixel_y_minus pixel_y 1 359 101100111 binary roundup_x INT INT pixel_x 1 16 8 1 10 roundup_y INT INT pixel_y 1 16 4 1 6 if pixel_y_minus 5 0 pixel_y_minus 5 0 b 100111 pixel_y_minus 5 1 pic_range pixel_y_minus 14 6 roundup_x pixe...

Page 1334: ...between CAMIF and Display Controller ML OO 0 Reserved 0 0 2 8 2 34 Key Detect Register CIKEYn CIKEY0 R W Address 0xFB20_019C CIKEY1 R W Address 0xFB30_019C CIKEY2 R W Address 0xFB40_019C CIKEYn Bit Description Initial State KEY_DETECT 31 Specifies KEY detect for graphic layer scaling 1 KEY detect ON 0 OFF Normal ML OO 0 Reserved 30 28 0 R_KEY 27 20 Specifies R of the RGB region key value ML OO 0 R...

Page 1335: ...ta lanes Supports pixel format 16bpp 18bpp packed 18bpp loosely packed 3 byte format and 24bpp Interfaces Complies with Protocol to PHY Interface PPI in MIPI D PHY Specification V0 90 Supports RGB Interface for Video Image Input from display controller Supports I80 Interface for Command Mode Image input from display controller Supports PMS control interface for PLL to configure byte clock frequenc...

Page 1336: ...MIPI DSIM CLK lane Data lane0 Data lane1 Data lane2 Data lane3 RGB Path I80 Path Figure 3 1 MIPI DSI System Block Diagram NOTE 1 DSIM gets data from the different IPs 2 You can select one of above data paths by setting DISPLAY_PATH_SEL 1 0 0xE010_7008 For more information refer to Section 2 3 S5PC110_CMU ...

Page 1337: ...pth Specifies the packet header FIFO for general packet SFR for general packets Payload FIFO 4byte X 512 depth Specifies the payload FIFO for general long packet RX FIFO Packet header and Payload FIFO 4byte X 64 depth Specifies Rx FIFO for LPDR This FIFO is common for packet header and payload 3 1 2 3 Packet Header Arbitration There are four packet headers FIFOs for Tx namely main display sub disp...

Page 1338: ...acket is always stored in LSB For example if a long packet has 7 byte payload the last byte is filled with dummy byte and the next packet is stored in the next word as shown in Figure 3 2 NOTE CRC data is not stored in RXFIFO P H b0 P H b1 P H b2 E C C PL b0 PL b1 PL b2 PL b3 PL b4 PL b5 PL b6 C R C 0 C R C 1 RXBUF with synchronizer between ByteClk and RxClk RXFIFO Asynchronous FIFO Packet header ...

Page 1339: ...SYNC RGB_VDEN BLLP BLLP Vsync start packet Hsync start packet BLLP BLLP BLLP BLLP RGB_DATA DSI_channel BLLP BLLP LP BLLP BLLP BLLP BLLP BLLP BLLP Vsync end packet Hsync end packet DSI_channel Burst mode Non burst mode with Sync event Non burst mode with Sync pulses H S A RGB HFP H B P HBP RGB HFP HBP RGB HFP BLLP Figure 3 3 Signal Converting Diagram in Video Mode ...

Page 1340: ...0 data 15 12 and data 7 4 The DSIM ignores rest of the bits 3 1 3 1 2 RGB Interface Vsync Hsync and VDEN are active high signals Among the three signals Vsync and Hsync are pulse types that spend several video clocks RGB_VD 23 0 is R 7 0 G 7 0 B 7 0 All sync signals are synchronized to the rising edge of RGB_VCLK The display controller sends minimum one horizontal line length of Vsync pulse V back...

Page 1341: ...HBP Mode HBP Mode Reset DSIM_CONFIG 21 0 Figure 3 7 Block Timing Diagram of HBP Mode HBP Mode Set DSIM_CONFIG 21 1 HFP mode HFP mode specifies the Horizontal Front Porch disable mode Figure 3 8 Block Timing Diagram of HFP Mode HFP Mode Reset DSIM_CONFIG 22 0 Figure 3 9 Block Timing Diagram of HFP Mode HFP Mode Set DSIM_CONFIG 22 1 ...

Page 1342: ...de HSE mode specifies the Horizontal Sync End Packet Enable mode in Vsync pulse or Vporch area Figure 3 10 Block Timing Diagram of HSE Mode HSE Mode Reset DSIM_CONFIG 23 0 Figure 3 11 Block Timing Diagram of HSE Mode HSE Mode Set DSIM_CONFIG 23 1 ...

Page 1343: ...s the command allowed area Configuration boundary is 4 h0 4 hF in DSIM_MVPORCH Only this area is allowed to start command transfer through HS mode or LPDT In LPDT data transferring takes a long time to complete approximately hundreds of microseconds or more In this time Hsync packet does not arrive due to LPDT long packet MIPI DSIM comprises of big size FIFO for lost Hsync packet After LPDT MIPI D...

Page 1344: ...ycle T5 2 clock cycle T2 T3 T4 1 cycle of byte clock A display controller generates these signals with its internal clock SYS_CS0 CS1 SYS_WE and SYS_VD MIPI DSI master decodes the SYS_ADDR Table 3 2 describes the I80 INTERFACE address map Table 3 2 I80 Interface Address Map SYS_ADDR 1 0 Description 2 b00 Specifies the image data 2 b01 Reserved 2 b10 Specifies the payload data 2 b11 Specifies the p...

Page 1345: ...S long write Payload DCS command is write_memory_continue PH DCS long write PH DCS long write PF CRC PF CRC PF CRC P0 P1 P2 P h 1 P h P h 1 P h 2 P 2h 1 P 2h P 2h 1 P 2h 2 P 3h 1 P v 1 h P v 1 h 1 P v 1 h 2 P v h 1 PH DCS long write PF CRC PH DCS long write PH DCS long write PH DCS long write PF CRC PF CRC PF CRC I80 I F Input Command mode output Payload DCS command is write_memory_continue Payloa...

Page 1346: ...acket 888 666 666 loosely packed and 565 should be specified via register configuration I80 I80 Image Transaction Specifies the Data type that is DCS Long Write packet DCS command is memory write start continue I80 I80 Command Transaction Specifies any DSI packet Bytes in I80 transaction should be the same bytes in DSI packets SFR Header and Payload FIFO access Specifies any DSI Packets Bytes in A...

Page 1347: ...mode 3 1 6 PLL To transmit Image data MIPI DSI Master Block needs high frequency clock 80MHz 1GHz generated by PLL To configure PLL MIPI DSI Master comprises of SFRs and corresponding interface signals PLL is embedded in PHY module You should use other PLL in SoC if it meets the timing specification 3 1 7 BUFFER In MIPI DSI standard specification DSI Master sends image stream in burst mode The ima...

Page 1348: ...fies the DP signal for MIPI DPHY Master data lane 2 XmipiDP 2 Dedicated MIPI_DN_2 O Specifies the DN signal for MIPI DPHY Master data lane 2 XmipiDN 2 Dedicated MIPI_DP_3 O Specifies the DP signal for MIPI DPHY Master data lane 3 XmipiDP 3 Dedicated MIPI_DN_3 O Specifies the DN signal for MIPI DPHY Master data lane 3 XmipiDN 3 Dedicated MIPI_CLK_TX_P O Specifies the DP signal for MIPI DPHY Master ...

Page 1349: ...50_0028 R W Specifies the sub display image resolution register 0x0300_0400 DSIM_INTSRC 0xFA50_002C R W Specifies the interrupt source register 0x0000_0000 DSIM_INTMSK 0xFA50_0030 R W Specifies the interrupt mask register 0xB337_FFFF DSIM_PKTHDR 0xFA50_0034 W Specifies the packet header FIFO register 0x0000_0000 DSIM_PAYLOAD 0xFA50_0038 W Specifies the payload FIFO register 0x0000_0000 DSIM_RXFIFO...

Page 1350: ... the HS clock ready at clock lane 0 Not ready for transmitting HS data at clock lane 1 Ready for transmitting HS data at clock lane 0 UlpsClk 9 Specifies the ULPS indicator at clock lane 0 No ULPS in clock lane 1 ULSP in clock lane 1 StopstateClk 8 Specifies the stop state indicator at clock lane 0 No stop state in clock lane 1 Stop state in clock lane 0 UlpsDat 3 0 7 4 Specifies the ULPS indicato...

Page 1351: ...except SFRs STATUS SWRST CLKCTRL TIMEOUT CONFIG ESCMODE MDRESOL MDVPORCH MHPORCH MSYNC INTMSK SDRESOL FIFOTHLD FIFOCTRL MEMACCHR PLLCTRL PLLTMR PHYACCHR and VERINFORM 0 Standby 1 Reset ForceStopstate CmdLpdt TxLpdt nInitRx nInitSfr nInitI80 nInitSub nInitMD 0 Reserved 15 1 Reserved SwRst 0 Specifies the software reset High active Software reset resets all FF in MIPI DSIM except some SFRs STATUS SW...

Page 1352: ...l Serial clock 0 ByteClkSrc 26 25 Selects byte clock source It must be 00 00 D PHY PLL default PLL_out clock is used to generate ByteClk by dividing 8 0 ByteClkEn 24 Enables byte clock 1 Disables 0 Enables 0 LaneEscClkEn 23 19 Enables escape clock for D phy lane LaneEscClkEn 0 Clock lane LaneEscClkEn 1 Data lane 0 LaneEscClkEn 2 Data lane 1 LaneEscClkEn 3 Data lane 2 LaneEscClkEn 4 Data lane 3 0 D...

Page 1353: ...configures MIPI DSI master such as data lane number input interface porch area frame rate BTA LPDT ULPS and so on DSIM_CONFIG Bit Description Initial State Reserved 31 30 Reserved Mflush_VS 29 Auto flush of MD FIFO using Vsync pulse It needs that Main display FIFO should be flushed for deleting garbage data 0 Enable defalut 1 Disable 1 EoT_r03 28 Disables EoT packet in HS mode 0 Enables EoT packet...

Page 1354: ...c 1 1r02 This bit transfers Hsync end packet in Vsync pulse and Vporch area optional 0 Disables transfer 1 Enables transfer In command mode this bit is ignored 0 HfpMode 22 Specifies HFP disable mode If this bit set DSI master ignores HFP area in Video mode 0 Enables 1 Disables In command mode this bit is ignored 0 HbpMode 21 Specifies HBP disable mode If this bit set DSI master ignores HBP area i...

Page 1355: ...bpp for Command mode only 010 12bpp for Command mode only 011 16bpp for Command mode only 100 16 bit RGB 565 for Video mode only 101 18 bit RGB 666 packed pixel stream for Video mode only 110 18 bit RGB 666 loosely packed pixel stream for common 111 24 bit RGB 888 for Common 0 Reserved 7 Reserved NumOfDatLane 6 5 Sets the data lane number 00 Data lane 0 1 data lane 01 Data lane 0 1 2 data lanes 10...

Page 1356: ...to D PHY MIPI DSI peripheral becomes master after BTA sequence This bit clears automatically after receiving BTA acknowledge from MIPI DSI peripheral 0 Reserved 15 8 Reserved CmdLpdt 7 Specifies LPDT transfers command in SFR FIFO 0 HS Mode 1 LP Mode 0 TxLpdt 6 Specifies data transmission in LP mode all data transfer in LPDT 0 HS Mode 1 LP Mode 0 Reserved 5 Reserved TxTriggerRst 4 Specifies remote ...

Page 1357: ... DSIM_MVPORCH R W Address 0xFA50_001C DSIM_MVPORCH Bit Description Initial State CmdAllow 31 28 Specifies the number of horizontal lines where command packet transmission is allowed after Stable VFP period For more information see Figure 3 12 0xF Reserved 27 Reserved StableVfp 10 0 26 16 Specifies the number of horizontal lines where command packet transmission is not allowed after end of active r...

Page 1358: ...es the vertical sync pulse width for Video mode Line count In command mode these bits are ignored 0 Reserved 21 16 Reserved MianHsa 15 0 15 0 Specifies the horizontal sync pulse width for Video mode HSA is specified using blank packet These bits specify word counts for blank packet in HSA In command mode these bits are ignored 0 3 3 1 11 Sub Display Image Resolution Register DSIM_SDRESOL R W Addre...

Page 1359: ...timeout See time out register 0x10 0 TaTout 20 Turns around Acknowledge Timeout See time out register 0x10 0 Reserved 19 Reserved RxDatDone 18 Completes receiving data 0 RxTE 17 Receives TE Rx trigger 0 RxAck 16 Receives ACK Rx trigger 0 ErrRxECC 15 Specifies the ECC multi bit error in LPDR 0 ErrRxCRC 14 Specifies the CRC error in LPDR 0 ErrEsc3 13 Specifies the escape mode entry error lane 3 For ...

Page 1360: ... to standard D PHY specification 0 ErrControl1 3 Controls Error lane1 For more information refer to standard D PHY specification 0 ErrControl0 2 Controls Error lane0 For more information refer to standard D PHY specification 0 ErrContentLP0 1 Specifies the LP0 Contention Error only lane0 because BTA occurs at lane0 only For more information refer to standard D PHY specification 0 ErrContentLP1 0 S...

Page 1361: ...sc3 13 Specifies escape mode entry error in lane3 For more information refer to standard D PHY specification 1 MskEsc2 12 Specifies escape mode entry error in lane2 For more information refer to standard D PHY specification 1 MskEsc1 11 Specifies escape mode entry error in lane1 For more information refer to standard D PHY specification 1 MskEsc0 10 Specifies escape mode entry error in lane0 For m...

Page 1362: ...end DSI packets DSIM_PKTHDR Bit Description Initial State Reserved 31 24 Reserved PacketHeader 23 0 Writes the packet header of Tx packet 7 0 DI 15 8 Dat0 Word Count lower byte for long packet 23 16 Dat1 Word Count upper byte for long packet 0 3 3 1 15 Payload FIFO Register DSIM_PAYLOAD W Address 0xFA50_0038 This register specifies the FIFO for payload to send DSI packets DSIM_PAYLOAD Bit Descript...

Page 1363: ...PLLTMR R W Address 0xFA50_0050 DSIM_PLLTMR Bit Description Initial State PllTimer 31 0 Specifies the PLL Timer for stability of the generated clock System clock cycle base If the timer value goes to 0x00000000 the clock stable bit of status and interrupt register is set 0xFFFFFFFF 3 3 1 19 DSIM D PHY AC Characteristic Register DSIM_PHYACCHR R W Address 0xFA50_0054 DSIM_PHYACCHR Bit Description Ini...

Page 1364: ...ACCHR Bit Description Initial State Reserved 31 7 Reserved Should be 0 0 Reserved 6 4 Reserved 0 Reserved 3 2 Reserved 0 DpDnSwap_CLK 1 Swaps Dp Dn channel of clock lane If this bit is set Dp and Dn channel swap each other 0 DpDnSwap_DAT 0 Swaps Dp Dn channel of Data lanes If this bit is set Dp and Dn channel swap each other 0 ...

Page 1365: ... stability The VCO output frequency range of MIPI_PLL varies from 500MHz to 1000MHz 3 Keep to range of Fin_pll varies from 6 MHz to 12 MHz using P code setting Table 3 5 PMS and Frequency Constraint Function Value Description Fin Fin 6 200MHz Specifies PLL input frequency Fin_pll Fin P 6 12 MHz Specifies PFD input frequency VCO_out M Fin P 500 1000 MHz Specifies VCO output frequency Fout M Fin P 2...

Page 1366: ...01 320 389 99 MHz 0110 390 449 99 MHz 0111 450 509 99 MHz 1000 510 559 99 MHz 1001 560 639 99 MHz 1010 640 689 99 MHz 1011 690 769 99 MHz 1100 770 869 99 MHz 1101 870 949 99 MHz 1110 950 1000 MHz 1111 3 4 1 2 Sample for Fout 80 MHz To set PMS value for Fout 80 MHz refer to the following table Case 1 Case 2 Fin 24MHz 30MHz Fin_pll 8MHz 10MHz P 5 0 3 3 M 8 0 80 64 S 2 0 8 8 VCO_out 640MHz 640MHz Fou...

Page 1367: ...ase 2 Fin 24MHz 30MHz Fin_pll 8MHz 10MHz P 5 0 3 3 M 9 0 125 100 S 2 0 1 1 VCO_out 1000MHz 1000MHz Fout 1000MHz 1000MHz 3 4 1 4 Sample for Fout 999 MHz To set PMS value for Fout 999 MHz refer to the following table Case 1 Case 2 Fin 27MHz 9MHz Fin_pll 9MHz 9MHz P 5 0 3 1 M 9 0 111 111 S 2 0 1 1 VCO_out 999MHz 999MHz Fout 999MHz 999MHz ...

Page 1368: ...nclude Compliance to MIPI CSI2 Standard Specification Version 1 0 Supports 1 2 3 or 4 data lanes Supports 1 channel Supports RAW8 RAW10 RAW12 and YUV422 8 bit All of User defined Byte based Data packet Interfaces Compatible with PPI Protocol to PHY Interface in MIPI D PHY Specification Version 0 90 ...

Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...

Page 1370: ...sync_SIntv 1 1 64 t2 Specifies the interval between last falling of DVALID and falling of HVALID Hsync_LIntv 2 2 66 t3 Specifies the interval between falling of HVALID and rising of next HVALID 1 t4 Specifies the interval between rising of HVALID and first rising of DVALID 0 t5 Specifies the interval between last falling of HVALID and falling of VVALID Vsync_EIntv 0 4095 t6 Specifies the interval ...

Page 1371: ... Alignment 4 4 2 YUV422 8 BIT ORDER YUV422 8 bit format data is stored as a UYVY sequence as specified in Table 4 2 Table 4 2 Data Order of YUV422 Alignment Format Stream Order of content 24 bit Alignment 32 bit Alignment DATA1 23 16 U1 DATA1 31 24 U1 DATA2 23 16 Y1 DATA1 23 16 Y1 DATA3 23 16 V1 DATA1 15 8 V1 YUV422 8 bit U1 Y1 V1 Y2 DATA4 23 16 Y2 DATA1 7 0 Y2 ...

Page 1372: ...e DP signal for MIPI DPHY slave data lane 2 XmipiSDP2 Dedicated DNDATA2 B Specifies the DN signal for MIPI DPHY slave data lane 2 XmipiSDN2 Dedicated DPDATA3 B Specifies the DP signal for MIPI DPHY slave data lane 3 XmipiSDP3 Dedicated DNDATA3 B Specifies the DN signal for MIPI DPHY slave data lane 3 XmipiSDN3 Dedicated DPCLK B Specifies the DP signal for MIPI DPHY slave clock lane XmipiSDPCLK Ded...

Page 1373: ...IS_INTMSK 0xFA60_0010 R W Specifies the interrupt mask register 0x0000_0000 CSIS_INTSRC 0xFA60_0014 R W Specifies the interrupt status register 0x0000_0000 CSIS_RESOL 0xFA60_002C R W Specifies the image resolution register 0x8000_8000 SDW_CONFIG 0xFA60_0038 R W Specifies the shadow register of configuration 0x0000_0000 SDW_RESOL 0xFA60_003C R Specifies the shadow register of resolution 0x8000_8000...

Page 1374: ...ng shadow registers 0 Reserved 15 9 Should be 0 0 WCLK_Src 8 Specifies wrapper clock source 0 PCLK 1 EXTCLK This bit determines the source of pixel clock which transfers image data to CAMIF 0 Reserved 7 5 Should be 0 0 SwRst 4 Specifies software reset 0 No reset 1 Reset All writable registers in CSIS return to their reset value After this bit is active for three cycles this bit is de asserted auto...

Page 1375: ...nterval As shown in Figure 4 2 t2 specifies this interval 6 h00 6 h3F cycle of Pixel clock 0 Vsync_SIntv 25 20 Specifies the interval between Vsync rising and first Hsync rising As shown in Figure 4 2 t1 specifies this interval 6 h00 6 h3F cycle of Pixel clock 0 Vsync_EIntv 19 8 Specifies the interval between last Hsync falling and Vsync falling As shown in Figure 4 2 t5 specifies this interval 12...

Page 1376: ...ta lane 3 6 Data lane 2 5 Data lane 1 4 Data lane 0 0 Not ULPS 1 ULPS 0 StopStateDat 7 4 Determines whether the data lane 3 0 is in Stop state 7 Data lane 3 6 Data lane 2 5 Data lane 1 4 Data lane 0 0 Not Stop state 1 Stop state F Reserved 3 2 Reserved 0 UlpsClk 1 Determines whether the clock lane is in ULPS 0 Not ULPS 1 ULPS 0 StopStateClk 0 Determines whether the clock lane is in Stop state 0 No...

Page 1377: ...ter 28 Receives non image data at odd frame and after image 0 Disables Interrupt 1 Enables Interrupt 0 Reserved 27 13 Reserved 0 MSK_ERR _SOT_HS 12 Specifies start of transmission error 0 Disables Interrupt 1 Enables Interrupt 0 Reserved 11 6 Reserved 0 MSK_ERR_LOST_FS 5 Lost of Frame Start packet 0 Disables Interrupt 1 Enables Interrupt 0 MSK_ERR_LOST_FE 4 Lost of Frame End packet 0 Disables Inte...

Page 1378: ...dicates the lost of Frame Start packet 0 ERR_LOST_FE 4 Indicates the lost of Frame End packet 0 ERR_OVER 3 Specifies overflow caused in image FIFO The outer bandwidth has to be faster than the input bandwidth However image FIFO can overflow due to user fault There are two ways to prevent overflow Tune output pixel clock faster than current WCLK_Src in CSIS_CTRL register should be set to 1 Then ass...

Page 1379: ... Input boundary 0x0001 0xFFFF 0x8080 4 6 1 8 Shadow Configuration Register CSIS_sdw_config R Address 0xFA60_0038 CSIS_SDW_CONFIG Bit Description Initial State Hsync_LIntv 31 26 Specifies current interval between Hsync falling and Hsync rising Line interval 0 Vsync_SIntv 25 20 Specifies current interval between Vsync rising and first Hsync rising 0 Vsync_EIntv 19 8 Specifies current interval betwee...

Page 1380: ...TA Bit Description Initial State HResol 31 16 Specifies current horizontal image resolution 0 VResol 15 0 Specifies current vertical image resolution 0 4 6 1 10 Packet Data Register CSIS_PKTDATA R Address 0xFA60_2000 0xFA60_3FFC CSIS_PKTDATA Bit Description Initial State PktData 31 0 Specifies packet data Unknown ...

Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...

Page 1382: ...3D The key features of G3D include Supports 3D and vector graphics on common hardware Uses Tile based architecture Incorporates Universal Scalable Shader engine which is a multi threaded engine with Pixel and Vertex Shader functionality Supports industry standard APIs such as OGL ES 1 1 and 2 0 OpenVG 1 0 Supports multiple operating systems such as Symbian Linux WinCE and future versions of these ...

Page 1383: ...es PVR TC1 PVR TC2 and ETC1 All YUV formats programmable Supports the same resolution for both frame buffer maximum size and texture maximum size Frame buffer maximum size 2048 x 2048 Texture maximum size 2048 x 2048 Controls texture filtering Bilinear Trilinear and Anisotropic Independent minimum and mag control Supports anti aliasing 4x Multisampling Programmable sample positions Supports indexe...

Page 1384: ...ogram size of 4096 instructions Contains dedicated pixel processing and vertex processing instructions Supports 2048 32 bit registers Supports SIMD execution unit related operations in 32 bit IEEE float 2 way 16 bit fixed point 4 way 8 bit integer 32 bit bitwise logical only Controls static and dynamic flow in Subroutine calls Loops Conditional branches Zero cost instruction predication Supports p...

Page 1385: ...ormats RGB A 3 3 2 4 4 4 4 5 5 5 5 5 5 1 5 6 5 8 8 8 8 and 8 8 8 0 Strides up to 2048 pixels Provides throughput Note All performance figures are affected by memory bandwidth The basic assumption is that 2D pipeline operates at x2 SGX540 core frequency All ROPs including color fill Two per clock Source Copy Two per clock Alpha Blends 2 per clock Rotated Blits 2 per clock Supports other 2D features...

Page 1386: ...S5PC110_UM 5 4BG3D 5 5 5 1 5 BLOCK DIAGRAM OF SGX540 Figure 5 1 SGX540 Block Diagram Figure 5 1 describes the terms used in the block diagram above ...

Page 1387: ...based on the PowerVR SGX core from Imagination Technologies 5 1 5 1 Coarse Grain Scheduler The Coarse Grain Scheduler CGS specifies the main system controller for the PowerVR SGX540 architecture It consists of two stages namely the Data Master Selector DMS and the Programmable Data Sequencer PDS The DMS processes requests from data masters and determines which tasks will be executed based on the r...

Page 1388: ...e GPDM responds to events within the system Each event causes an interrupt to the host or synchronized execution of a program on the PDS The program may or may not cause a subsequent task to be executed on the USSE 5 1 5 6 PDS The DMS and PDS controls whether vertices pixels or imaging data operations are processed by the USSE It controls the order location and size of these operations It also con...

Page 1389: ... data from the USSE and PDS and generates a macro tiled block of vertex index data This data is written to memory after removing the redundant data In addition to this the MTE generates a set of primitive blocks for the tiling engine A primitive block is a list of primitives where each primitive consists of its indices and fixed point x y of the vertices 5 1 5 12 Tiling Engine The Tiling Engine TE...

Page 1390: ...quests and parses position and TSP vertex data from internal 3D display list for visible primitives produced by the hidden surface removal engine ISP To set up triangle for the TSP the TSP FPU uses vertex data sourced from the TSP parameter fetch Multiple plane equations are produced that define how colors and texture coordinate sets are interpolated across primitives 5 1 5 17 Texture Address Gene...

Page 1391: ...ock domains partitioned internally to functional areas of the design It automatically controls clock gating if some blocks are not used at that time G3D block has its own power domain If you do not use G3D block then you can turn off the G3D block thoroughly by setting PMU The detail power states are summarized in Table 5 2 You can see the detailed explanation of power mode in Chapter PMU Table 5 ...

Page 1392: ... Table 5 3 Contact us for more information about registers descriptions operating systems support and 3D libraries Refer to http www khronos org about Open APIs like OGL ES and OpenVG Table 5 3 G3D Register Summary Module Name Start Address End Address Size G3D 0xF300_0000 0xF3FF_FFFF 16M bytes ...

Page 1393: ...ps o Baseline Profile Level 4 0 Except FMO Flexible Macroblock Ordering ASO Arbitrary Slice Ordering and RS Redundant Slice o Main Profile Level 4 0 o High Profile Level 4 0 Encoding High Profile Level 4 0 1920x1080 30fps 20Mbps o Baseline Main High Profile o Except FMO Flexible Macroblock Ordering ASO Arbitrary Slice Ordering and RS Redundant Slice o Support 8x8 transform in high profile o Suppor...

Page 1394: ... Support only one rectangular visual object o Only forward reversible VLC RVLC is supported o Support error resilience tool o Support post processing by re using H 263 in loop filter Encoding Advanced Simple Profile Level 5 D1 30fps 8Mbps o Support MPEG4 Simple Advanced Simple Profile Except data partitioning RVLC o Support only one rectangular visual object o Support only DC prediction ISO IEC 13...

Page 1395: ...nter prediction at encoding Number of reference frames Max 2 P frame 1 or 2 B frame 2 Search range Horizontal 64 Vertical 32 Motion estimation resolution 1 4 pel for H264 1 2 pel for MPEG4 Number of B frames 1 or 2 Supported modes H264 16x16 16x8 8x16 8x8 spatial direct mode MPEG4 4MV UMV Intra macroblock for encoding Support cyclic intra macroblock refresh Intra prediction Support 4x4 9 modes 16x...

Page 1396: ...on o Checking if firmware parsing is out of range H W o VLD error detection When there is no stream to decode before stream decoder is complete o Macroblock error detection When MB type is out of range i e 0 25 I slice 0 30 P slice 0 48 B slice o Sub MB type error detection When sub_MB_type or intra prediction mode is out of range i e Intra prediction mode 0 7 sub_mb_type 0 2 P slice 0 11 B slice ...

Page 1397: ...cate through registers in RG and risc2host interrupt generated by register in RG If RISC gets some interrupt or information from HW RISC set the registers to let host know the status of MFC Host clears the interrupt signal by resetting the MFC_RISC_HOST_INT register There are two AXI master interfaces in which both Port_A and Port_B are used for full performance As per the AXI standard MFC masters...

Page 1398: ...e bus arbiter Internal masters have an index 6 0 register controlled by firmware This register may be used to generate address which will be an output of AXI interface After getting an index the bus arbiter makes a decision which port to be used based on Index 6 Index 6 0 for Port_A and 1 for Port_B With Index 5 0 the bus arbiter get a base address from Q matrix SRAM The real address is calculated...

Page 1399: ...Luma Y 0 1 2 3 4pixel Y Y Y Y Chroma Cb Cr 4pixel Cb Cr Cb Cr Figure 6 2 Luma and Chroma Pixel 8 bytes aligned Reference picture is always made in the tile mode memory structure Decoding reconstruction image is made in 64 pixels x 32 lines tiled mode Encoding reconstruction image is made in 16 pixels x 16 lines tiled mode Current picture for encoding can be stored in two ways linear memory structu...

Page 1400: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 8 Figure 6 3 QCIF Image in 16pixel x 16lines 1x1 Tiled Mode ...

Page 1401: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 9 Figure 6 4 QCIF Image in 64pixel x 32lines 4x2 Tiled Mode ...

Page 1402: ...ext memory address 0x00000000 MFC_HOST2RISC_ARG4 0xF170_0040 R W Context memory size 0x00000000 MFC_RISC2HOST_ COMMAND 0xF170_0044 R W MFC to host command register MFC can respond to host using the MFC_RISC2HOST_COMMAND register 0x00000000 MFC_RISC2HOST_ARG1 0xF170_0048 R W MFC to host argument register This register is used with the MFC_RISC2HOST_COMMAND register 0x00000000 MFC_RISC2HOST_ARG2 0xF...

Page 1403: ...000000 MFC_PICTURE_STRUCT 0xF170_083C R W Field picture frame picture flag register at encoder 0x00000000 MFC_LF_CONTROL 0xF170_0848 R W Loop filter control 0x00000000 MFC_LF_ALPHA_OFF 0xF170_084C R W Loop filter alpha offset 0x00000000 MFC_LF_BETA_OFF 0xF170_0850 R W Loop filter beta offset 0x00000000 MFC_QP_OFFSET 0xF170_0C30 R W QP information offset from the DPB start address 0x00000000 MFC_QP...

Page 1404: ...x00000000 MFC_COMMON_SI_RG_ 11 0xF170_202C R Decoding status register 0x00000000 MFC_COMMON_CHx_R G_1 0xF170_2044 or 0xF170_2084 R W Start address of the CPB coded picture buffer in the external stream buffer 0x00000000 MFC_COMMON_CHx_R G_2 0xF170_2048 or 0xF170_2088 R W Decoding unit size register 0x00000000 MFC_COMMON_CHx_R G_3 0xF170_204C or 0xF170_208C R W Channel descriptor buffer address 0x0...

Page 1405: ...0_2010 R W Slice type of the current frame to be encoded 0x00000000 MFC_COMMON_SI_RG_ 5 0xF170_2014 R W Encoded luma address 0x00000000 MFC_COMMON_SI_RG_ 6 0xF170_2018 R W Encoded chroma address 0x00000000 MFC_COMMON_CHx_R G_1 0xF170_2044 or 0xF170_2084 R W Stream buffer start address at encoder 0x00000000 MFC_COMMON_CHx_R G_3 0xF170_204C or 0xF170_208C R W Stream buffer size register 0x00000000 M...

Page 1406: ...dding control register 0x00000000 ENC_COMMON_INTRA_ BIAS 0xF170_C588 R W Intra mode bias register for the macroblock mode decision 0x00000000 ENC_COMMON_BI _DIRECT_BIAS 0xF170_C58C R W Bi directional mode bias register for the macroblock mode decision 0x00000000 RC_CONFIG 0xF170_C5A0 R W Configuration of the rate control 0x00000000 RC_FRAME_RATE 0xF170_C5A4 R W Frame rate for the frame level RC 0x...

Page 1407: ...cutive video packet between header extension codes Undef METADATA_ENABLE 0x0038 W Enable storing the metadata information to the shared memory Undef METADATA_STATUS 0x003C R Getting the presence of the metadata Undef METADATA_DISPLAY_ INDEX 0x0040 R DPB number when concealed macroblock or QP is enabled Undef EXT_METADATA_STAR T_ADDR 0x0044 W The start address of the metadata memory Undef PUT_EXTRA...

Page 1408: ...a flushed command Undef FLUSH_CMD_INBUF2 0x0088 R Input buffer pointer of a flushed command Undef FLUSH_CMD_OUTBUF 0x008C R Output buffer pointer of a flushed command Undef NEW_RC_BIT_RATE 0x0090 W Updated target bit rate Undef NEW_RC_FRAME_RATE 0x0094 W Updated target frame rate Undef NEW_I_PERIOD 0x0098 W Updated intra period Undef ...

Page 1409: ... for VI 1 RSTN_MFCCORE 2 Soft reset for MFC core 1 RSTN_MC 1 Soft reset for MC 1 RSTN_RISC 0 Soft reset for RISC core 0 6 3 2 1 2 RISC to Host Interrupt Register MFC_RISC_HOST_INT R W Address 0xF170_0008 MFC_RISC_HOST_INT Bit Description Initial State Reserved 31 1 Reserved 0 INTERRUPT 0 0 Interrupt clear 1 Interrupt is raised by MFC 0 6 3 2 1 3 HOST2RISC Command Register MFC_HOST2RISC_COMMAND R W...

Page 1410: ...ivX 5 0 DivX 5 01 DivX 5 02 Decoding 9 DivX 5 03 and upper decoding 16 H 264 Encoding 17 MPEG4 Encoding 18 H 263 Encoding CLOSE_CH An instance ID to close should be specified SYS_INIT Size of the memory for the firmware should be specified currently 300KB 0 6 3 2 1 5 HOST2RISC Argument Registers MFC_HOST2RISC_ARG2 R W Address 0xF170_0038 MFC_HOST2RISC_ARG2 Bit Description Initial State Reserved 31...

Page 1411: ...3 2 1 8 RISC2HOST Command Register MFC_RISC2HOST_COMMAND R W Address 0xF170_0044 MFC_RISC2HOST_ COMMAND Bit Description Initial State RISC2HOST_COMMAN D 31 0 0 RISC2HOST_CMD_EMPTY 1 RISC2HOST_CMD_OPEN_CH_RET 2 RISC2HOST_CMD_CLOSE_CH_RET 3 Reserved 4 RISC2HOST_CMD_SEQ_DONE_RET 5 RISC2HOST_CMD_FRAME_DONE_RET 6 RISC2HOST_CMD_SLICE_DONE_RET 7 RISC2HOST_CMD_ENC_COMPLETE_RET 8 RISC2HOST_CMD_SYS_INIT_RET...

Page 1412: ...annel If 31 16 is not 0xFFFF a command in CH1 has been flushed If 15 0 is not 0xFFFF a command in CH0 has been flushed 6 3 2 1 10 RISC2HOST Argument Registers MFC_RISC2HOST_ARG2 R W Address 0xF170_004C MFC_RISC2HOST_ARG2 Bit Description Initial State DISP_ERROR_STATUS 31 16 Error status for the displayed frame Error codes are defined in 0 0 DEC_ERROR_STATUS 15 0 Error status for the decoded encode...

Page 1413: ... have different interpretation for each codec 0 6 3 2 1 15 Debug Information Output Register2 DBG_INFO_OUTPUT2 R Address 0xF170_0068 DBG_INFO_OUTPUT1 Bit Description Initial State EXCEPTION_STATUS 31 0 The status of the exception handler 0x01 Bus error handler 0x02 Illegal instruction handler 0x04 Tick handler 0x10 Trap handler 0x20 Align handler 0x40 Range handler 0x80 DTLB miss exception handler...

Page 1414: ... the channel is not open in INIT_BUFFERS 8 SEQ_START_ERROR_INI T_BUFFERS If SEQ_START is not complete before INIT_BUFFERS 9 INIT_BUFFER_ALREADY _CALLED If INIT_BUFFERS is already done and again INIT_BUFFERS is issued for the same channel 10 OPEN_CH_ERROR_FRA ME_START If the channel is not open ERROR in FRAME_START 11 SEQ_START_ERROR_FR AME_START If SEQ_START is not complete before FRAME_START 12 I...

Page 1415: ...han MIN_NUM_DPB and equal or smaller than 32 77 NULL_METADATA_INPUT _POINTER External metadata input structure address is null 78 NULL_DPB_POINTER The allocated DPB address is null 79 NULL_OTH_EXT_BUF_A DDR Other external buffers for decoder are NULL 80 NULL_MV_POINTER MV address is null Common HW errors 81 DIVIDE_BY_ZERO Divide by zero error 82 BIT_STREAM_BUF_EXHA UST Bit stream buffer exhausted ...

Page 1416: ...slice address 122 NON_PAIRED_FIELD_NO T_SUPPORTED Non paired field is not supported 123 NON_FRAME_DATA_RE CEIVED Frame data is not received Only header e g seq header SPS PPS SEI is received 124 INCOMPLETE_FRAME Incomplete frame data is received e g only part of slices are received 125 NO_BUFFER_RELEASED _FROM_HOST No Free buffer available All the buffers are either locked by host or they are anch...

Page 1417: ...R_PRIMARIES_UN KNOWN Invalid color primaries 161 TRASNFER_CHAR_UNK WON Invalid trasnsfer characterstics 162 MATRIX_COEFF_UNKNO WN Invalid matrix coefficients 163 NON_SEQ_SLICE_ADDR New slice address is not sequencial with respect to the old one 164 BROKEN_LINK Current GOV has B pictures whose anchor frame is in the previous GOV 165 FRAME_CONCEALED Error Concealment done by MFC 166 PROFILE_UNKOWN P...

Page 1418: ...MULTI FORMAT CODEC 6 26 Error Code Error Name Description 181 METADATA_NO_SPACE_ SLICE_SIZE Out of space for slice size output 182 RESOLUTION_WARNING Resoultion setting is not supported for given H 263 encoder profile ...

Page 1419: ...d 0 6 3 2 3 2 Channel B DRAM Base Address Register MFC_MC_DRAMBASE_ADDR_B R W Address 0xF170_050C MFC_MC_DRAMBASE_ ADDR_B Bit Description Initial State MC_DRAMBASE_ADDR_B 31 17 The DRAM base address must be aligned at 128KByte MFC s access range through port B is from DRAMBASE_ADDR_B to DRAMBASE_ADDR_B 256MByte 0x1180 Reserved 16 0 Reserved 0 6 3 2 3 3 MC Memory Controller Status Register MFC_MC_S...

Page 1420: ...OMMON_BASE_ADDR 11 6 3 2 4 1 For Port_A Common Baseram Register 0 63 Common Baseram Register 0 63 Address Description R W Initial State MFC_COMMON_BASE_ ADDR_0 16 0 0xF170_0600 Codec common memory region for start address R W X MFC_COMMON_BASE_ ADDR_63 16 0 0xF170_06FC Codec common memory region for start address R W X 6 3 2 4 2 For Port_B Common Baseram Register 64 127 Common Baseram Register 64 ...

Page 1421: ...FC_COMMON_BASE_ADDR_36 Neighbor information of stream parser DEC_SUB_ANCHOR_MV MFC_COMMON_BASE_ADDR_37 Neighbor information of stream parser DEC_STX_PARSER MFC_COMMON_BASE_ADDR_42 Syntax Parser Buffer DEC_LUMA_x MFC_COMMON_BASE_ADDR_64 95 Reconstructed luma plane DEC_CHROMA_x MFC_COMMON_BASE_ADDR_0 31 Reconstructed chroma plane MPEG2 Decoder Memory Region Register Name Description DEC_LUMA_x MFC_C...

Page 1422: ...tion of stream parser DEC_SUB_ANCHOR_MV MFC_COMMON_BASE_ADDR_37 Neighbor information of stream parser OVERLAP_TRANSFORM MFC_COMMON_BASE_ADDR_38 Information for Motion Compensation BITPLANE3 MFC_COMMON_BASE_ADDR_39 BITPLANE2 MFC_COMMON_BASE_ADDR_40 BITPLANE1 MFC_COMMON_BASE_ADDR_41 BitPlane DEC_LUMA_x MFC_COMMON_BASE_ADDR_64 95 Reconstructed luma plane DEC_CHROMA_x MFC_COMMON_BASE_ADDR_0 31 Reconst...

Page 1423: ...n y_size 32 8192 DEC_CHROMA_x align align x_size 128 align y_size 2 32 8192 H264DEC_VERT_NB_MV 16KB H264DEC_NB_IP 32KB H264DEC_CHROMA_x align align x_size 128 align y_size 2 32 8192 align align x_size 128 align y_size 4 32 8192 H264DEC_LUMA_x align align x_size 128 align y_size 32 8192 H264DEC_MV_x Quarter size of H 264 Luma DPB NOTE 1 ll linear information in this table should be aligned at 2KB w...

Page 1424: ...INTRA_MD_ADDR MFC_COMMON_BASE_ADDR_2 Upper row current pixel data storage region UPPER_INTRA_PRED_ADDR MFC_COMMON_BASE_ADDR_80 Upper row pre filter reconstruction data storage region NBOR_INFO_MPENC_ADDR MFC_COMMON_BASE_ADDR_1 Neighbor MB information storage region H 263 Encoder Memory Region Register Name in User s Manual Description ENC_DPB_Y0_ADDR MFC_COMMON_BASE_ADDR_7 Reconstructed Y0 buffer ...

Page 1425: ...ASE_ADDR_65 Reconstructed C1 buffer ENC_DPB_Y2_ADDR MFC_COMMON_BASE_ADDR_68 Reconstructed Y2 buffer ENC_DPB_C2_ADDR MFC_COMMON_BASE_ADDR_66 Reconstructed C2 buffer ENC_DPB_Y3_ADDR MFC_COMMON_BASE_ADDR_69 Reconstructed Y3 buffer ENC_DPB_C3_ADDR MFC_COMMON_BASE_ADDR_67 Reconstructed C3 buffer UPPER_MV_ADDR MFC_COMMON_BASE_ADDR_0 Upper row MV storage region DIRECT_COLZERO_FLAG_ADDR MFC_COMMON_BASE_AD...

Page 1426: ...DPB_C3_ADDR align align x_size 128 align y_size 2 32 8192 CH_SB_ADDR Configurable Limit1 Should be aligned at 2KB Limit2 Should be a multiple of 4KB Configurable Limit1 Should be aligned at 2KB Limit2 Should be a multiple of 4KB UPPER_MV_ADDR xMB_size 2 8byte xMB_size 2 8byte DIRECT_COLZERO_FLAG_ADDR xMB_size yMB_size 7 8 8byte xMB_size yMB_size 7 8 8byte UPPER_INTRA_MD_ADDR xMB_size 15 16 40byte ...

Page 1427: ...E_HEIGHT 12 0 Coded height of a picture field or frame 0 6 3 3 1 3 Profile Register MFC_PROFILE R W Address 0xF170_0830 MFC_PROFILE Bit Description Initial State Reserved 31 16 Reserved 0 LEVEL 15 8 Level in MPEG4 and H 264 In H 264 31 stands for level 3 1 and 9 stands for level 1b In MPEG4 3 stands for level 3 7 stands for level 3b and 9 stands for level 0b 0 Reserved 7 6 Reserved 0 PROFILE 5 0 M...

Page 1428: ...ilter disable indicator which corresponds to disable_deblocking_filter_idc 0 Enable 1 Disable 2 Disable at slice boundary MPEG4 1 Reserved 0 Deblocking filter enable post filter 0 Disable 1 Enable 0 NOTE 1 This register can be used by both encoders and decoders 2 This register is not effective for MPEG4 encoder 3 This register returns disable_deblocking_filter_idc from the bitstream for H 264 deco...

Page 1429: ... MFC_QP_OFFSET Bit Description Initial State MFC_QP_OFFSET 31 0 When MFC_QP_OUT_EN is set QP information is stored at the offset from the luma DPB address The unit of the offset is double word 64bits 0 6 3 3 1 9 QP Information Enable Register MFC_QP_OUT_EN R W Address 0xF170_0C34 MFC_QP_OUT_EN Bit Description Initial State Reserved 31 1 Reserved 0 MFC_QP_OUT_EN 0 If MFC_QP_OUT_EN is enabled the qu...

Page 1430: ...pixel_x_m1 I_XSIZE 1 pixel_y_m1 I_YSIZE 1 roundup_x pixel_x_m1 16 8 1 roundup_y pixel_x_m1 16 4 1 x_addr x_pos 4 linear_addr0 y_pos 0x1f 4 x_addr 0xf 2 linear_addr1 y_pos 6 0xff roundup_x x_addr 5 0x7f if x_addr 5 0x1 y_pos 5 0x1 bank_addr x_addr 4 0x1 else bank_addr 0x2 x_addr 4 0x1 physical_addr DRAM_BASE DPB_OFFSET QP_OFFSET linear_addr1 13 bank_addr 11 linear_addr0 qp_save_range pixel_y_minus ...

Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...

Page 1432: ... R W Address 0xF170_200C MFC_COMMON_SI_RG_4 R W Address 0xF170_2010 MFC_COMMON_SI_RG_5 R W Address 0xF170_2014 MFC_COMMON_SI_RG_6 R W Address 0xF170_2018 MFC_COMMON_SI_RG_7 R W Address 0xF170_201C MFC_COMMON_SI_RG_8 R W Address 0xF170_2020 MFC_COMMON_SI_RG_9 R W Address 0xF170_2024 MFC_COMMON_SI_RG_10 R W Address 0xF170_2028 MFC_COMMON_SI_RG_11 R W Address 0xF170_202C MFC_COMMON_SI_RG_12 R W Addre...

Page 1433: ...alization Decoder only 5 FRAME_START_REALLOC frame decoding for resolution change CH_INST_ID 15 0 Instance ID for a codec 6 3 3 2 4 CH1 Instance ID Register MFC_SI_CH1_INST_ID R W Address 0xF170_2080 MFC_SI_CH1_INST_ID Bit Description Initial State Reserved 31 19 Reserved 0 CH_DEC_TYPE 18 16 1 0 CH1 control 1 SEQ_START sequence header processing 2 FRAME_START frame decoding encoding 3 LAST_SEQ las...

Page 1434: ... 0xF170_205C MFC_COMMON_CH0_RG_8 R W Address 0xF170_2060 MFC_COMMON_CH0_RG_9 R W Address 0xF170_2064 MFC_COMMON_CH0_RG_10 R W Address 0xF170_2068 MFC_COMMON_CH0_RG_11 R W Address 0xF170_206C MFC_COMMON_CH0_RG_12 R W Address 0xF170_2070 MFC_COMMON_CH0_RG_13 R W Address 0xF170_2074 MFC_COMMON_CH0_RG_14 R W Address 0xF170_2078 MFC_COMMON_CH0_RG_15 R W Address 0xF170_207C MFC_COMMON_CH0_ RG_1 15 Bit D...

Page 1435: ...MFC_COMMON_CH1_RG_8 R W Address 0xF170_20A0 MFC_COMMON_CH1_RG_9 R W Address 0xF170_20A4 MFC_COMMON_CH1_RG_10 R W Address 0xF170_20A8 MFC_COMMON_CH1_RG_11 R W Address 0xF170_20AC MFC_COMMON_CH1_RG_12 R W Address 0xF170_20B0 MFC_COMMON_CH1_RG_13 R W Address 0xF170_20B4 MFC_COMMON_CH1_RG_14 R W Address 0xF170_20B8 MFC_COMMON_CH1_RG_15 R W Address 0xF170_20BC MFC_COMMON_CH1_RG_ 1 15 Bit Description In...

Page 1436: ...uld be read after decoding sequence header 0 6 3 3 3 3 Required Buffer Number Register MFC_COMMON_SI_RG_3 R Address 0xF170_200C MFC_COMMON_SI_RG_3 Bit Description Initial State MIN_NUM_DPB 31 0 Required decoded picture buffer number After decoding sequence header MFC sets the minimum number of required DPB buffers 0 6 3 3 3 4 Display Order Luminance Address Register MFC_COMMON_SI_RG_4 R Address 0x...

Page 1437: ...The status of the decoded picture to be displayed 5 4 Resolution change 0 No change 1 Resolution increased 2 Resolution decreased 3 Progressive interlace 0 Progressive frame 1 Interlace frame 2 0 Display status 0 Decoding only no display 1 Decoding and display 2 Display only 3 DPB is empty and decoding is finished 0 6 3 3 3 8 Frame Type Register MFC_COMMON_SI_RG_8 R Address 0xF170_2020 MFC_COMMON_...

Page 1438: ...RG_ 10 Bit Description Initial State DECODE_C_ADR 31 0 Chrominance address in decoding order 0 6 3 3 3 11 Decoding Status Register MFC_COMMON_SI_RG_11 R Address 0xF170_202C MFC_COMMON_SI_ RG_11 Bit Description Initial State Reserved 31 4 Reserved 0 DECODE_STATUS 3 0 The status of the decoded picture 3 Progressive interlace 0 Progressive frame 1 Interlace frame 2 0 Decoding status 0 Decoding only n...

Page 1439: ...ial State CH_ES_DEC_UNIT_ SIZE 31 0 Decoding unit size in the CPB 0 6 3 3 3 14 CH Descriptor Buffer Address MFC_COMMON_CHx_RG_3 R W Address 0xF170_204C or 0xF170_208C MFC_COMMON_CHx_ RG_3 Bit Description Initial State CH_DESC_ADDR 1 0 Channel descriptor buffer address 0 NOTE The address should be in Port_A i e the address should be between MC_DRAMBASE_ADDR_A and MC_DRAMBASE_ADDR_A 256MB 6 3 3 3 15...

Page 1440: ...s 4MB 0 NOTE CPB_SIZE align CH_ES_DEC_UNIT_SIZE 64 pow 2KB for H 264 and VC1 decoders when DMX is enabled where pow 2KB 1KB 2KB 4KB 8KB 4MB 6 3 3 3 18 Descriptor Buffer Size Register MFC_COMMON_CHx_RG_7 R W Address 0xF170_205C or 0xF170_209C MFC_COMMON_CHx_ RG_7 Bit Description Initial State DESC_SIZE 31 0 Descriptor buffer size register should be set before SEQ_START and FRAME_START The maximum d...

Page 1441: ..._ENABLE 31 Enable slice interface for decoding 0 Disable 1 Enable 0 CONFIG_DELAY_ENABLE 30 Enable configurable display delay for H 264 decoding 0 Disable 1 Enable 0 DISPLAY_DELAY 29 16 Number of frames for display delay MFC is forced to return frames for display even if DPB is not filled It is valid for H 264 decoder only 0 DMX_DISABLE 15 Host may generate the descriptor information on behalf of M...

Page 1442: ...nd of descriptors word is written to descriptor table to indicate end of descriptors ID 7 0 Offset 2 0 Start_addr 20 0 9 d0 Unit_size 22 0 32 d0 32 d0 ID start code suffix byte first byte after start code NALU header byte for H 264 and 0x82 for VC1 Offset nal start address 0x0 Start_addr nal start address 3 1 Unit_size size of NALU 6 3 3 3 22 Command Sequence Number Register MFC_COMMON_CHx_RG_11 R...

Page 1443: ...crements field by field 0 6 3 3 4 3 Write Pointer Register MFC_COMMON_SI_RG_3 R Address 0xF170_200C MFC_COMMON_SI_RG_3 Bit Description Initial State WRITE_POINTER 31 0 Stream buffer write pointer EDFU updates external memory address at the end of encoding a frame 0 6 3 3 4 4 Slice type Register MFC_COMMON_SI_RG_4 R W Address 0xF170_2010 MFC_COMMON_SI_RG_4 Bit Description Initial State ENC_SLICE_TY...

Page 1444: ...etween MC_DRAMBASE_ADDR_A and MC_DRAMBASE_ADDR_A 256MB 6 3 3 4 8 Stream Buffer Size Register MFC_COMMON_CHx_RG_3 R W Address 0xF170_204C or 0xF170_208C MFC_COMMON_CHx _RG_3 Bit Description Initial State BUFFER_SIZE 31 0 Buffer size of the encoded stream 0 6 3 3 4 9 Current Y Address Register MFC_COMMON_CHx_RG_4 R W Address 0xF170_2050 or 0xF170_2090 MFC_COMMON_CHx _RG_4 Bit Description Initial Sta...

Page 1445: ...ESERVED 31 0 Reserved 0 NOT_CODED 1 Current frame must be encoded into a not coded frame 0 I_FRAME 0 Current frame must be encoded into an I frame It will be effective at the next anchor frame 0 6 3 3 4 12 Auxiliary Host Command Register MFC_COMMON_CHx_RG_9 R W Address 0xF170_2064 or 0xF170_20A4 MFC_COMMON_CHx _RG_9 Bit Description Initial State HOST_WR_ADR 31 0 The address points to a space of sh...

Page 1446: ...d Sequence Number Register MFC_COMMON_CHx_RG_11 R W Address 0xF170_206C or 0xF170_20AC MFC_COMMON_CHx _RG_9 Bit Description Initial State CMD_SEQ_NUM 31 0 Command sequence number from the host The sequence number is used for in order processing of commands 0 ...

Page 1447: ...3 I P P I N N 1 P frames between two I frames 0 6 3 4 1 2 B Picture Recon Picture Writing Control Register ENC_B_RECON_WRITE_ON R W Address 0xF170_C508 ENC_B_RECON_WRITE_ON Bit Description Initial State Reserved 31 1 Reserved 0 B_RECON_ON 0 This register is used for debugging By default it is set to zero If it is set it is required to allocate the required memory 0 Disable recon data write at B fr...

Page 1448: ..._MB R W Address 0xF170_C510 ENC_MSLICE_MB Bit Description Initial State Reserved 31 16 Reserved 0 MSLICE_MB 15 0 The number of macroblocks in one slice Valid if MSLICE_MODE 0 and MSLICE_ENA 1 0 6 3 4 1 5 Byte Number of Multi slice Register ENC_MSLICE_BYTE R W Address 0xF170_C514 ENC_MSLICE_BYTE Bit Description Initial State MSLICE_BYTE 31 0 The number of byte count in one slice Valid if MSLICE_MOD...

Page 1449: ...current image padding 0 Reserved 30 24 Reserved 0 CR_PAD_VAL 23 16 Value for original CR image s padding when PAD_CTRL_ON is 1 0 CB_PAD_VAL 15 8 Value for original CB image s padding when PAD_CTRL_ON is 1 0 LUMA_PAD_VAL 7 0 Value for original Y image s padding when PAD_CTRL_ON is 1 0 6 3 4 1 9 Encoder Intra Mode Bias Register ENC_COMMON_INTRA_BIAS R W Address 0xF170_C588 ENC_INT_MASK Bit Descripti...

Page 1450: ... ENC_COMMON_ BI_DIRECT_BIAS 15 0 The register is used against the bi directional mode in the weighted macroblock mode decision Mode decision will be done by comparing 1 uni_direction_cost and 2 bi_direction_cost ENC_COMMON_BI_DIRECT_BIAS If the macroblock type is INTRA this register is of no effect To disable this option set ENC_COMMON_BI_DIRECT_BIAS to zero This register is effective in MPEG4 enc...

Page 1451: ...BOUND The QP of the next macroblocks can be changed as per the value of FR_RC_EN and MB_RC_EN The interpretation of FRAME_QP is varying as per RC_CONFIG 9 8 as follows RC_CONFIG 9 8 2 b00 Constant QP is applied to all macroblocks FRAME_QP is used for I frame P_FRAME_QP and B_FRAME_QP are used for P and B frames 2 b01 The QP of the next macroblocks can vary with macroblock adaptive scaling But it d...

Page 1452: ...Bit Description Initial State Reserved 31 14 Reserved 0 MAX_QP 13 8 Maximum quantization parameter The range is given as follows H 264 0 51 MPEG4 H 263 1 31 0 Reserved 7 6 Reserved 0 MIN_QP 5 0 Minimum quantization parameter The range is given as follows H 264 0 51 MPEG4 H 263 1 31 0 NOTE MAX_QP must be greater than or equal to MIN_QP 6 3 4 2 5 Reaction Coefficient Register RC_RPARA R W Address 0x...

Page 1453: ...region adaptive feature 0 Enable smooth region adaptive feature 1 Disable smooth region adaptive feature QP of smooth MB may be smaller than frame QP 0 STATIC_DISABLE 1 Disable static region adaptive feature 0 Enable static region adaptive feature 1 Disable static region adaptive feature QP of static MB may be smaller than frame QP 0 ACT_DISABLE 0 Disable MB activity adaptive feature 0 Enable MB a...

Page 1454: ...ter H264_ENC_NUM_OF_REF R W Address 0xF170_D010 H264_ENC_NUM_OF_REF Bit Description Initial State Reserved 31 5 Reserved 0 H264_ENC_P_NUM_OF_REF 6 5 The number reference pictures of P picture 1 1 reference frame 2 2 reference frame 0 H264_ENC_NUM_OF_REF 4 0 The maximum number of reference pictures 1 1 reference frame 2 2 reference frame 0 6 3 4 3 3 H 264 8X8 Transform Enable Flag Register H264_ENC...

Page 1455: ... Register 6 3 4 4 1 MPEG4 Quarter Pixel Interpolation Register MPEG4_ENC_QUART_PXL R W Address 0xF170_E008 MPEG4_ENC_QUART_PXL Bit Description Initial State Reserved 31 1 Reserved 0 MPEG4_QUART_PXL 0 0 Quarter pixel search disable 1 Quarter pixel search enable 0 ...

Page 1456: ...cate the shared memory and informs MFC of the buffer pointer through the HOST_WR_ADR register It is recommended to allocate the shared memory before the sequence header parsing through SEQ_START Since the number of fields in the shared memory is fixed in 0 host is required to allocate a buffer in the external memory to accommodate them Once the shared memory has been allocated host and MFC are abl...

Page 1457: ...pecific timestamp for this output buffer Undef 6 4 2 1 3 Get Frame Tag Top GET_FRAME_TAG_TOP R Offset 0x0008 GET_FRAME_TAG_ TOP Bit Description Initial State GET_FRAME_TAG_ TOP 31 0 Host reads a unique ID on display This tag returns an application specific ID for the progressive frame For an interlaced picture this tag returns an application specific ID for the top field Undef 6 4 2 1 4 Get Frame ...

Page 1458: ...014 PIC_TIME_BOTTOM Bit Description Initial State PIC_TIME_BOTTOM 31 0 Presentation time of the bottom field It is valid for the interlaced picture only Undef 6 4 2 1 7 Start Byte Number START_BYTE_NUM R W Offset 0x0018 START_BYTE_NUM Bit Description Initial State START_BYTE_NUM 31 0 An offset of the stream when it is not aligned Undef 6 4 2 1 8 Cropping Information One CROP_INFO1 R Offset 0x0020 ...

Page 1459: ...or level 1b In MPEG4 3 stands for level 3 and 7 stands for level 3b In VC1 simple and main profile define 0 Low 2 Medium 4 High Advanced profile defines 0 Level 0 1 Level 1 2 Level 2 3 Level 3 4 Level 4 In MPEG2 levels are defined as follows 4 High 6 High 1440 8 Main 10 Low Undef Reserved 7 5 Reserved Undef DISP_PIC_PROFILE 4 0 MPEG4 0 SP 1 ASP H 264 0 Baseline 1 Main 2 High H 263 0 Always bitstre...

Page 1460: ...Sequence header is generated on both SEQ_START and the first FRAME_START FRAME_SKIP_ENABLE 2 1 0 Frame skip is disabled The chance of the rate overshoot will be increased when the generate bitrate is high 1 Frame skip is enabled using maximum buffer size defined by level 2 Frame skip is enabled using VBV_BUFFER_SIZE defined by HOST Undef HEC_ENABLE 0 0 Header extension code HEC is disabled in the ...

Page 1461: ...OD 31 0 Insert a header extenstion code every HEC_PERIOD number of packets in the MPEG4 encoding Undef 6 4 2 2 5 P Frame QP and B Frame QP P_B_FRAME_QP W Offset 0x0070 P_B_FRAME_QP Bit Description Initial State Reserved 31 12 Reserved Undef B_FRAME_QP 11 6 The value is used for the B frame QP Undef P_FRAME_QP 5 0 The value is used for the P frame QP Undef NOTE The frame QPs are valid only if FR_RC...

Page 1462: ...0 Updated target bit rate at encoder which has the same format as RC_BIT_RATE 0xC5A8 It is valid only if RC_BIT_RATE_CHANGE 1 Undef 6 4 2 2 9 New RC Frame Rate NEW_RC_FRAME_RATE W Offset 0x0094 NEW_RC_FRAME_RATE Bit Description Initial State NEW_RC_FRAME_RATE 31 0 Updated target frame rate at encoder which has the same format as RC_FRAME_RATE 0xC5A4 It is valid only if RC_FRAME_RATE_CHANGE 1 Undef...

Page 1463: ... Bit Description Initial State ALLOCATED_CHROMA _DPB_SIZE 31 0 Size of chroma DPB that host allocated for decoding The allocated DPB size has to take into account the tile mode format Undef 6 4 2 3 3 Allocated Motion Vector Size Register ALLOCATED_MV_SIZE W Offset 0x006C ALLOCATED_MV_SIZE Bit Description Initial State ALLOCATED_MV_SIZE 31 0 Size of motion vector buffers that host allocated for dec...

Page 1464: ...ush Command Input Buffer 2 Register FLUSH_CMD_INBUF2 R Offset 0x0088 FLUSH_CMD_INBUF2 Bit Description Initial State FLUSH_CMD_INBUF2 31 0 11bit right shifted address of an input buffer pointer Encoder Current C address Decoder Descriptor buffer address Undef 6 4 2 3 7 1 4 2 3 7 Flush Command Output Buffer Register FLUSH_CMD_OUTBUF R Offset 0x008C FLUSH_CMD_OUTBUF Bit Description Initial State FLUS...

Page 1465: ...roblock info 1 Enable concealed macroblock info Undef QP_ENABLE 0 0 Disable QP info 1 Enable QP info Undef NOTE When QP_ENABLE 1 MFC sets MFC_QP_OUT_EN and MFC_QP_OFFSET internally METADATA_ENABLE and EXT_METADATA_START_ADDR should be set on SEQ_START 6 4 2 4 2 Metadata Status METADATA_STATUS R Offset 0x003C METADATA_STATUS Bit Description Initial State Reserved 31 1 Reserved Undef METADATA_STATUS...

Page 1466: ...ADDR should be set on SEQ_START 6 4 2 4 5 Put Extradata PUT_EXTRADATA W Offset 0x0048 PUT_EXTRADATA Bit Description Initial State Reserved 31 1 Reserved Undef PUT_EXTRADATA 0 Host informs MFC of the existence of extra metadata for each frame decoding Valid only if EXTRADATA_ENABLE is set 0 No extra metadata 1 Extra metadata exists Undef 6 4 2 4 6 Extradata Address Register EXTRADATA_ADDR W Offset ...

Page 1467: ... of the pointer through the EXT_METADATA_START_ADDR register The structure of the metadata buffer output is OpenMax compliant which is shown as follows typedef struct OMX_OTHER_EXTRADATATYPE OMX_U32 nSize OMX_VERSIONTYPE nVersion OMX_U32 nPortIndex OMX_EXTRADATATYPE eType OMX_U32 nDataSize OMX_U8 data 1 OMX_OTHER_EXTRADATATYPE Note that the start and end addresses should be informed through metada...

Page 1468: ...d memory and Figure 6 5 shows the shared memory input structure in more detail The shared memory input structure should be provided to MFC on the INIT_BUFFERS command Table 6 1 Payload in the Shared Memory Element Payload Metadata 0 No more metadata Metadata 1 QP information of each decoded macroblocks Metadata 2 An array of concealed macroblock numbers Metadata 3 VC1 parameters Metadata 4 SEI NAL...

Page 1469: ...ses are not used in storing metadata The size is communicated through the first fields in the shared memory input However since the VUI information is embedded in the sequence header SPS in H 264 there is no one to one relationship between VUI and metadata buffers MFC will return the appropriate VUI for a specific frame when there is an SPS change Figure 6 6 shows the metadata output in the shared...

Page 1470: ...LTI FORMAT CODEC 6 78 Figure 6 7 shows more detailed data structure for the VC1 parameters The numbers in the parenthesis specify the effective number of bits for each field Figure 6 6 Shared Memory Output for Decoders ...

Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...

Page 1472: ...re for encoders The input structure is provided to MFC for each FRAME_START command so that host updates the metadata buffer address accordingly Figure 6 9 shows the metadata output for encoders Currently there is only one metadata field for encoders in which the slice size metadata provides the offset and length information for multiple slices Figure 6 8 Shared Memory Input for Encoders Figure 6 ...

Page 1473: ...wing features 7 2 1 I O AND CONTROL ITU R BT 601 YCbCr 4 4 4 input format 10 Bit 4X over sampled CVBS output data to 1 channel 54 MHz DAC 7 2 2 VIDEO STANDARD COMPLIANCES FOR CVBS M NTSC NTSC J B D G H I PAL M PAL N PAL Nc PAL PAL 60 NTSC4 43 7 2 3 ANCILLARY DATA INSERTION EIA 608 compliant Closed Caption CC and Extended Data Service XDS IEC61880 ITU R BT 1119 compliant Wide Screen Signaling WSS E...

Page 1474: ...Waveform Generation QAM Modulation and YCbCr Video Processing AAF Affine Transformation luma chroma Anti Aliasing Filter OSF 4x Oversampling Filter VBI Ancillary data insertion during vertical blanking interval CTRL Register Control NOTE Image Mixer is directly connected with TVOUT and HDMI Thus to complete the connection you must configure MIXER_OUT_SEL in Clock Controller ...

Page 1475: ...858 samples per line 13 5 MHz sample rate Vertical frequency FV 59 94 Hz 525 lines per frame 7 4 2 625 50 HZ Video standard PAL BGHID PAL N and PAL Nc Horizontal frequency FH 15 625 kHz 864 samples per line 13 5 MHz sample rate Vertical frequency FV 50 00 Hz 625 lines per frame There are four kinds of discrete timing oscillation for sub carrier generation in TG module namely 7 4 3 3 579545 MHZ Vid...

Page 1476: ...24 525 1 2 3 4 5 6 7 8 9 10 22 261 262 263 264 265 266 267 268 269 270 271 272 285 286 Burst Begins with Positive Half Cycle Burst Phase 180o Relative to U Burst Begins with Negative Half Cycle Burst Phase 180o Relative to U HSYNC H 2 H 2 HSYNC 2 H 2 H 2 Analog Field 2 Analog Field 4 Burst Phase Burst Phase Analog Field 3 Equalizing Pulses Figure 7 2 Four Field NTSC M Sequence and Burst Blanking ...

Page 1477: ... 314 315 316 317 318 319 320 336 337 313 312 311 310 309 308 Analog Field 2 1 2 3 4 5 6 7 23 24 625 624 623 622 621 620 Analog Field 3 314 315 316 317 318 319 320 336 337 313 312 311 310 309 308 Analog Field 4 FieldFour FieldThree Field Two FieldOne Burst Blanking Intervals Burst Phase Reference Phase 90o 225o Relative to U Pal Switch 1 V Component Figure 7 3 Field PAL BGHIDNc Sequence and Burst B...

Page 1478: ... 315 316 317 318 319 320 336 337 313 312 311 310 309 308 Analog Field 6 1 2 3 4 5 6 7 23 24 625 624 623 622 621 620 Analog Field 7 314 315 316 317 318 319 320 336 337 313 312 311 310 309 308 Analog Field 8 Field Eight Field Seven FieldSix Field Five Burst Blanking Intervals Burst Phase Reference Phase 90o 225o Relative to U PAL Switch 1 V Component Figure 7 4 Eight Field PAL BGHIDNc Sequence and B...

Page 1479: ...e Video Timing 525 60 Hz Sample Rate 13 5 MHZ 12 Samples Digital Blanking Digital Active Line Total Line 144 Samples 0 143 720 Samples 144 863 864 Samples 0 863 Figure 7 6 Horizontal Blanking and Active Video Timing 625 50 Hz VIDEO 3 0 bits in SDO_CONFIG register controls all the timing signals in TG module Finally note that all the internal counters and discrete time oscillators operate with 54 M...

Page 1480: ...sponses are fully programmable since filter coefficients themselves are controllable Since linear FIR filters have symmetric coefficients 11 coefficients completely defines the filter responses The registers SDO_Y0 SDO_Y1 and SDO_Y11 are used to control the luminance filter response The register SDO_CB0 SDO_CB1 SDO_CB11 and SDO_CR0 SDO_CR1 SDO_CR11 are used to control the chrominance Cb and Cr fil...

Page 1481: ... SDO_CB6 6 7 7 7 SDO_CB7 13 14 15 15 SDO_CB8 28 28 2A 2B SDO_CB9 3F 3F 44 45 SDO_CB10 51 52 57 59 SDO_CB11 56 5A 5F 61 Table 7 3 Filter Coefficients of Anti aliasing Filters for Chrominance Cr Register 7 5 IRE Setup 7 3 Sync 7 5 IRE Setup 10 4 Sync 0 IRE Setup 7 3 Sync 0 IRE Setup 10 4 Sync SDO_CR0 0 0 0 0 SDO_CR1 0 0 0 0 SDO_CR2 0 0 0 0 SDO_CR3 0 0 0 0 SDO_CR4 0 0 0 0 SDO_CR5 2 1 2 2 SDO_CR6 5 9 ...

Page 1482: ...nses of CB and CR anti aliasing filters with the above settings Note that these filters are applied only to CVBS an S video Figure 7 7 Magnitude Response of CB and CR Anti Aliasing Filter 13 5 MHz Sampling Rate Figure 7 8 Phase Response of CB and CR Anti Aliasing Filter 13 5 MHz Sampling Rate ...

Page 1483: ... signals The physical waveform of EIA 608 closed caption and extended data service signals is as follows 10 5 0 25μs 12 91μs 7 Cycles of 0 5035 MHZ Clock Run In 40 IRE Blank Level Sync Level 3 58 MHZ Color Burst 9 Cycles Two 7 Bit Parity ASCIICharacters Data D0 D6 D0 D6 S T A R T P A R I T Y P A R I T Y 240 288 NS Rise Fall Times 2T Bar Shaping 50 2 IRE 10 5 0 25 μs 27 382 μs 33 764 μs Figure 7 9 ...

Page 1484: ...aping 11 20 0 30μs 49 1 0 44μs Figure 7 10 IEC 61880 Wide Screen Signaling This waveform is inserted at the 20 th line of 525 60 standard video The register SDO_ARMWSS525 is used to carry the 20 bit data into the waveform Bits b1 b0 define display aspect ratio control bit b7 b6 b5 b4 b3 b2 define copy control information and bits b13 b12 b11 b10 b9 b8 is used to specify the reserved signals Bits b...

Page 1485: ...MHZ Elements 500 MV 5 11 00 0 25 μs 27 4 μs 24 5 MHZ Elements Figure 7 11 ITU R BT 1119 Wide Screen Signaling This waveform is inserted at the 23rd line of 625 50 standard video The register SDO_ARMWSS625 is used for carrying the 14 bit data into the waveform Bits b3 b2 b1 b0 specify display aspect ratio control bits b7 b6 b5 b4 are used for enhanced TV service bits b10 b9 b8 is used for European ...

Page 1486: ...ideo data Y For the chrominance data paths base band chrominance data Cb and Cr are modulated with a sub carrier FSC along with the video standard that is C n U n sin 2πFSC n V n cos 2πFSC n where U n and V n denote properly scaled and offset versions of Cb n and Cr n respectively Then a pilot sinusoidal waveform called a burst is formed and added prior to the start of modulated chrominance data C...

Page 1487: ...tio are controlled by CSETUP CSYNC VSETUP and VSYNC bits in SDO_SCALE registers Note that the configuration of setup level and video to sync ratio in our implementation are set regardless of video standards and output format White Level Sync Level Blank Level 100 IRE 40 IRE Black Level 20 IRE 20 IRE 7 5 IRE White Yellow Cyan Green Magenta Red Blue Black Blank Level Color Saturation 3 58 MHZ Color ...

Page 1488: ...c Level Black Blank Level 100 IRE 43 IRE 21 43 IRE White Yellow Cyan Green Magenta Red Blue Black Color Burst 10 1 Cycles 21 43 IRE Blank Level Color Saturation Luminance Level Phase Hue Figure 7 14 PAL BGHIDNc Composite Video Signal with 75 Color Bars ...

Page 1489: ...mparison If YCbCr data converted to RGB data outside the RGB cube the CVBS sub module compensates the value so that the result falls within the RGB cube A constant luma and constant hue approach is used for this compensation The luminance Y is not altered while the chrominance Cb and Cr are limited to the maximum valid values having the same hue as the invalid color prior to limiting The SDO_RGB_C...

Page 1490: ...ion is done by making the filter response to boost at high frequency OSF operates in different ways according to the oversampling ratio the number of taps and the meanings of the coefficient registers are different for each case 4x oversampling case 13 5Msps interlaced mode It operates as 4 polyphase 95 tap FIR filters All the coefficient registers SDO_OSFC00_0 SDO_OSFC23_0 DAC 0 SDO_OSFC00_1 SDO_...

Page 1491: ...h 8 h 10 2 h 86 h 84 2 0 8 SDO_OSFC05 osf_coef11 h 11 h 83 0 8 osf_coef12 h 12 h 14 2 h 82 h 80 2 0 9 SDO_OSFC06 osf_coef13 h 13 h 81 0 9 osf_coef14 h 12 h 14 2 h 82 h 80 2 0 9 SDO_OSFC07 osf_coef15 h 15 h 79 0 9 osf_coef16 h 16 h 18 2 h 78 h 76 2 0 9 SDO_OSFC08 osf_coef17 h 17 h 77 0 9 osf_coef18 h 16 h 18 2 h 78 h 76 2 0 9 SDO_OSFC09 osf_coef19 h 19 h 75 0 9 osf_coef20 h 20 h 22 2 h 74 h 72 2 0 ...

Page 1492: ..._OSFC17 osf_coef35 h 35 h 59 h 11 h 35 10 osf_coef36 h 36 h 38 2 h 58 h 56 2 h 12 h 34 10 SDO_OSFC18 osf_coef37 h 37 h 57 h 13 h 33 10 osf_coef38 h 36 h 38 2 h 58 h 56 2 h 14 h 32 10 SDO_OSFC19 osf_coef39 h 39 h 55 h 15 h 31 10 osf_coef40 h 40 h 42 2 h 54 h 52 2 h 16 h 30 11 SDO_OSFC20 osf_coef41 h 41 h 53 h 17 h 29 11 osf_coef42 h 40 h 42 2 h 54 h 52 2 h 18 h 28 11 SDO_OSFC21 osf_coef43 h 43 h 51...

Page 1493: ...erence amplifier A 0 1uF ceramic capacitor must be connected between COMP and 3 3V PWR XdacCOMP Dedicated XdacIREF Input Full Scale Adjust control The full scale current drive on each of the output channels is determined by the value of a resistor RSET connected between this terminal and GND XdacIREF Dedicated XdacVREF Input Voltage reference for DAC An Internal voltage reference of nominally 1 22...

Page 1494: ..._Y4 0xF900_0054 R W Y AAF 5 th and 19 th Coefficient 0x0000_0000 SDO_Y5 0xF900_0058 R W Y AAF 6 th and 18 th Coefficient 0x0000_0000 SDO_Y6 0xF900_005C R W Y AAF 7 th and 17 th Coefficient 0x0000_0000 SDO_Y7 0xF900_0060 R W Y AAF 8 th and 16 th Coefficient 0x0000_0000 SDO_Y8 0xF900_0064 R W Y AAF 9 th and 15 th Coefficient 0x0000_0000 SDO_Y9 0xF900_0068 R W Y AAF 10 th and 14 th Coefficient 0x0000...

Page 1495: ...00 SDO_CRSCALE 0xF900_018C R W Hue Saturation Control for CR 0x0000_0080 SDO_CB_CR_OFFSET 0xF900_0190 R W Hue Sat Offset Control for CB CR 0x0000_0000 SDO_CVBS_CC_Y1 0xF900_0198 R W Color Compensation of CVBS Output 0x0200_0000 SDO_CVBS_CC_Y2 0xF900_019C R W Color Compensation of CVBS Output 0x03FF_0200 SDO_CVBS_CC_C 0xF900_01A0 R W Color Compensation of CVBS Output 0x0000_01FF SDO_OSFC00_0 0xF900...

Page 1496: ... 0xF900_02C8 R W OSF Coefficient 5 4 of Channel 1 0x0005_0004 SDO_OSFC03_1 0xF900_02CC R W OSF Coefficient 7 6 of Channel 1 0x0000_00FF SDO_OSFC04_1 0xF900_02D0 R W OSF Coefficient 9 8 of Channel 1 0x00F7_00FA SDO_OSFC05_1 0xF900_02D4 R W OSF Coefficient 11 10 of Channel 1 0x0000_0001 SDO_OSFC06_1 0xF900_02D8 R W OSF Coefficient 13 12 of Channel 1 0x000E_000A SDO_OSFC07_1 0xF900_02DC R W OSF Coeff...

Page 1497: ... 0x03D8_03E4 SDO_OSFC13_2 0xF900_0354 R W OSF Coefficient 27 26 of Channel 2 0x0000_0002 SDO_OSFC14_2 0xF900_0358 R W OSF Coefficient 29 28 of Channel 2 0x0038_0028 SDO_OSFC15_2 0xF900_035C R W OSF Coefficient 31 30 of Channel 2 0x0000_03FD SDO_OSFC16_2 0xF900_0360 R W OSF Coefficient 33 32 of Channel 2 0x03B0_03C7 SDO_OSFC17_2 0xF900_0364 R W OSF Coefficient 35 34 of Channel 2 0x0000_0005 SDO_OSF...

Page 1498: ...MCGMS625 are paired with above shadow registers respectively as follows SDO_ARMCC SDO_CC SDO_ARMWSS525 SDO_WSS525 SDO_ARMWSS625 SDO_WSS625 SDO_ARMCGMS525 SDO_CGMS525 SDO_ARMCGMS625 SDO_CGMS625 If MCU set values in the source registers with the prefix of SDO_ARMXXX they are not immediately effective But the values are copied into the corresponding shadow registers which are named with SDO_XXX They ...

Page 1499: ... stop mode of TVOUT 0 TVOUT clock off TVOUT requests for clock down to host controller If SDO is ready for clock down SDO_CLKCON 1 bit will be 1 The host controller should stop the clock for the TVOUT after that 1 TVOUT clock on TVOUT starts running NOTE Vertical Sync of TVENC s Timing Generator updates the SFRs of Video Processor and Image Mixer Thus SFRs are configured before this bit is enabled...

Page 1500: ...as zero do not modify 0 Reserved 15 14 Reserved read as zero do not modify 0 Reserved 13 12 Reserved read as zero do not modify 2 Reserved 11 10 Reserved read as zero do not modify 1 Selection of Video Mux for DAC 9 8 0 CVBS signal 1 Y signal 2 C signal 0 Reserved 7 Reserved read as zero do not modify 0 Reserved 6 Reserved read as zero do not modify 0 Reserved 5 Reserved read as zero do not modify...

Page 1501: ... Reserved read as zero do not modify 0 Reserved 2 Reserved read as zero do not modify 1 Setup Level Selection for Composite 1 0 0 IRE 1 7 5 IRE This setting is valid if bit 6 of SDO_CONFIG register is set to composite 1 Video to Sync Ratio Selection for Composite 0 0 10 4 1 7 3 This setting is valid if bit 6 of SDO_CONFIG register is set to composite 0 NOTE The Table 7 5 and Table 7 6 according to...

Page 1502: ...tion of Video Standard in SDO_CONFIG Register is set to NTSC M PAL M PAL 60 or NTSC 4 43 0 No Ancillary Data Insertion 1 US Closed Caption Insertion at 21H 2 US Closed Caption Insertion at 21H and 284H 3 Reserved for Other Use Otherwise No Ancillary Data Insertion NOTE This setting is valid if the bit 6 of SDO_CONFIG register is set to composite Note European closed caption is not supported 3 Rese...

Page 1503: ... Offset of Channel 0 Signal Scale Conversion 25 16 Function F x X Offset Gain 0x1FF 511 0x001 1 0x000 0 0x3FF 1 0x200 512 This setting is valid if the bit 6 of SDO_CONFIG register is set to component 000 Reserved 15 12 Reserved read as zero do not modify 0 Gain of Channel 0 Signal Scale Conversion 11 0 Function F x X Offset Gain 0x000 x0 0 0x400 x0 5 0x800 x1 0 0xC00 x1 5 0xFFF x1 999512 2048 2 1 ...

Page 1504: ...End Position 7 0 0x3F 4 667 usec 0x01 0 074 usec 0x00 0 000 usec 0xFF 0 074 usec 0x40 4 741 usec 00 7 12 1 7 SDO SCH Phase Control Register SDO_SCHLOCK R W Address 0xF900_0038 SDO_SCHLOCK Bit Description Initial State Reserved 31 1 Reserved read as zero do not modify 0 Color Sub Carrier Phase Adjustment 0 0 Never adjusted 1 Every field is adjusted such that color sub carrier frequency and horizont...

Page 1505: ...ield Counter Modulo 1001 25 16 This counter is used for 59 94 60 0 Hz field rate conversion 0 Reserved 15 2 Reserved read as zero do not modify 0 Field ID 1 0 Top field 1 Bottom field 1 Field ID with Progressive Interlaced Indication 0 If the SDO_CONFIG register is set to interlaced 0 Top field 1 Bottom field If the SDO_CONFIG register is set to progressive this bit would be fixed to zero 0 ...

Page 1506: ...SDO_CB4 R W Address 0xF900_0090 7 12 1 27 SDO Anti Aliasing Filter Coefficients SDO_CB5 R W Address 0xF900_0094 7 12 1 28 SDO Anti Aliasing Filter Coefficients SDO_CB6 R W Address 0xF900_0098 7 12 1 29 SDO Anti Aliasing Filter Coefficients SDO_CB7 R W Address 0xF900_009C 7 12 1 30 SDO Anti Aliasing Filter Coefficients SDO_CB8 R W Address 0xF900_00A0 7 12 1 31 SDO Anti Aliasing Filter Coefficients ...

Page 1507: ...3 ratio 0x25D at 7 5 IRE setup and 10 4 ratio 0x281 at 0 IRE setup and 7 3 ratio 0x28F at 0 IRE setup and 7 3 ratio for CB channel 0x1F3 at 7 5 IRE setup and 7 3 ratio 0x200 at 7 5 IRE setup and 10 4 ratio 0x21E at 0 IRE setup and 7 3 ratio 0x228 at 0 IRE setup and 7 3 ratio and for CR channel 0x2C0 at 7 5 IRE setup and 7 3 ratio 0x2D1 at 7 5 IRE setup and 10 4 ratio 0x2C0 at 0 IRE setup and 7 3 r...

Page 1508: ...ff Control of CVBS Color Compensation 0 0 On 1 Bypass The CVBS color compensation imposes a saturation operation on the CVBS data Values which exceed DAC conversion range 0 1023 in 10 bit resolution would be saturated 0 7 12 1 47 SDO Brightness Control for Y SDO_YSCALE R W Address 0xF900_0184 SDO_YSCALE Bit Description Initial State Reserved 31 24 Reserved read as zero do not modify 0 Gain of Brig...

Page 1509: ...ontrol of CB with F CB CR CB Gain0 CR Gain1 Offset 0x0FF 1 992188 128 2 1 128 0x080 1 0 0x000 0 0 0x180 1 0 0x100 2 0 This setting is valid for all the CVBS Y C YpbPr RGB outputs 80 Reserved 15 9 Reserved read as zero do not modify 0 Gain1_CB 8 0 Gain1 of Hue Saturation Control of CB with F CB CR CB Gain0 CR Gain1 Offset 0x0FF 1 992188 128 2 1 128 0x080 1 0 0x000 0 0 0x180 1 0 0x100 2 0 This setti...

Page 1510: ...ontrol of CR with F CB CR CB Gain0 CR Gain1 Offset 0x0FF 1 992188 128 2 1 128 0x080 1 0 0x000 0 0 0x180 1 0 0x100 2 0 This setting is valid for all the CVBS Y C YpbPr RGB outputs 00 Reserved 15 9 Reserved read as zero do not modify 0 Gain1_CR 8 0 Gain1 of Hue Saturation Control of CR with F CB CR CB Gain0 CR Gain1 Offset 0x0FF 1 992188 128 2 1 128 0x080 1 0 0x000 0 0 0x180 1 0 0x100 2 0 This setti...

Page 1511: ...ead as zero do not modify 0 Offset_CB 9 0 Offset of Hue Saturation Control of CB with 0x1FF 511 0x001 1 0x000 0 0x3FF 1 0x200 512 This setting is valid for all the CVBS Y C YpbPr RGB outputs 00 7 12 1 51 Color Compensation Control Register for CVBS Output SDO_CVBS_CC_Y1 R W Address 0xF900_0198 SDO_CVBS_CC_Y1 Bit Description Initial State Reserved 31 26 Reserved read as zero do not modify 0 Y_Lower...

Page 1512: ...ro do not modify 0 Radius_CVBS_Corn 8 0 Radius of Legal CVBS Corn 0x1FF 511 0x000 0 1FF It should be set such that Y_Top_CVBS_Corn Y_Upper_Mid_CVBS_Corn Y_Lower_Mid_CVBS_Corn Y_Bottom_CVBS_Corn It is highly recommended for users not to alter their reset values This setting is valid if SDO_CCCON 0 is set to On 7 12 1 54 SDO 525 Line Component Front Back Porch Position Control Register SDO_CSC_525_P...

Page 1513: ...ved 31 26 Reserved read as zero do not modify 0 625 line back porch position 25 16 Back porch start position 96 Reserved 15 10 Reserved read as zero do not modify 0 625 line front porch position 9 0 Front porch start position 35C Resolution in progressive 1 27MHz resolution in interlaced 1 13 5MHz Compare line count value with porch position One Line Count Value of 525 Line One Line Count Value of...

Page 1514: ...00_0200 SDO_OSFCN_0 N is 00 23 Bit Description Initial State osf_coef 2xN 1 23 16 27 16 2xN 1 th oversampling filter coefficient Signed 8 12bit integer Actual value is osf_coef 210 osf_coef 2xN 7 0 11 0 2xN th oversampling filter coefficient Signed 8 12bit integer Actual value is osf_coef 210 Refer to below table ...

Page 1515: ...7 SDO Oversampling 0 Filter Coefficient SDO_OSFC11_0 R W Address 0xF900_022C 7 12 1 68 SDO Oversampling 0 Filter Coefficient SDO_OSFC12_0 R W Address 0xF900_0230 7 12 1 69 SDO Oversampling 0 Filter Coefficient SDO_OSFC13_0 R W Address 0xF900_0234 7 12 1 70 SDO Oversampling 0 Filter Coefficient SDO_OSFC14_0 R W Address 0xF900_0238 7 12 1 71 SDO Oversampling 0 Filter Coefficient SDO_OSFC15_0 R W Add...

Page 1516: ...00_ 02C0 SDO_OSFCN_1 N is 00 23 Bit Description Initial State osf_coef 2xN 1 23 16 27 16 2xN 1 th oversampling filter coefficient Signed 8 12bit integer Actual value is osf_coef 210 osf_coef 2xN 7 0 11 0 2xN th oversampling filter coefficient Signed 8 12bit integer Actual value is osf_coef 210 Refer to below table ...

Page 1517: ...SDO Oversampling 1 Filter Coefficient SDO_OSFC11_1 R W Address 0xF900_02EC 7 12 1 92 SDO Oversampling 1 Filter Coefficient SDO_OSFC12_1 R W Address 0xF900_02F0 7 12 1 93 SDO Oversampling 1 Filter Coefficient SDO_OSFC13_1 R W Address 0xF900_02F4 7 12 1 94 SDO Oversampling 1 Filter Coefficient SDO_OSFC14_1 R W Address 0xF900_02F8 7 12 1 95 SDO Oversampling 1 Filter Coefficient SDO_OSFC15_1 R W Addre...

Page 1518: ...900_ 0320 SDO_OSFCN_2 N is 00 23 Bit Description Reset Value osf_coef 2xN 1 23 16 27 16 2xN 1 th oversampling filter coefficient Signed 8 12bit integer Actual value is osf_coef 210 osf_coef 2xN 7 0 11 0 2xN th oversampling filter coefficient Signed 8 12bit integer Actual value is osf_coef 210 Refer to below table ...

Page 1519: ... SDO Oversampling 2 Filter Coefficient SDO_OSFC11_2 R W Address 0xF900_034C 7 12 1 116 SDO Oversampling 2 Filter Coefficient SDO_OSFC12_2 R W Address 0xF900_0350 7 12 1 117 SDO Oversampling 2 Filter Coefficient SDO_OSFC13_2 R W Address 0xF900_0354 7 12 1 118 SDO Oversampling 2 Filter Coefficient SDO_OSFC14_2 R W Address 0xF900_0358 7 12 1 119 SDO Oversampling 2 Filter Coefficient SDO_OSFC15_2 R W ...

Page 1520: ...oef44 613 osf_coef13 14 osf_coef29 56 osf_coef45 651 osf_coef14 1 osf_coef30 3 osf_coef46 308 osf_coef15 0 osf_coef31 0 osf_coef47 1024 2x Oversampling Case Coefficient Flat response up to 12MHz Coefficient Value Coefficient Value Coefficient Value osf_coef00 0 osf_coef16 0 osf_coef32 19 osf_coef01 0 osf_coef17 0 osf_coef33 0 osf_coef02 0 osf_coef18 0 osf_coef34 28 osf_coef03 0 osf_coef19 0 osf_co...

Page 1521: ...ption Initial State Reserved 31 18 Reserved read as zero do not modify 0 ref_bb_level 17 8 Black level setting value It specifies the level during horizontal active video for black burst signal The recommended values are NTSC 0x11A include 7 5 IRE setup PAL 0xFB without setup 0x11A Reserved 7 6 Reserved read as zero do not modify 0 sel_bb_chan 5 4 Black burst BB test channel selection DAC0 DAC1 DA...

Page 1522: ... even if the request is disabled Only the request to MCU will be disabled 0 7 12 1 132 SDO Closed Caption Data Registers SDO_ARMCC R W Address 0xF900_03C0 SDO_ARMCC Bit Description Initial State Reserved 31 16 Reserved read as zero do not modify 0 Display Control Character of Closed Caption Data 15 8 Bit alignment of the Display Control Character register is in their incoming order The first incom...

Page 1523: ... used for copy control b7 b6 00 copying permitted 01 one copy permitted 10 reserved 11 no permission to copy b9 b8 reserved b10 0 not analog pre recorded medium 1 analog pre recorded medium b13 b12 b11 reserved 0 Word 1 of WSS 525 Data 5 2 Bit alignment of the Word 1 register is according to their incoming order The first incoming bit becomes LSB i e Word 1 5 2 b5 b4 b3 b2 where bn represents data...

Page 1524: ...ncoming order n The Group D data are used for surround sound and copy control b11 surround sound no yes b12 copyright no copyright asserted or unknown copyright asserted b13 copy protection copying not restricted copying restricted 0 Group C of WSS 625 Data 10 8 Bit alignment of the Group C register is according to their incoming order The first incoming bit becomes LSB i e Group C 10 8 b10 b9 b8 ...

Page 1525: ...ive ColorPlus b6 helper signals not present present b7 fixed to 0 0 Group A of WSS 625 Data 3 0 Bit alignment of the Group A register is according to their incoming order The first incoming bit becomes LSB i e Group A 3 0 b3 b2 b1 b0 where bn represents data bit with their incoming order n The Group A data are used for display aspect ratio control b3 b2 b1 b0 1000 4 3 full format 576 lines 0001 14...

Page 1526: ...er is according to their incoming order The first incoming bit becomes LSB i e Word 2 13 6 b13 b12 b11 b10 b9 b8 b7 b6 where bn represents data bit with their incoming order n The Word 2 data are used for copy control b7 b6 00 copying permitted 01 one copy permitted 10 reserved 11 no copying permitted b9 b8 reserved b10 0 not analog pre recorded medium 1 analog pre recorded medium b13 b12 b11 rese...

Page 1527: ... Word 0 register is according to their incoming order The first incoming bit becomes LSB i e Word 0 1 0 b1 b0 where bn represents data bit with their incoming order n The Word 0 data are used for display aspect ratio control b1 b0 00 4 3 aspect ratio normal 01 16 9 aspect ratio anamorphic 10 4 3 aspect ratio letterbox 11 reserved 0 ...

Page 1528: ... incoming order n The Group D data are used for surround sound and copy control b11 surround sound no yes b12 copyright no copyright asserted or unknown copyright asserted b13 copy protection copying not restricted copying restricted 0 Group C of CGMS A 625 Data 10 8 Bit alignment of the Group C register is according to their incoming order The first incoming bit becomes LSB i e Group C 10 8 b10 b...

Page 1529: ... Data 3 0 Bit alignment of the Group A register is according to their incoming order The first incoming bit becomes LSB i e Group A 3 0 b3 b2 b1 b0 where bn represents data bit with their incoming order n The Group A data are used for display aspect ratio control b3 b2 b1 b0 1000 4 3 full format 576 lines 0001 14 9 letterbox center 504 lines 0010 14 9 letterbox top 504 lines 1011 16 9 letterbox ce...

Page 1530: ...on Initial State Reserved 31 20 Reserved read as zero do not modify 0 CRC of WSS 525 Data 19 14 0 Word 2 of WSS 525 Data 13 6 0 Word 1 of WSS 525 Data 5 2 0 Word 0 of WSS 525 Data 1 0 If MCU set values of SDO_ARMWSS525 the values are copied into this shadow register at the next vertical sync interrupt Do not set values to this shadow register 0 7 12 2 3 SDO WSS 625 Data Shadow Registers SDO_WSS625...

Page 1531: ...s are copied into this shadow register at the next vertical sync interrupt Do not set values to this shadow register 0 7 12 2 5 SDO CGMS A 625 Data Registers SDO_CGMS625 R W Address 0xF900_0394 SDO_CGMS625 Bit Description Initial State Reserved 31 14 Reserved read as zero do not modify 0 Group D of CGMS A 625 Data 13 11 0 Group C of CGMS A 625 Data 10 8 0 Group B of CGMS A 625 Data 7 4 0 Group A o...

Page 1532: ...te Rate 10 bit Current Output DAC 1 3Vpp Triple Output Compliance Range Internal Voltage Reference Fine Full Scale control 91 1 114 8 Power Down Mode 7 13 3 CORE PORT DESCRIPTION Table 7 5 Port Description of Video DAC Name Width I O Description VREF AI Voltage reference for DAC An Internal voltage reference of nominally 1 22V is provided Is driven with an external reference source IREF AI Full Sc...

Page 1533: ...en COMP and AVDD30A1 I O Type Abbreviation AI Analog Input DI Digital Input AO Analog Output AP Analog Power AG Analog Ground DP Digital Power DG Digital Ground LP Logic Power LG Logic Ground 7 13 4 FULL SCALE VOLTAGE MODIFICATION Table 7 6 Recommended RSET and RO According to Full Scale Voltage Full Scale Voltage RSET RO 1 3V 1 2k Tolerance 1 ohm 75 Tolerance 5 ohm 1 0V 1 54k Tolerance 1 ohm 75 T...

Page 1534: ...on ideal interpolation filter is basically implies distortions in chrominance components However in the case of CVBS signal the chrominance component and the luminance component are together to be mixed and transmitted via one channel Then parts of the interpolation error appears in luminance parts if the CVBS signal is separated into luminance component and chrominance components by the comb filt...

Page 1535: ...llows Supports BOB TILE YUV420 NV12 type Note refer to MFC user s manual for TILE Input source size up to 1920x1080 min 32x4 Produce YCbCr 4 4 4 outputs to help MIXER to blend video and graphics Supports 1 4X to 16X vertical scaling with 4 tap 16 phase poly phase filter Supports 1 4X to 16X horizontal scaling with 8 tap 16 phase poly phase filter Supports Pan Scan Letterbox and NTSC PAL conversion...

Page 1536: ...ideo Processor Components in video processor DMA DMA reads the image from memory Input Line Memory It stores data to process the image Registers The configuration of Video Processor 2D IPC and Vertical Scaler It performs IPC and vertical scaling Horizontal Scaler Horizontal scaling and post processing ...

Page 1537: ...mode is one of fundamental de interlacing algorithm Video mode de interlacing can be further broken down into inter filed and intra field processing Particular Intra field processing in video mode is the simplest method to generate additional scan lines using only information in the original field The computer industry has coined this technique as BOB BOB in VP consists of Intra field or inter fie...

Page 1538: ...rsion IPC plays role to convert interlaced to progressive It is distinguished with vertical x2 scale Figure 8 4 Difference Between IPC and X2 Scale up IPC engine executes Edge Detection Function which is based on the edge diagnosis method This enables IPC to estimate edge line and display more natural image ...

Page 1539: ...e Address for C of Top Field frame 0x0000_0000 VP_BOT_C_PTR 0xF910_0034 R W Specifies the Base Address for C of Bottom Field 0x0000_0000 VP_ENDIAN_MODE 0xF910_03CC R W Specifies the Big Little Endian Mode Selection 0x0000_0000 VP_SRC_H_POSITION 0xF910_0044 R W Specifies the Horizontal Offset in the Source Image 0x0000_0000 VP_SRC_V_POSITION 0xF910_0048 R W Specifies the Vertical Offset in the Sour...

Page 1540: ...p Poly phase Filter Coefficients for Luminance Horizontal Scaling 0x0000_0000 VP_POLY8_Y1_HH 0xF910_0088 R W Specifies the 8 Tap Poly phase Filter Coefficients for Luminance Horizontal Scaling 0x0000_0000 VP_POLY8_Y2_LL 0xF910_008C R W Specifies the 8 Tap Poly phase Filter Coefficients for Luminance Horizontal Scaling 0x0000_0000 VP_POLY8_Y2_LH 0xF910_0090 R W Specifies the 8 Tap Poly phase Filter...

Page 1541: ...4 Tap Poly phase Filter Coefficients for Luminance Vertical Scaling 0x0000_0000 VP_POLY4_Y1_HL 0xF910_0104 R W Specifies the 4 Tap Poly phase Filter Coefficients for Luminance Vertical Scaling 0x0000_0000 VP_POLY4_Y1_HH 0xF910_0108 R W Specifies the 4 Tap Poly phase Filter Coefficients for Luminance Vertical Scaling 0x0000_0000 VP_POLY4_Y2_LL 0xF910_010C R W Specifies the 4 Tap Poly phase Filter C...

Page 1542: ...Poly phase Filter Coefficients for Chrominance Horizontal Scaling 0x0000_0000 VP_POLY4_C1_LH 0xF910_0140 R W Specifies the 4 Tap Poly phase Filter Coefficients for Chrominance Horizontal Scaling 0x0000_0000 VP_POLY4_C1_HL 0xF910_0144 R W Specifies the 4 Tap Poly phase Filter Coefficients for Chrominance Horizontal Scaling 0x0000_0000 VP_POLY4_C1_HH 0xF910_0148 R W Specifies the 4 Tap Poly phase Fi...

Page 1543: ...Specifies the Line Equation for Contrast Duration 4 0x0000_0000 PP_LINE_EQ5 0xF910_022C R W Specifies the Line Equation for Contrast Duration 5 0x0000_0000 PP_LINE_EQ6 0xF910_0230 R W Specifies the Line Equation for Contrast Duration 6 0x0000_0000 PP_LINE_EQ7 0xF910_0234 R W Specifies the Line Equation for Contrast Duration 7 0x0000_0000 PP_BRIGHT_OFFSET 0xF910_0238 R W Specifies the Brightness Of...

Page 1544: ...xF910_01C4 R Specifies the Width of the Display 0x0000_0000 VP_DST_HEIGHT_S 0xF910_01C8 R Specifies the Height of the Display 0x0000_0000 VP_H_RATIO_S 0xF910_01CC R Specifies the Horizontal Zoom Ratio of SRC DST 0x0000_0000 VP_V_RATIO_S 0xF910_01D0 R Specifies the Vertical Zoom Ratio of SRC DST 0x0000_0000 PP_BYPASS_S 0xF910_0258 R Specifies the Disable the Post Image Processor 0x0000_0000 PP_SATU...

Page 1545: ... to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_Y2CB_COEF_ S 0xF910_029C R Specifies the Y to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_CB2CB_COEF _S 0xF910_02A0 R Specifies the CB to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_CR2CB_COEF _S 0xF910_02AC R Specifies the CR to Y CSC Coefficient Setting 0x0000_0000 PP_CSC_Y2CR_COEF_ S 0xF910_02A8 R Specifies the Y to Y CSC Coefficient Setting 0x...

Page 1546: ...bles Note The SFRs of Video Processor and Image Mixer is updated by Vertical Sync of TVENC s Timing Generator Thus SFRs are configured before this bit is enabled The sequence to enable TVSS is as follows VP MIXER TVENC HDMI Also because SFRs are updated by Verical Sync the disabling sequence is following as VP MIXER TVNEC HDMI R W 0 8 4 1 2 Video Processor Software Reset VP_SRESET R W Address 0xF9...

Page 1547: ...adow registers are updated and this register is cleared by H W at the rising edge of vertical sync Shadow registers are listed in SHADOW REGISTER MAP table 0 8 4 1 4 Video Processor Input Field ID Control Register VP_FIELD_ID R W Address 0xF910_000C VP_FIELD_ID Bit Description Initial State Reserved 31 1 Reserved read as zero do not modify 0 VP_FILED_ID 0 When VP_MODE 2 is set to high this bit sho...

Page 1548: ...r two lines while it reads line data 0 OFF 1 ON 0 MEM_MODE 4 0 Linear Mode 1 Tile Mode refer to MFC user s manual 0 CROMA_EXPANSION 3 If it is set to 0 only refer to the chrominance of TOP filed But set to 1 it uses the chrominance both TOP and BOTTOM 0 Using only C_TOP_PTR 1 Using both C_TOP_PTR and C_BOT_PTR 0 FIELD_ID_AUTO_TOGGLING 2 0 FIELD_ID is defined by user 1 FIELD_ID is automatically tog...

Page 1549: ...S5PC110_UM 8 7BVIDEO PROCESSOR 8 15 The guide of configuration Figure 8 5 Examples of Usage Cases ...

Page 1550: ...essor Chrominance Image Size Control Register VP_IMG_SIZE_C R W Address 0xF910_0018 VP_ IMG _SIZE_C Bit Description Initial State Reserved 31 30 Reserved read as zero do not modify 0 VP_IMG_HSIZE_C 29 16 Horizontal size of image 8 8192 Without minus 1 LSB 2 0 must be 3 b000 for 64 bit interface Zero value and values greater than 8192 are not allowed 0 Reserved 15 14 Reserved read as zero do not mo...

Page 1551: ...essor Top Chrominance Picture Pointer Control Register VP_TOP_C_PTR R W Address 0xF910_0030 VP_CR_PTR Bit Description Initial State VP_TOP_C_PTR 31 0 Base address for chrominance of top field It should be integer multiples of 8 LSB 2 0 must be 3 b000 0 8 4 1 11 Video Processor Bottom Chrominance Picture Pointer Control Register VP_BOT_C_PTR R W Address 0xF910_0034 VP_BOT_Y_PTR Bit Description Init...

Page 1552: ...ENDIAN_MODE Bit Description Initial State Reserved 31 1 Reserved read as zero do not modify 0 VP_ENDIAN_MODE 0 0 Big Endian 1 Little Endian Refer to Figure 8 6 0 Big Endian mode Little Endian mode Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 63 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 63 0 Figure 8 6 Endian Mode ...

Page 1553: ...ction 0100 b is had to do 4 time left shift operation As a result register value is 4 2 4 64 0x40 0 8 4 1 14 Video Processor Vertical Offset of Source Image Control Register VP_SRC_V_POSITION R W Address 0xF910_0048 VP_SRC_V_POSITION Bit Description Initial State Reserved 31 10 Reserved read as zero do not modify 0 VP_SRC_V_POSITION 10 0 Vertical offset in the source image This value should be in ...

Page 1554: ...0054 VP_DST_H_POSITION Bit Description Initial State Reserved 31 11 Reserved read as zero do not modify 0 VP_DST_H_POSITION 10 0 Horizontal offset in the display 0 8 4 1 18 Video Processor Vertical Offset of Destination Image Control Register VP_DST_V_POSITION R W Address 0xF910_0058 VP_DST_V_POSITION Bit Description Initial State Reserved 31 10 Reserved read as zero do not modify 0 VP_DST_V_POSIT...

Page 1555: ...it Description Initial State Reserved 31 10 Reserved read as zero do not modify 0 VP_DST_HEIGHT 10 0 Height of the display 0 VP_DST_H_POSITION VP_DST_V_POSITION picture height picture width VP_SRC_HEIGHT VP_SRC_WIDTH VP_DST_HEIGHT VP_DST_WIDTH Arbitrary Scaling Positioning VP_SRC_H_POSITION VP_SRC_V_POSITION Figure 8 7 Video Scaling Positioning on TV Display ...

Page 1556: ...e is 1 2 2 16 0x8000 0 8 4 1 22 Video Processor Vertical Zoom Ratio VP_V_RATIO R W Address 0xF910_0068 VP_V_RATIO Bit Description Initial State Reserved 31 19 Reserved read as zero do not modify 0 VP_V_RATIO 18 0 Vertical zoom ratio of SRC DST 3 16 format This register should be as follows 1 BOB mode IPC disable VP_V_RATIO SRC DST 2 BOB mode IPC enable VP_V_RATIO 2 SRC DST This is because destinat...

Page 1557: ...served read as zero do not modify 0 vp_poly8_y0_ph4 26 24 Poly phase Filter Coefficients 0 Reserved 23 19 Reserved read as zero do not modify 0 vp_poly8_y0_ph5 18 16 Poly phase Filter Coefficients 0 Reserved 15 11 Reserved read as zero do not modify 0 vp_poly8_y0_ph6 10 8 Poly phase Filter Coefficients 0 Reserved 7 3 Reserved read as zero do not modify 0 vp_poly8_y0_ph7 2 0 Poly phase Filter Coeff...

Page 1558: ... Reserved read as zero do not modify 0 vp_poly8_y1_ph0 28 24 Poly phase Filter Coefficients 0 Reserved 23 21 Reserved read as zero do not modify 0 vp_poly8_y1_ph1 20 16 Poly phase Filter Coefficients 0 Reserved 15 13 Reserved read as zero do not modify 0 vp_poly8_y1_ph2 12 8 Poly phase Filter Coefficients 0 Reserved 7 5 Reserved read as zero do not modify 0 vp_poly8_y1_ph3 4 0 Poly phase Filter Co...

Page 1559: ...29 Reserved read as zero do not modify 0 vp_poly8_y1_ph12 28 24 Poly phase Filter Coefficients 0 Reserved 23 21 Reserved read as zero do not modify 0 vp_poly8_y1_ph13 20 16 Poly phase Filter Coefficients 0 Reserved 15 13 Reserved read as zero do not modify 0 vp_poly8_y1_ph14 12 8 Poly phase Filter Coefficients 0 Reserved 7 5 Reserved read as zero do not modify 0 vp_poly8_y1_ph15 4 0 Poly phase Fil...

Page 1560: ...served read as zero do not modify 0 vp_poly8_y2_ph8 30 24 Poly phase Filter Coefficients 0 Reserved 23 Reserved read as zero do not modify 0 vp_poly8_y2_ph9 22 16 Poly phase Filter Coefficients 0 Reserved 15 Reserved read as zero do not modify 0 vp_poly8_y2_ph10 14 8 Poly phase Filter Coefficients 0 Reserved 7 Reserved read as zero do not modify 0 vp_poly8_y2_ph11 6 0 Poly phase Filter Coefficient...

Page 1561: ...Reserved read as zero do not modify 0 vp_poly8_y3_ph4 30 24 Poly phase Filter Coefficients 0 Reserved 23 Reserved read as zero do not modify 0 vp_poly8_y3_ph5 22 16 Poly phase Filter Coefficients 0 Reserved 15 Reserved read as zero do not modify 0 vp_poly8_y3_ph6 14 8 Poly phase Filter Coefficients 0 Reserved 7 Reserved read as zero do not modify 0 vp_poly8_y3_ph7 6 0 Poly phase Filter Coefficient...

Page 1562: ...ved read as zero do not modify 0 vp_poly4_y0_ph0 29 24 Poly phase Filter Coefficients 0 Reserved 23 22 Reserved read as zero do not modify 0 vp_poly4_y0_ph1 21 16 Poly phase Filter Coefficients 0 Reserved 15 14 Reserved read as zero do not modify 0 vp_poly4_y0_ph2 13 8 Poly phase Filter Coefficients 0 Reserved 7 6 Reserved read as zero do not modify 0 vp_poly4_y0_ph3 5 0 Poly phase Filter Coeffici...

Page 1563: ...30 Reserved read as zero do not modify 0 vp_poly4_y0_ph12 29 24 Poly phase Filter Coefficients 0 Reserved 23 22 Reserved read as zero do not modify 0 vp_poly4_y0_ph13 21 16 Poly phase Filter Coefficients 0 Reserved 15 14 Reserved read as zero do not modify 0 vp_poly4_y0_ph14 13 8 Poly phase Filter Coefficients 0 Reserved 7 6 Reserved read as zero do not modify 0 vp_poly4_y0_ph15 5 0 Poly phase Fil...

Page 1564: ...served read as zero do not modify 0 vp_poly4_y1_ph8 30 24 Poly phase Filter Coefficients 0 Reserved 23 Reserved read as zero do not modify 0 vp_poly4_y1_ph9 22 16 Poly phase Filter Coefficients 0 Reserved 15 Reserved read as zero do not modify 0 vp_poly4_y1_ph10 14 8 Poly phase Filter Coefficients 0 Reserved 7 Reserved read as zero do not modify 0 vp_poly4_y1_ph11 6 0 Poly phase Filter Coefficient...

Page 1565: ...Reserved read as zero do not modify 0 vp_poly4_y2_ph4 30 24 Poly phase Filter Coefficients 0 Reserved 23 Reserved read as zero do not modify 0 vp_poly4_y2_ph5 22 16 Poly phase Filter Coefficients 0 Reserved 15 Reserved read as zero do not modify 0 vp_poly4_y2_ph6 14 8 Poly phase Filter Coefficients 0 Reserved 7 Reserved read as zero do not modify 0 vp_poly4_y2_ph7 6 0 Poly phase Filter Coefficient...

Page 1566: ...ved read as zero do not modify 0 vp_poly4_y3_ph0 29 24 Poly phase Filter Coefficients 0 Reserved 23 22 Reserved read as zero do not modify 0 vp_poly4_y3_ph1 21 16 Poly phase Filter Coefficients 0 Reserved 15 14 Reserved read as zero do not modify 0 vp_poly4_y3_ph2 13 8 Poly phase Filter Coefficients 0 Reserved 7 6 Reserved read as zero do not modify 0 vp_poly4_y3_ph3 5 0 Poly phase Filter Coeffici...

Page 1567: ...efficients 0 Reserved 7 6 Reserved read as zero do not modify 0 vp_poly4_y3_ph11 5 0 Poly phase Filter Coefficients 0 8 4 1 54 Video Processor Luminance 4 tap Poly phase Filter Coefficients VP_POLY4_Y3_HH R W Address 0xF910_0128 VP_POLY4_Y3_LL Bit Description Initial State Reserved 31 30 Reserved read as zero do not modify 0 vp_poly4_y3_ph12 29 24 Poly phase Filter Coefficients 0 Reserved 23 22 Re...

Page 1568: ...o do not modify 0 vp_poly4_c0_ph1 22 16 Signed 7 bit integer 64 63 0 Reserved 15 Reserved read as zero do not modify 0 vp_poly4_c0_ph2 14 8 Signed 7 bit integer 64 63 0 Reserved 7 Reserved read as zero do not modify 0 vp_poly4_c0_ph3 6 0 Signed 7 bit integer 64 63 0 8 4 1 56 Video Processor Chrominance 4 tap Poly phase Filter Coefficients VP_POLY4_C0_LH R W Address 0xF910_0130 VP_POLY4_C0_LH Bit D...

Page 1569: ...ficients VP_POLY4_C0_HH R W Address 0xF910_0138 VP_POLY4_C0_HH Bit Description Initial State Reserved 31 29 Reserved read as zero do not modify 0 vp_poly4_c0_ph12 28 24 Signed 5 bit integer 16 15 0 Reserved 23 21 Reserved read as zero do not modify 0 vp_poly4_c0_ph13 20 16 Signed 5 bit integer 16 15 0 Reserved 15 13 Reserved read as zero do not modify 0 vp_poly4_c0_ph14 12 8 Signed 5 bit integer 1...

Page 1570: ...ly4_c1_ph8 31 24 Unsigned 8 bit integer 0 255 0 vp_poly4_c1_ph9 23 16 Signed 8 bit integer 128 127 0 vp_poly4_c1_ph10 15 8 Signed 8 bit integer 128 127 0 vp_poly4_c1_ph11 7 0 Signed 8 bit integer 128 127 0 8 4 1 62 Video Processor Chrominance 4 tap Poly phase Filter Coefficients VP_POLY4_C1_HH R W Address 0xF910_0148 VP_POLY4_C1_HH Bit Description Initial State Reserved 31 Reserved read as zero do...

Page 1571: ...98 Cr709 Above all equations are written without interface offsets of 16 for Luminance and 128 for Chrominance CSC module calculates above all equations without 128 offset for Chrominance and generates final CSC results with 128 offset In case of two Luminance equations 16 offset is selectable by control register PP_CSC_EN 1 If Y offset 16 exists in matrix input data the coefficient of above equat...

Page 1572: ...ead as zero do not modify 0 PP_CSC_CR2Y_COEF 11 0 BT 601 to BT 709 or BT 709 to BT 601 CSC coefficient for CR to Y 0 8 4 1 66 Video Processor Post processing Color Space Conversion Coefficient Register PP_CSC_Y2CB_COEF R W Address 0xF910_01E0 PP_CSC_Y2CB_COEF Bit Description Initial State Reserved 31 12 Reserved read as zero do not modify 0 PP_CSC_Y2CB_COEF 11 0 BT 601 to BT 709 or BT 709 to BT 60...

Page 1573: ...ead as zero do not modify 0 PP_CSC_Y2CR_COEF 11 0 BT 601 to BT 709 or BT 709 to BT 601 CSC coefficient for Y to CR 0 8 4 1 70 Video Processor Post processing Color Space Conversion Coefficient Register PP_CSC_CB2CR_COEF R W Address 0xF910_01E8 PP_CSC_CB2CR_COEF Bit Description Initial State Reserved 31 12 Reserved read as zero do not modify 0 PP_CSC_CB2CR_COEF 11 0 BT 601 to BT 709 or BT 709 to BT...

Page 1574: ...for SDTV We don t recommend you to use functions for HDTV Post image processor executes color saturation control sharpness enhancement contrast and brightness control 0 Enables 1 Disables default 1 8 4 1 73 Video Processor Color Saturation Control Register PP_SATURATION R W Address 0xF910_020C PP_SATURATION Bit Description Initial State Reserved 31 8 Reserved read as zero do not modify 0 PP_SATURA...

Page 1575: ...cription Initial State Reserved 31 2 Reserved read as zero do not modify 0 PP_TH_HNOISE 15 8 Threshold value setting to decide minimum vertical edge value 0x5 Reserved 7 2 Reserved read as zero do not modify 0 PP_SHARPNESS 1 0 Control for the edge enhancement 0 No effect 1 Minimum edge enhancement 2 Moderate edge enhancement 3 Maximum edge enhancement 0 ...

Page 1576: ...INE_SLOPE 7 0 Slope unsigned 1 7 format Due to1 bit integer LINE_SLOPE has range from 0 to 1 9921875 Note 1 7 format means that 1 is a integer 7 is a fraction Example LINE_SLOPE 0 5 1 2 1 Because of 7 bit fraction it is had to do 7 time left shift operation As a result register value is 1 2 2 7 0x40 0 NOTE 8 equation is related with Figure 8 8 Input luminance value between 0 255 is divide by 8 ste...

Page 1577: ...FF 255 0x1 1 0x0 0 0x1FF 1 0x100 256 0 NOTE Figure 8 8 shows examples of how VP controls brightness and contrast of image sequence using PP_LINE_EQ0 PP_LINE_EQ7 registers and PP_BRIGHT_OFFSET register Input to output luminance mapping curve is approximated by 8 sub lines described by PP_LINE_EQ0 PP_LINE_EQ7 Consequently brightness and contrast is controlled in very flexible way INPUT Luminance 0 O...

Page 1578: ...ef Cr 128 Cr2Y_coef Cb Y 16 Y2Cb_coef Cb 128 Cb2Cb_coef Cr 128 Cr2Cb_coef Cr Y 16 Y2Cr_coef Cb 128 Cb2Cr_coef Cr 128 Cr2Cr_coef Else Y Y Y2Y_coef Cb 128 Cb2Y_coef Cr 128 Cr2Y_coef Cb Y Y2Cb_coef Cb 128 Cb2Cb_coef Cr 128 Cr2Cb_coef Cr Y Y2Cr_coef Cb 128 Cb2Cr_coef Cr 128 Cr2Cr_coef 1 CSC_EN 0 Color space conversion enable control 0 Disable 1 Enable 0 8 4 1 78 Video Processor Version Information Reg...

Page 1579: ...els to be interpolated are calculated with VP_SRC_V_POSITION and VP_V_RATIO Once the vertical position is calculated the nearest pixel phase with 1 16 resolution and which pixels are used for interpolation are decided V_RATIO Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 0 16 phase 8 16 phase 16 16 phase Nth Line N 1th Line N 2th Line N 3th Line N 4th Line 4 16 phase 12 16 phase Current Interpolated Pixel with Y0 Y1 Y2...

Page 1580: ... vp_poly4_y1_ph7 vp_poly4_y2_ph7 and vp_poly4_y3_ph7 8 tap luminance horizontal poly phase filter and 4 tap chrominance horizontal poly phase filter use the exact same scheme At the boundaries of pictures top bottom left and right some pixels in filter window are not available In this case value of the nearest pixel is repeated as shown in Figure 8 10 a b c d e 1st Line 2nd Line 3rd Line a 4th Lin...

Page 1581: ... real time transfer 9 1 1 KEY FEATURES OF MIXER Supports AXI Master AHB Slave Interface AXI Master interface for graphic layer data fetch AHB Slave interface for control register setup Supports Little Big Endian for graphic layers data Input Multiple Layers Background layer Graphic0 layer Graphic1 layer Video layer Input Control features Blending between each layers Selectable graphic layer frame ...

Page 1582: ...layer blending factor between each layer Scale Vertical line duplication x2 Horizontal win scale x2 Video Layer Source Video processor module Color Format 24bpp Direct YCbCr 888 Maximum Resolution 480i p 720x480 pixel 576i p 720x576 pixel 720p 1280x720 pixel 1080i p 1920x1080 pixel The xvYcc limiter is supported Background layer Source Configuration register Lowest layer Layer ordering Background ...

Page 1583: ...Fetcher This block fetches data from VP module Grp0 1 fetcher and Grp0 1 CSC Grp0 1 fetchers pop up data from Line Buffer0 1 and delivers image data to Blender block through the color space converters Grp0 1 CSC Background Generator This block generates background patterns according to configurations Blender The role of this block is to mix 4 image layers such as Video Graphic0 1 and Back ground T...

Page 1584: ...k VCLKHS and VCLKS TVENC clock is fixed by 54MHz Thus you must set MIXER_SEL register in CLK_SRC1 0xE010_0204 for more information refer to CMU chapter Else in HDMI out selection REG_DST_SEL register is configured properly Then you set the same clock configuration between MIXER I F clock VCLKHS and VCLKH HDMI pixel clock The clock which is generated by embedded PLL in HDMI PHY must be selected usi...

Page 1585: ...0 R W Specifies the Graphic Layer0 Configuration 0x0000_0000 MIXER_GRAPHIC0_BASE 0xF920_0024 R W Specifies the Base Address for Graphic Layer0 0x0000_0000 MIXER_GRAPHIC0_SPAN 0xF920_0028 R W Specifies the Span for Graphic Layer0 0x0000_0000 MIXER_GRAPHIC0_SXY 0xF920_002C R W Specifies the Source X Y Positions for Graphic Layer0 0x0000_0000 MIXER_GRAPHIC0_WH 0xF920_0030 R W Specifies the Width Heig...

Page 1586: ...or Space Conversion RGB to CB Coefficient for Graphic Layer 0x3b5d_b0e1 MIXER_CM_COEFF_CR 0xF920_0088 R W Specifies the Scaled Color Space Conversion RGB to Cr Coefficient for Graphic Layer 0x0e1d_13dc Mixer Global Setting Shadowing Register MIXER_STATUS_S 0xF920_2000 R Specifies the Status of MIXER Operation Shadow 0x0000_0006 MIXER_CFG_S 0xF920_2004 R Specifies the MIXER Mode Setting Shadow 0x00...

Page 1587: ...ow 0x0000_0000 MIXER_GRAPHIC1_SPAN_S 0xF920_2048 R Specifies the Graphic1 Span Shadow 0x0000_0000 MIXER_GRAPHIC1_SXY_S 0xF920_204C R Specifies the Graphic1 Source X Y Coordinates Shadow 0x0000_0000 MIXER_GRAPHIC1_WH_S 0xF920_2050 R Specifies the Graphic1 Width Height Shadow 0x0000_0000 MIXER_GRAPHIC1_DXY_S 0xF920_2054 R Specifies the Graphic1 Destination X Y Coordinates Shadow 0x0000_0000 MIXER_GR...

Page 1588: ...6Beat Burst Mode 0 8Beat Burst Mode 0 Reserved 6 4 Reserved 0 BIG_ENDIAN 3 0 Little Endian Source Format 1 Big Endian Source Format 0 SYNC_ENABLE 2 0 Values set by user will not be applied to the mixer operation although v_sync is detected 1 Values set by user can be applied to the mixer operation after v_sync detected 1 MIXER_OPERATION_STA TUS 1 This bit is read only 0 MIXER is operating 1 MIXER ...

Page 1589: ...0 1080p REG_SCAN_MODE is 1 0 REG_GRAPHIC1_EN 5 Graphic1 layer display control bit 0 Disable 1 Enable 0 REG_GRAPHIC0_EN 4 Graphic0 layer display control bit 0 Disable 1 Enable 0 REG_VIDEO_EN 3 Video layer display control bit 0 Disable 1 Enable 0 REG_SCAN_MODE 2 Display scanning mode of TV 0 Interlaced mode 1 Progressive mode 0 REG_NTSC_PAL 1 Display standard of TV If you set this bit 0 and set REG_...

Page 1590: ... enable Write only 0 Disable interrupt 1 Enable interrupt 0 INT_EN_VP 10 The VP underflow interrupt enable 0 Disables interrupt 1 Enables interrupt Setting this bit to 0 disables only the interrupt request to host controller It does not mask the change of the MIXER_INT_STATUS 10 bit status 0 INT_EN_GRP1 9 The graphic layer1 line buffer underflow interrupt enable 0 Disables interrupt 1 Enables inte...

Page 1591: ...line buffer 0 INT_STATUS_GRP1 9 The graphic layer1 line buffer underflow interrupt status 0 Interrupt is not fired 1 Interrupt is fired Writing 1 to this bit clears the interrupt This interrupt is automatically asserted by line buffer controller if underflow is generated in line buffer 0 INT_STATUS_GRP0 8 The graphic layer0 line buffer underflow interrupt status 0 Interrupt is not fired 1 Interrup...

Page 1592: ...mined by difference of priority s value For example case1 and case 2 have the same effect Case1 GRP1 priority is 2 GRP0 priority 3 Video Priority 1 Case2 GRP1 priority is 14 GRP0 priority 15 Video Priority 13 MIXER_LAYER_CFG Bit Description Initial State Reserved 31 12 Reserved read as zero do not modify 0 Graphic layer 1 priority 11 8 15 1 the priority value 0 Hides the graphic layer 1 0 Graphic ...

Page 1593: ...blend with lower layer α video_layer_pixel_value 1 α lower_layer_pixel_value If REG_ALPHA_VID is 0 α is 0 If REG_ALPHA_VID is not 0 α REG_ALPHA_VID 1 256 0 NOTE All changes to this register are valid on a vertical sync signal of next frame 9 2 2 7 MIXER_VIDEO_LIMITER_PARA_CFG Register MIXER_VIDEO_LIMITER_PARA_CFG R W Address 0xF920_0018 MIXER_VIDEO_LIMITER_ PARA_CFG Bit Description Initial State R...

Page 1594: ...iplied mode 0 Normal mode In this mode graphic pixel data must be pre multiplied with graphic pixel alpha In pre multiplied mode REG_PIXEL0_BLEND_EN must be enabled Graphic and lower layer blending factor This factor is used all over the pixels in the graphic and lower layer to blend with A blending factor α is as follows depending on the a layer blending factor and a pixel blending factor values ...

Page 1595: ...lend with A blending factor α is as follows depending on the a layer blending factor and a pixel blending factor values α graphic_layer_pixel_value 1 α lower_layer_pixel_value See Table 9 1 If REG_ALPHA_WIN0 is 0 blending_factor_layer is 0 If REG_ALPHA_WIN0 is not 0 blending_factor_layer REG_ALPHA_WIN 1 256 If A blending factor of each pixel is 0 blending_factor_each_pixel is 0 If A blending facto...

Page 1596: ...plied mode 0 Normal mode In this mode graphic pixel data must be pre multiplied with graphic pixel alpha In pre multiplied mode REG_PIXEL1_BLEND_EN must be enabled Graphic and lower layer blending factor This factor is used all over the pixels in the graphic and lower layer to blend with A blending factor α is as follows depending on the a layer blending factor and a pixel blending factor values S...

Page 1597: ...lend with A blending factor α is as follows depending on the a layer blending factor and a pixel blending factor values α graphic_layer_pixel_value 1 α lower_layer_pixel_value See Table 9 1 If REG_ALPHA_WIN1 is 0 blending_factor_layer is 0 If REG_ALPHA_WIN1 is not 0 blending_factor_layer REG_ALPHA_WIN 1 256 If A blending factor of each pixel is 0 blending_factor_each_pixel is 0 If A blending facto...

Page 1598: ...pre multiplied mode the input graphic data is multiplied by the pixel blending factor alpha_gp and truncated to the size of source format bits For example although the result of the multiplication of 8 bit data by 8 bit pixel blending factor is 16 bits which is the first term of the blending equation in the Table 9 2 Normal mode the supplied data is truncated to 8 bits that results the loss of the...

Page 1599: ...icant bits 1 0 will be set 2 b00 automatically 0 9 2 2 11 MIXER_GRAPHIC0_SPAN R W Address 0xF920_0028 MIXER_GRAPHIC1_SPAN R W Address 0xF920_0048 MIXER_GRAPHICn_SPAN Bit Description Initial State Reserved 31 15 Reserved read as zero do not modify 0 REG_GRAPHICn_SPAN 14 0 Horizontal pixel interval between line and line in graphic layer s source image Note SPAN is the number of the original image s ...

Page 1600: ... Available 1 X2 Duplication 0 Reserved 11 Reserved read as zero do not modify 0 REG_GRAPHICn_H 10 0 Height of graphic layer pixel unit 0 NOTE All the changes of this register are valid on a vertical sync signal of next frame When specifying the X coordinates and the width of a graphic layer it should be located inside the display region for example 720x480 region in NTSC display mode and 720x576 r...

Page 1601: ...l unit Allowed range 0 479 at NTSC mode 0 575 at PAL mode 0 719 at HD mode 720p 0 1079 at HD mode 1080i p 0 9 2 2 14 MIXER_GRAPHIC0_DXY R W Address 0xF920_0034 MIXER_GRAPHIC1_DXY R W Address 0xF920_0054 MIXER_GRAPHICn_DXY Bit Description Initial State Reserved 31 27 Reserved read as zero do not modify 0 REG_GRAPHICn_DX 26 16 X coordinate of upper left corner of graphic layer in destination frame p...

Page 1602: ...register value must be same with pixel value including alpha value 0 9 2 2 16 MIXER_BG_COLOR0 R W Address 0xF920_0064 MIXER_BG_COLOR1 R W Address 0xF920_0068 MIXER_BG_COLOR2 R W Address 0xF920_006C MIXER_BG_COLOR0 1 2 Bit Description Initial State 31 24 Reserved read as zero do not modify 0 Y 23 16 Y component of background color 0 Cb 15 8 Cb component of background color 0 Cr 7 0 Cr component of ...

Page 1603: ...h 16 235 range Y601 0 299R 0 587G 0 114B Y709 0 213R 0 715G 0 072B Cb 0 172R 0 339G 0 511B 128 Cb 0 117R 0 394G 0 511B 128 Cr 0 511R 0 428G 0 083B 128 Cr 0 511R 0 464G 0 047B 128 RGB data with 0 255 range Y601 0 257R 0 504G 0 098B 16 Y709 0 183R 0 614G 0 062B 16 Cb 0 148R 0 291G 0 439B 128 Cb 0 101R 0 338G 0 439B 128 Cr 0 439R 0 368G 0 071B 128 Cr 0 439 0 399G 0 040B 128 Fraction Number Exaple 1bi...

Page 1604: ... decimal 0x36b REG_COEFF_21 9 0 Scaled color space conversion coefficient C21 9 Sign bit 8 0 Fractional bit Default and Recommended value 0 439 in decimal 0xe1 9 2 2 19 MIXER_COLOR_SPACE_CONVERSION_COEF_CR Register MIXER_CM_COEFF_Cr R W Address 0xF920_0088 MIXER_CM_COEFF_CR Bit Description Initial State Reserved 31 30 Reserved read as zero do not modify 0 REG_COEFF_02 29 20 Scaled color space conv...

Page 1605: ...or as it is the lowest layer Video layer Video layer has one blending factor that is applied to all the pixels in the video layer MIXER_VIDEO_CFG 7 0 REG_ALPHA_VID is the blending factor The video blending is enabled or disabled Graphic0 layer Graphic0 layer supports pixel blending and window blending Pixel blending factors are applied pixel by pixel although window blending factor is applied all ...

Page 1606: ...S5PC110_UM 9 8BMIXER 9 26 Video layer Graphic layer0 Background layer blend blend blend Graphic laer1 Figure 9 4 Mixer Blending ...

Page 1607: ...ength like the following 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 alpha factor R G B Figure 9 5 16bpp ARGB Example The internal data path is processed with YCbCr 888 format therefore RGB format is converted to YCbCr by color matrix conversion If the bit per pixel BPP of color format is smaller than 8 bits that value is used after expanding Refer Figure 9 6 example ARGB 1555 4 3 2 1 0 4 3 2 MSB paddin...

Page 1608: ... endian format This different endian format is applicable to the graphic data Mixer supports many graphic formats The register format of the supported source formats is shown in Figure 9 7 The following picture shows the pixels in a display that is seen through human eyes A1 R1 ARGB8888 ARGB 4444 RGB 1555 RGB 565 G1 A3 R3 G3 B3 A 63 0 31 47 R3 G3 B3 R3 G3 B3 Little Endian Big Endian B1 A2 R2 G2 B2...

Page 1609: ...e Mixer the word format to represent these pixels is different depending on the endian format In the big endian mode the pixel with lower X coordinate is positioned to the MSB parts in the 64 bit register of Mixer However in the little endian mode the pixel with lower X coordinate is positioned to the LSB parts in the 64 bit register 9 3 5 BACKGROUND LAYER If there is no video or graphic backgroun...

Page 1610: ...omplies with HDMI 1 3 HDCP 1 1 and DVI 1 0 Supports the following video formats 480p 59 94Hz 60Hz 576p 50Hz 720p 50Hz 59 94Hz 60Hz 1080i 50Hz 59 94Hz 60Hz 1080p 25Hz 29 97Hz 30Hz Other various formats up to 74 25 MHz Pixel Clock Supports Color Format 4 4 4 RGB YCbCr Supports Bit Per Color 8 bit Supports CEC function Contains an Integrated HDCP Encryption Engine for Video Audio content protection D...

Page 1611: ...the output resolution You can configure both CMU and HDMI_PHY SPDIF in peripheral bus and I2S 5 1 channel in Audio sub system feed audio data in HDMI TX V1 3 For more information refer to SPDIF and I2S datasheets HDMI TX V1 3 in S5PC110 supports embedded HDCP key system S5PC110 does not allow access to HDCP key A dedicated I2C is used to configure HDMI PHY In addition the HDMI PHY generates pixel ...

Page 1612: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 3 10 1 3 BLOCK DIAGRAM OF HDMI SUB SYSTEM IN S5PC110 Figure 10 2 Block Diagram of HDMI SUB System in S5PC110 ...

Page 1613: ...Diagram of HDCP Key Management S5PC110 supports embedded HDCP key system The HDCP key value is fused during fabrication based on customers request S5PC110 strictly prohibits access to HDCP key value from any method After S5PC110 boot up the HDCP key is loaded using SFR from E FUSE memory HDCP_E_FUSE_CTRL 0xFA16_000 0 bit ...

Page 1614: ...alue TG_VSYNC2_H 0xFA15_0044 Reset value Reset value Reset value 0x02 Reset value TG_VACT_ST_L 0xFA15_0048 0x2d 0x31 0x1e 0x16 0x2d TG_VACT_ST_H 0xFA15_004C 0x00 0x00 0x00 0x00 0x00 TG_VACT_SZ_L 0xFA15_0050 0xe0 0xe0 0xd0 0x1c 0x38 TG_VACT_SZ_H 0xFA15_0054 0x01 0x01 0x02 0x02 0x04 TG_FIELD_CHG_L 0xFA15_0058 Reset value Reset value Reset value 0x33 Reset value TG_FIELD_CHG_H 0xFA15_005C Reset value...

Page 1615: ...NTERFACE 10 6 720x480p 720x576p 1280x720p 1920x1080i 1920x1080p 0xFA15_008C TG_FIELD_BOT_HDMI_L 0xFA15_0090 Reset value Reset value Reset value 0x33 Reset value TG_FIELD_BOT_HDMI_H 0xFA15_0094 Reset value Reset value Reset value 0x02 Reset value ...

Page 1616: ...set CORE_RSTOUT 0 _bit 0xFA10_0020 is set to 0 for 100us 4 PHY ready check 5 Clock path change CLK_SRC1 0 _bit 0xE010_0204 is set to 1 SCLK_HDMIPHY Upper sequence is prior to configuration of VP MIXER and HDMI LINK Due to the security policy below table s configuration is only opened as shown in Table 10 2 Table 10 2 HDMI PHY Configuration Table for 27MHz OSC_In 27MHz Pixel Clock Ratio 27 027MHz 7...

Page 1617: ... 00h 20h 0x13 38h 38h 38h 38h 0x14 00h 00h 00h 00h 0x15 08h 08h 08h 08h 0x16 10h 10h 10h 10h 0x17 E0h E0h E0h E0h 0x18 22h 22h 22h 22h 0x19 40h 40h 40h 40h 0x1A FFh FFh B9h B9h 0x1B 26h 26h 26h 26h 0x1C 00h 00h 01h 01h 0x1D 00h 00h 00h 00h 0x1E 00h 00h 00h 00h 0x1F 80h 80h 80h 80h Address 0x1f specifies the PHY_START control If PHY is configured the address 0x1f must be 0x0 NOTE It can be various ...

Page 1618: ... 52h 52h 52h 52h 0x0C DFh DFh EFh FFh 0x0D F2h F2h F3h F1h 0x0E 54h 54h 54h 54h 0x0F 87h 87h B9h BAh 0x10 84h 84h 84h 84h 0x11 00h 00h 00h 00h 0x12 30h 30h 30h 10h 0x13 38h 38h 38h 38h 0x14 00h 00h 00h 00h 0x15 08h 08h 08h 08h 0x16 10h 10h 10h 10h 0x17 E0h E0h E0h E0h 0x18 22h 22h 22h 22h 0x19 40h 40h 40h 40h 0x1A E3h E2h A5h A4h 0x1B 26h 26h 26h 26h 0x1C 00h 00h 01h 01h 0x1D 00h 00h 00h 00h 0x1E ...

Page 1619: ...mode Power Down REG01 bit 5 Bias power down REG01 bit 7 Sigma delta modulator clock generator power down REG05 bit 5 PLL power down REG17 bit 0 PCG power down REG17 bit 1 TX power down 4 b1111 Maximum amplitude 4 b0000 Minimum amplitude TMDS Data Amplitude Control Reg 18 bit 3 0 TMDS data amplitude control 4 b1111 Maximum amplitude 4 b0000 Minimum amplitude TMDS Clock Amplitude Control Reg 18 bit ...

Page 1620: ...miTX2N Output TMDS output data pairs XhdmiTXCP Output XhdmiTXCN Output TMDS output clock pair XhdmiREXT Input External Reference Resistor External reference resistor input A 4 6K 1 resistor is connected to ground XhdmiXTI Input Reference Clock Input Crystal oscillator input It is used to generate internal clock signals It s nominal frequency is 27MHz XhdmiXTO Output Reference Clock Output Crystal ...

Page 1621: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 12 10 1 9 BLOCK DIAGRAM OF CLOCK STRATEGY FOR HDMI TX Figure 10 5 Block Diagram of HDMI TX Clock Scheme in S5PC110 ...

Page 1622: ...el and TMDS clock Pixel and TMDS clocks are from HDMI PHY You must configure it before use VCLKHS MIXER pixel clock and VCLKH HDMI pixel clock are synchronous Thus the same clock is fed through VCLKHS and VCLKH For pixel frequency refer to Figure 10 6 Figure 10 6 Frequency Summary in Use ...

Page 1623: ...reamble is changed to preamble B once every 192 frames This unit is composed of 192 frames It defines the block structure used to organize the channel status information On the other hand sub frames of channel 2 right or B in stereophonic operation and secondary channel in monophonic operation always use preamble W In single channel operation mode and broadcasting studio environment the frame form...

Page 1624: ...ed auxiliary sample bits If the source provides fewer bits than what the interface allows 24 or 20 the unused LSBs are set to a logical 0 By this procedure the equipment using different numbers of bits can be connected together Time slot 28 carries the validity flag associated with audio sample word This flag is set to logical 0 if the audio sample is reliable Time slot 29 carries one bit of user ...

Page 1625: ... Channel Status bit in each sub frame as shown in Figure 10 9 As one frame consists of 192 frames one channel status block can be obtained for one channel This block holds the information of the stream being transmitted such as application stream type sampling frequency word length and so on Figure 10 9 Channel Status Block Extract from SPDIF Stream ...

Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...

Page 1627: ...he first if the bit to be transmitted is logical 0 and different from the first if the bit is logical 1 Clock twice bit rate Source coding Channel coding bi phase mark Figure 10 11 Channel coding 10 2 1 4 Preamble Preambles are specific patterns providing synchronization and identification of the sub frames and blocks A set of three preambles is used These preambles are transmitted in the time all...

Page 1628: ...ng rate of the encoded audio within that bitstream Each data burst contains a burst preamble consisting of four 16 bit words Pa Pb Pc and Pd followed by the burst payload that contains data of an encoded audio frame The burst preamble consists of four mandatory fields Pa and Pb represent a synchronization word Pc gives information about the type of data and some information control for the receive...

Page 1629: ...SE 0xFA10_0000 Specifies the controller register base address HDMI_CORE_BASE 0xFA11_0000 Specifies the HDMI register base address SPDIF_BASE 0xFA13_0000 Specifies the SPDIF receiver register base address I2S_BASE 0xFA14_0000 Specifies the I2S receiver register base address TG_BASE 0xFA15_0000 Specifies the HDMI timing generator register base address eFUSE_BASE 0xFA16_0000 Specifies the e fuse rela...

Page 1630: ...cifies the HDMI system status register 0x00 PHY_STATUS 0xFA11_0014 R Specifies the PHY status register 0x00 STATUS_EN 0xFA11_0020 R W Specifies the HDMI system status enable register 0x00 HPD 0xFA11_0030 R W Specifies the HPD control register 0x00 MODE_SEL 0xFA11_0040 R W Selects the HDMI DVI mode 0x00 ENC_EN 0xFA11_0044 R W Specifies the HDCP encryption enable register 0x00 HDMI Core Registers Vi...

Page 1631: ...C_GEN_1 0xFA11_0124 R W Specifies the horizontal sync generation setting 0x00 H_SYNC_GEN_2 0xFA11_0128 R W Specifies the horizontal sync generation setting 0x00 V_SYNC_GEN1_0 0xFA11_0130 R W Specifies the vertical sync generation for top field or frame 0x01 V_SYNC_GEN1_1 0xFA11_0134 R W Specifies the vertical sync generation for top field or frame 0x10 V_SYNC_GEN1_2 0xFA11_0138 R W Specifies the v...

Page 1632: ...0194 R W Specifies the CTS value for fixed CTS transmission mode 0x03 ACR_CTS2 0xFA11_0198 R W Specifies the CTS value for fixed CTS transmission mode 0x00 ACR_N0 0xFA11_01A0 R W Specifies the N value for ACR packet 0xe8 ACR_N1 0xFA11_01A4 R W Specifies the N value for ACR packet 0x03 ACR_N2 0xFA11_01A8 R W Specifies the N value for ACR packet 0x00 ACR_LSB2 0xFA11_01B0 R W Specifies the alternate ...

Page 1633: ...CHECK_SUM 0xFA11_0370 R W Specifies the AUI packet checksum 0x00 AUI_BYTE1 5 0xFA11_0380 0xFA11_0390 R W Specifies the AUI packet body 0x00 MPG_CON 0xFA11_03A0 R W Specifies the ACR packet control register 0x00 MPG_CHECK_SUM 0xFA11_03B0 R W Specifies the MPG packet checksum 0x00 MPG_BYTE1 5 0xFA11_03C0 0xFA11_03D0 R W Specifies the MPG packet body 0x00 SPD_CON 0xFA11_0400 R W Specifies the SPD pac...

Page 1634: ...Ri_1 0xFA11_0744 R W Specifies the Ri value of Tx 0x00 HDCP_I2C_INT 0xFA11_0780 R W Specifies the I2C interrupt flag 0x00 HDCP_AN_INT 0xFA11_0790 R W Specifies the An value ready interrupt flag 0x00 HDCP_WATCGDOG _ INT 0xFA11_07A0 R W Specifies the Watchdog interrupt flag 0x00 HDCP_Ri_INT 0xFA11_07B0 R W Specifies the Ri value update interrupt flag 0x00 HDCP_Ri_Compare_ 0 0xFA11_07D0 R W Specifies...

Page 1635: ...ved 0xFA13_001C Reserved SPDIFIN_USER_ VALUE_1 0xFA13_0020 R W Specifies the SPDIFIN user value register 1 0x00 SPDIFIN_USER_ VALUE_2 0xFA13_0024 R W Specifies the SPDIFIN user value register 2 0x00 SPDIFIN_USER_ VALUE_3 0xFA13_0028 R W Specifies the SPDIFIN user value register 3 0x00 SPDIFIN_USER_ VALUE_4 0xFA13_002C R W Specifies the SPDIFIN user value register 4 0x00 SPDIFIN_CH_STAT US_0_1 0xFA...

Page 1636: ... Specifies the SPDIFIN data buffer register 1_2 0x00 SPDIFIN_DATA_BU F_1_3 0xFA13_0078 R Specifies the SPDIFIN data buffer register 1_3 0x00 SPDIFIN_USER_BU F_1 0xFA13_007C R Specifies the SPDIFIN user buffer register 1 0x00 I2S Registers I2S_CLK_CON 0xFA14_0000 R W Specifies the I2S clock enable register 0x00 I2S_CON_1 0xFA14_0004 R W Specifies the I2S control register 1 0x00 I2S_CON_2 0xFA14_000...

Page 1637: ...ister 0x00 I2S_IRQ_STATUS 0xFA14_0060 R W Specifies the I2S interrupt request status register 0x00 I2S_CH0_L_0 0xFA14_0064 R Specifies the I2S PCM output data register 0x00 I2S_CH0_L_1 0xFA14_0068 R Specifies the I2S PCM output data register 0x00 I2S_CH0_L_2 0xFA14_006C R Specifies the I2S PCM output data register 0x00 I2S_CH0_L_3 0xFA14_0070 R Specifies the I2S PCM output data register 0x00 I2S_C...

Page 1638: ... Registers TG Configure Status Registers TG_CMD 0xFA15_0000 R W Specifies the command register 0x00 TG_H_FSZ_L 0xFA15_0018 R W Specifies the horizontal full size 0x72 TG_H_FSZ_H 0xFA15_001C R W Specifies the horizontal full size 0x06 TG_HACT_ST_L 0xFA15_0020 R W Specifies the horizontal active start 0x05 TG_ HACT_ST_H 0xFA15_0024 R W Specifies the horizontal active start 0x01 TG_ HACT_SZ_L 0xFA15_...

Page 1639: ...0 TG_VSYNC_BOT_H DMI_L 0xFA15_0080 R W Specifies the HDMI VSYNC position for bottom field 0x01 TG_VSYNC_BOT_H DMI_H 0xFA15_0084 R W Specifies the HDMI VSYNC position for bottom field 0x00 TG_FIELD_TOP_HD MI_L 0xFA15_0088 R W Specifies the HDMI top field start position 0x01 TG_FIELD_TOP_HD MI_H 0xFA15_008C R W Specifies the HDMI top field start position 0x00 TG_FIELD_BOT_HD MI_L 0xFA15_0090 R W Spe...

Page 1640: ...Global 6 0 Disables all interrupts 1 Enables or disables interrupts by INTC_CON5 0 0 IntrEnI2S 5 Enables I2S interrupt 0 Disables 1 Enables 0 IntrEnCEC 4 Enables CEC interrupt 0 Disables 1 Enables 0 IntrEnHPDplug 3 Enables HPD plugged interrupt 0 Disables 1 Enables 0 IntrEnHPDunplug 2 Enables HPD unplugged interrupt 0 Disables 1 Enables 0 IntrEnSPDIF 1 Enables SPDIF interrupt 0 Disables 1 Enables ...

Page 1641: ...plugged interrupt flag If it is written by 1 it is cleared 0 Interrupt does not occur 1 HPD unplugged interrupt occurs 0 IntrSPDIF 1 Specifies the SPDIF interrupt flag read only 0 Interrupt does not occur 1 Interrupt occurs 0 IntrHDCP 0 Specifies the HDCP interrupt flag read only 0 Interrupt does not occur 1 Interrupt occurs 0 10 3 2 3 Control Register HDCP_KEY_LOAD_DONE R Address 0xFA10_0008 HDCP...

Page 1642: ...less than 512fs Hz audio data may be missed Thus if the frequency of PCLK is below 512fs Hz select SPDIF clock after it makes the frequency of SPDIF clock be higher than 512fs Hz 0 10 3 2 6 Control Register HDMI_PHY_RSTOUT R W Address 0xFA10_0014 PHY_RSTOUT Bit Description Initial State 7 1 Reserved 0x00 RSTOUT 0 Specifies the HDMI PHY Software Reset out active high 0 Normal 1 Reset 0 10 3 2 7 Con...

Page 1643: ... Initial State CMU_LOCK 7 Specifies the HDMI PHY CMU Locking 0x0 6 4 Reserved 0x0 CMU_CODE 3 0 Specifies the HDMI PHY CMU Code 0x0 10 3 2 9 Control Register HDMI_CORE_RSTOUT R W Address 0xFA10_0020 CORE_RSTOUT Bit Description Initial State 7 1 Reserved 0x00 RSTOUT 0 Specifies the HDMI TX core software reset out active low 1 Normal 0 Reset 0x1 ...

Page 1644: ...ideo pixels are discarded and blue screen register values are transmitted for all video data period 0 Disables 1 Enables 0 Encoding_Option 4 Specifies the 10 bit TMDS encoding bit order option 0 Reverses the bit order during 10 bit encoding to be set to 1 when connecting to TMDS PHY 1 3 1 Retains the bit order as is 0 3 Reserved 0 Asp_E 2 Generates audio sample packet This bit is only valid when S...

Page 1645: ...O_G is limited based on YMAX and YMIN register values The values of I_VIDEO_B and I_VIDEO_R are limited based on CMAX and CMIN register values 2b11 Reserved 3b00 4 2 Reserved 3b000 1 0 Reserved 0 10 3 3 3 Control Registers HDMI_CON_2 R W Address 0xFA11_0008 HDMI_CON_2 Bit Description Initial State 7 6 Reserved 3b00 Vid_Period_En 5 Controls the video preamble 0 Video preamble is applied HDMI mode 1...

Page 1646: ...e host 0 Not full 1 Full 0 5 Reserved 0 Update_Ri_Int 4 Specifies the Ri interrupt status bit If it is written by 1 it is cleared 0 Interrupt does not occur 1 Interrupt occurs 0 3 Reserved 0 An_Write_Int 2 Indicates that An random value is ready If it is written by 1 it is cleared 0 Interrupt does not occur 1 Interrupt occurs 0 Watchdog_Int 1 Indicates that the 2nd part of HDCP authentication prot...

Page 1647: ...ddress 0xFA11_0020 STATUS_EN Bit Description Initial State 7 Reserved 0 Aud_Fido_Ovf_Ee 6 Enables audio buffer overflow interrupt If it is set to 1 interrupt assertion is written on status registers 0 Disables 1 Enables 0 5 Reserved 0 Update_Ri_Int_En 4 Enables UPDATE_RI_INT interrupt 0 Disables 1 Enables 0 3 Reserved 0 An_Write_Int_En 2 Enables AN_WRITE_INT interrupt 0 Disables 1 Enables 0 Watchd...

Page 1648: ...PD 0 HPD signal 1 SW_HPD internal HPD signal 0 NOTE If ENC_EN 0xFA11_0044 is disabled not using HDCP HPD must be controlled by S W If you don t use S W control it is possible that HDMI core works abnormally 10 3 3 8 Control Registers MODE_SEL R W Address 0xFA11_0040 MODE_SEL Bit Description Initial State 7 2 Reserved 6b000000 Hdmi_Mode 1 Selects a mode 0 Disables 1 Enables 0 Dvi_Mode 0 Selects a m...

Page 1649: ... 0xFA11_0050 BLUE_SCREEN_1 R W Address 0xFA11_0054 BLUE_SCREEN_2 R W Address 0xFA11_0058 BLUESCREEN_0 1 2 Bit Description Initial State BLUESCREEN_0 7 0 Specifies the Channel 0 color setting Cb or B 0x0 BLUESCREEN_1 7 0 Specifies the Channel 1 color setting Y or G 0x0 BLUESCREEN_2 7 0 Specifies the Channel 2 color setting Cr or R 0x0 ...

Page 1650: ... 7 0 7 0 7 0 These registers are used based upon the PX_LMT_CTRL bits in HDMI_CON_1 register For RGB mode if i_video_x HDMI_YMAX x 16 output HDMI_YMAX x 16 else if i_video_x HDMI_YMIN x 16 output HDMI_YMIN x 16 else output i_video_x For YCbCr mode the Y input is dealt in a similar way as shown above For Cb and Cr values if i_video_x HDMI_CMAX x 16 output HDMI_CMAX x 16 else if i_video_x HDMI_CMIN ...

Page 1651: ...it Description Initial State 15 10 Reserved 6b000000 H_BLANK 9 0 Specifies the clock cycles of horizontal blanking size For more details on H_BLANK refer to Reference CEA 861D 0x000 60Hz 720x480p 1280x720p 1920x1080i 1920x1080p H_BLANK 138 8Ah 370 172h 280 118h 280 118h 50Hz 720x576p 1280x720p 1920x1080i 1920x1080p H_BLANK 144 90h 700 2bch 720 2d0h 720 2d0h NOTE 1080p is 25 29 97 30Hz ...

Page 1652: ...efer to Reference CEA 861D 0x000 V2_BLANK 10 0 Specifies V1_BLANK Active Lines end part This value is the same as V_LINE value for progressive mode For interlace mode use the reference value as mentioned in the table below For more details on V2_BLANK refer to CEA 861D 0x000 60Hz 720x480p 1280x720p 1920x1080i 1920x1080p V2_BLANK V1_BLANK V_BLANK 525 d 45 d 16a0d h 750 d 30 d f2ee h 562 d 22 d b232...

Page 1653: ...20p 1920x1080i 1920x1080p V_LINE H_LINE H_V_LINE 525 d 858 d 35a20d h 750 d 1650 d 6722ee h 1125 d 2200 d 898465 h 1125 d 2200 d 898465 h 50Hz 720x576p 1280x720p 1920x1080i 1920x1080p V_LINE H_LINE H_V_LINE 625 d 864 d 360271 h 750 d 1980 d 7bc2ee h 1125 d 2640 d a50465 h 1125 d 2640 d a50465 h 10 3 3 15 Video Related Register VSYNC_POL R W Address 0xFA11_00E4 VSYNC_POL Bit Description Initial Sta...

Page 1654: ...Bit Description Initial State 23 22 Reserved 0x0 V_BOT_END 21 11 In the interlace mode v_blank length of even and odd field is different This register specifies the end position of bottom field s active region For more details on V_BOT_END refer to Reference CEA 861D 0x000 V_BOT_ST 10 0 Specifies the start position of bottom field s active region This value is the same as V_LINE value for interlac...

Page 1655: ...details on Hsync_Pol refer to Reference CEA 861D 0 Active high 1 Active low 0 Hsync_Edn 19 10 Sets the end point of H sync For more details on Hsync_Edn refer to Reference CEA 861D 0x000 Hsync_Start 9 0 Sets the start point of H sync For more details on Hsync_Start refer to Reference CEA 861D 0x000 60Hz 720x480p 1280x720p 1920x1080i 1920x1080p HSYNC_START HSYNC_END HSYNC_POL H_SYNC_GEN 14 d 76 d 1...

Page 1656: ...0 60 Hz 720x480p 720x576p 1280x720p 1920x1080i 1920x1080p VSYNC_T_END VSYNC_T_ST V_SYNC_GEN1 15 d 9 d 900f h 10 d 5 d 500a h 10 d 5 d 500a h 7 d 2 d 2007 h 9 d 4 d 4009 h 10 3 3 20 Video Related Register V_SYNC_GEN2_0 1 2 Progressive mode only has one v_sync whereas interlace mode has two This register is used for generating second v_sync of interlace case V_SYNC_GEN2_0 R W Address 0xFA11_0140 V_S...

Page 1657: ...0158 V_SYNC_GEN3_0 1 2 Bit Description Initial State Vsync_H_Pos_St 23 12 Specifies the bottom field V sync start transition point For more details on Vsync_H_Pos_St refer to Reference CEA 861D 0x001 Vsync_H_Pos_End 11 0 Specifies the bottom field V sync end transition point For more details on Vsync_H_Pos_End refer to Reference CEA 861D 0x001 60 Hz 1920x1080i Other cases VSYNC_H_POS_ST VSYNC_H_PO...

Page 1658: ...er 0 Two channel mode 1 Multi channel mode Set this bit to transmit HBR packets 0 SP_Pre 3 0 Controls sub packet usage for multi channel mode only When using two channel mode this register value is not used 0 AUDIO0 control 0 disable 1 enable 1 AUDIO1 control 0 disable 1 enable 2 AUDIO2 control 0 disable 1 enable 3 AUDIO3 control 0 disable 1 enable 4b0000 10 3 3 23 Audio Related Packet Register AS...

Page 1659: ...4 Selects the audio channel for subpacket 3 left channel data in multi channel mode The meaning is the same as SPK3R_SEL 3b110 23 22 Reserved 2b00 Spk2R_Sel 21 19 Selects the audio channel for subpacket 2 right channel data in multi channel mode The meaning is the same as SPK2R_SEL 3b101 Spk2L_Sel 18 16 Selects the audio channel selection for subpacket 2 left channel data in multi channel mode The...

Page 1660: ...lue 1 01 1 1 CTS value 1 CTS value2 10 2 1 CTS value 1 CTS value2 11 3 1 CTS value 1 CTS value2 Measured CTS mode this value is not used 2b00 ACR_Tx_Mode 2 0 000 Does not transfer Tx the ACR packet 001 Tx once Transmits ACR packet once anytime available after this value is set After transmitting these bits are reset to all zero 010 Tx ACR_TXCNT times during every VBI period 011 Tx by counting i_cl...

Page 1661: ...et on ACR_CON register 0x00001 10 3 3 27 Audio Related Packet Register ACR_CTS0 1 2 ACR_CTS0 R W Address 0xFA11_0190 ACR_CTS1 R W Address 0xFA11_0194 ACR_CTS2 R W Address 0xFA11_0198 ACR_CTS0 1 2 Bit Description Initial State 23 20 Reserved 0x0 ACR_CTS 19 0 Specifies the CTS value for transmission mode other than measured CTS mode 0x0003E8 10 3 3 28 Audio Related Packet Register ACR_N0 1 2 ACR_N0 ...

Page 1662: ...R_TX_MODE is 10 0x1F 10 3 3 31 Audio Related Packet Register ACR_TXINTERVAL R W Address 0xFA11_01B8 ACR_TXINTERVAL Bit Description Initial State ACR_TX_INTERVAL 7 0 If ACR_TX_MODE is 10 the ACR packet will be transmitted ACR_TXCNT times during VBI This register specifies the number of cycles between each ACR packets and avoids continuous transmission in more than 18 packets within single DI band I...

Page 1663: ...1 Transfers GCP packet 1b1 GCP_CON 1 0 00 Does not transmit 01 Transmits once 1x Transmits every vsync Transmits GCP packet within 384 cycles after active vsync 2b00 10 3 3 34 Audio Related Packet Register GCP_BYTE1 R W Address 0xFA11_01D0 GCP_BYTE1 Bit Description Initial State GCP_BYTE1 7 0 Specifies the GCP packet s first data byte It is either 0x10 Clear AVMUTE or 0x01 Set AVMUTE For more info...

Page 1664: ...ster ACP_DATA00 16 ACP_DATA00 R W Address 0xFA11_0200 ACP_DATA01 R W Address 0xFA11_0204 ACP_DATA02 R W Address 0xFA11_0208 ACP_DATA03 R W Address 0xFA11_020C ACP_DATA04 R W Address 0xFA11_0210 ACP_DATA05 R W Address 0xFA11_0214 ACP_DATA06 R W Address 0xFA11_0218 ACP_DATA07 R W Address 0xFA11_021C ACP_DATA08 R W Address 0xFA11_0220 ACP_DATA09 R W Address 0xFA11_0224 ACP_DATA10 R W Address 0xFA11_0...

Page 1665: ... Table 5 20 in HDMI v1 3 specification 3b000 10 3 3 42 ISRC1 2 Packet Register ISRC1_DATA 00 15 ISRC1_DATA 00 R W Address 0xFA11_0270 ISRC1_DATA 01 R W Address 0xFA11_0274 ISRC1_DATA 02 R W Address 0xFA11_0278 ISRC1_DATA 03 R W Address 0xFA11_027C ISRC1_DATA 04 R W Address 0xFA11_0280 ISRC1_DATA 05 R W Address 0xFA11_0284 ISRC1_DATA 06 R W Address 0xFA11_0288 ISRC1_DATA 07 R W Address 0xFA11_028C ...

Page 1666: ...ISRC2_DATA 12 R W Address 0xFA11_02E0 ISRC2_DATA 13 R W Address 0xFA11_02E4 ISRC2_DATA 14 R W Address 0xFA11_02E8 ISRC2_DATA 15 R W Address 0xFA11_02EC ISRC2_DATA 00 15 Bit Description Initial State ISRC2_DATA00 15 7 0 Specifies the ISRC2 packet body data PB0 15 of ISRC2 packet body For more information see Table 5 23 in HDMI v1 3 specification 0x00 10 3 3 44 AVI InfoFrame Register AVI_CON R W Add...

Page 1667: ...dress 0xFA11_0330 AVI_DATA06 R W Address 0xFA11_0334 AVI_DATA07 R W Address 0xFA11_0338 AVI_DATA08 R W Address 0xFA11_033C AVI_DATA09 R W Address 0xFA11_0340 AVI_DATA10 R W Address 0xFA11_0344 AVI_DATA11 R W Address 0xFA11_0348 AVI_DATA12 R W Address 0xFA11_034C AVI_DATA13 R W Address 0xFA11_0350 AVI_DATA01 AVI_DATA13 Bit Description Initial State AVI_DATA01 AVI_DATA13 7 0 Specifies the AVI Infofr...

Page 1668: ...CHECK_SUM Bit Description Initial State AUI_CHECK_SUM 7 0 Specifies the AUI checksum data PB0 byte of AUI packet body 0x00 10 3 3 49 Audio InfoFrame Register AUI_DATA1 5 AUI_DATA1 R W Address 0xFA11_0380 AUI_DATA2 R W Address 0xFA11_0384 AUI_DATA3 R W Address 0xFA11_0388 AUI_DATA4 R W Address 0xFA11_038C AUI_DATA5 R W Address 0xFA11_0390 AUI_DATA1 AUI_DATA5 Bit Description Initial State AUI_BYTE1 ...

Page 1669: ... 0xFA11_03B0 MPG_CHECK_SUM Bit Description Initial State MPG_CHECK_SUM 7 0 Specifies the MPG infoframe checksum register PB0 byte of MPG packet body 0x00 10 3 3 52 MPEG Source InfoFrame MPG_DATA1 5 MPG_DATA1 R W Address 0xFA11_03C0 MPG_DATA2 R W Address 0xFA11_03C4 MPG_DATA3 R W Address 0xFA11_03C8 MPG_DATA4 R W Address 0xFA11_03CC MPG_DATA5 R W Address 0xFA11_03D0 MPG_DATA1 MPG_ DATA5 Bit Descrip...

Page 1670: ...me SPD_CON R W Address 0xFA11_0400 SPD_CON Bit Description Initial State 7 2 Reserved 6b000000 SPD_TX_CON 1 0 00 Does not transmit 01 Transmits once 1x Transmits every vsync 2b00 10 3 3 54 Source Product Descriptor Infoframe SPD_HEADER0 1 2 SPD_HEADER0 R W Address 0xFA11_0410 SPD_HEADER1 R W Address 0xFA11_0414 SPD_HEADER2 R W Address 0xFA11_0418 SPD_HEADER0 1 2 Bit Description Initial State SPD_H...

Page 1671: ...1 R W Address 0xFA11_044C SPD_DATA12 R W Address 0xFA11_0450 SPD_DATA13 R W Address 0xFA11_0454 SPD_DATA14 R W Address 0xFA11_0458 SPD_DATA15 R W Address 0xFA11_045C SPD_DATA16 R W Address 0xFA11_0460 SPD_DATA17 R W Address 0xFA11_0464 SPD_DATA18 R W Address 0xFA11_0468 SPD_DATA19 R W Address 0xFA11_046C SPD_DATA20 R W Address 0xFA11_0470 SPD_DATA21 R W Address 0xFA11_0474 SPD_DATA22 R W Address 0...

Page 1672: ...Address 0xFA11_0620 HDCP_SHA1_09 R W Address 0xFA11_0624 HDCP_SHA1_10 R W Address 0xFA11_0628 HDCP_SHA1_11 R W Address 0xFA11_062C HDCP_SHA1_12 R W Address 0xFA11_0630 HDCP_SHA1_13 R W Address 0xFA11_0634 HDCP_SHA1_14 R W Address 0xFA11_0638 HDCP_SHA1_15 R W Address 0xFA11_063C HDCP_SHA1_16 R W Address 0xFA11_0640 HDCP_SHA1_17 R W Address 0xFA11_0644 HDCP_SHA1_18 R W Address 0xFA11_0648 HDCP_SHA1_...

Page 1673: ...0 Indicates that the SHA 1 comparison succeeds Must be cleared by SW by writing 0 0 Valid 1 Not valid 0 10 3 3 58 HDCP Register Description HDCP_KSV_LIST_0 4 HDCP_KSV_LIST_0 R W Address 0xFA11_0650 HDCP_KSV_LIST_1 R W Address 0xFA11_0654 HDCP_KSV_LIST_2 R W Address 0xFA11_0658 HDCP_KSV_LIST_3 R W Address 0xFA11_065C HDCP_KSV_LIST_4 R W Address 0xFA11_0660 HDCP_KSV_LIST_0 4 Bit Description Initial ...

Page 1674: ...e in HDCP_KSV_LIST_X registers is the last one 0 Not End 1 End 0 Hdcp_Ksv_Read 0 After writing KSV data in HDCP_KSV_LIST_X registers the HDCP SHA 1 module keeps the KSV value in internal buffer and sets this flag to 1 for notifying it has been read After setting the flag to 1 the SW clears to 0 at the same time when writing the HDCP_KSV_WRITE_DONE bit for next KSV list value 0 Not Read 1 Read 1 10...

Page 1675: ...ECK_RESULT Bit Description Initial State 7 2 Reserved 6b000000 Ri_Match_Result 1 0 Writes the result of comparison between Ri of Rx and Tx as the following values Ri Tx Ri Rx Must be cleared by SW after setting 10 or 11 before next Ri interrupt occurs 0x Don t care 10 Ri Ri 11 Ri Ri 2b00 10 3 3 63 HDCP Register Description HDCP_BKSV0 4 HDCP_BKSV0 R W Address 0xFA11_06A0 HDCP_BKSV1 R W Address 0xFA...

Page 1676: ...n Initial State HDCP_AKSV 39 0 Specifies the KSV value of transmitter All zeros 10 3 3 65 HDCP Register Description HDCP_An_0 7 HDCP_An_0 R Address 0xFA11_06E0 HDCP_An_1 R Address 0xFA11_06E4 HDCP_An_2 R Address 0xFA11_06E8 HDCP_An_3 R Address 0xFA11_06EC HDCP_An_4 R Address 0xFA11_06F0 HDCP_An_5 R Address 0xFA11_06F4 HDCP_An_6 R Address 0xFA11_06F8 HDCP_An_7 R Address 0xFA11_06FC HDCP_An_0 7 Bit ...

Page 1677: ... advance cipher and enhanced link verification 0 Does not set 1 Sets 0 Fast_Reauthentication 0 Specifies all HDMI receivers that are capable of reauthentication 0 Does not set 1 Sets 0 10 3 3 67 HDCP Register Description HDCP_BSTATUS_0 1 HDCP_BSTATUS_0 R W Address 0xFA11_0710 HDCP_BSTATUS_1 R W Address 0xFA11_0714 HDCP_BSTATUS_0 1 Bit Description Initial State 15 13 Reserved 3b000 Hdmi_Mode 12 Spe...

Page 1678: ...scription Initial State 7 1 Reserved 7b0000000 HDCP_I2C_INT 0 Specifies the HDCP I2C interrupt status active high It indicates the start of I2C transaction if it is set After active it should be cleared by S W by writing 0 0 Does not occur 1 Occurs 0 10 3 3 70 HDCP Register Description HDCP_AN_INT R W Address 0xFA11_0790 HDCP_AN_INT Bit Description Initial State 7 1 Reserved 7b0000000 HDCP_AN_INT ...

Page 1679: ...ve high If the repeater bit value is set after 1st authentication success this bit is set After active it should be cleared by S W by writing 0 0 Does not occur 1 Occurs 0 10 3 3 72 HDCP Register Description HDCP_RI_INT R W Address 0xFA11_07B0 HDCP_RI_INT Bit Description Initial State 7 1 Reserved 7b0000000 HDCP_Ri_INT 0 If Ri value is updated internally at every 128 video frames it is set to high...

Page 1680: ...errupt occurs 7b0000000 10 3 3 74 Ri Check Register HDCP_Ri_Compare_1 R W Address 0xFA11_07D4 HDCP_Ri_Compare_1 Bit Description Initial State Enable 7 Enables the interrupt for this frame number index 0 Frame Number index 6 0 If the frame count reaches frame number index an Ri Link integrity check interrupt occurs 7b1111111 10 3 3 75 Ri Check Register HDCP_Frame_Count R Address 0xFA11_07E0 HDCP_Fr...

Page 1681: ...1 Bit Description Initial State Next_Field 7 Indicates the effectiveness of GBD carried in this packet on the next video field 0 GBD_profile 6 4 Specifies the transmission profile number only profile 0 is supported 3b000 Affected_Gamut_Seq_Num 3 0 Indicates which video fields are relevant for this metadata 4b0000 10 3 3 79 Gamut Metadata Packet Register GAMUT_HEADER2 R W Address 0xFA11_050C GAMUT_...

Page 1682: ...T_METADATA12 R W Address 0xFA11_0540 GAMUT_METADATA13 R W Address 0xFA11_0544 GAMUT_METADATA14 R W Address 0xFA11_0548 GAMUT_METADATA15 R W Address 0xFA11_054C GAMUT_METADATA16 R W Address 0xFA11_0550 GAMUT_METADATA17 R W Address 0xFA11_0554 GAMUT_METADATA18 R W Address 0xFA11_0558 GAMUT_METADATA19 R W Address 0xFA11_055C GAMUT_METADATA20 R W Address 0xFA11_0560 GAMUT_METADATA21 R W Address 0xFA11...

Page 1683: ...b000000 Ext_Video_En 1 0 Ext off 1 Ext on 0 Video Pattern Enable 0 0 Disables 1 Uses internally generated video pattern 0 10 3 3 82 Video Mode Register HPD_GEN R W Address 0xFA11_05C8 HPD_GEN Bit Description Initial State HPD_Duration 7 0 Specifies the number of cycles for determining stable HPD input Internal count TMDS clock HPD_Duration 16 cycles Default value 0x1 16 TMDS clock cycles 0x01 ...

Page 1684: ... the clock should not cause stalling of HDMI data transfer Therefore the system processor requests disabling of the clock by setting the power_on register to low and the module acknowledges this request by setting the ready_clk_down register to high after a current transaction on the I2C bus and HDMI is finished The module must not commence a new bus transaction until the system processor sets the...

Page 1685: ... by the system processor keep their values 01b This command should be asserted after SPDIFIN_CLK_CTRL power_on is set SPDIFIN starts the clock recovery When recovery is done SPDIFIN detects preambles of SPDIF signal format and stream data header abnormal time signal input abnormal signal input and also reports these status via interrupts in SPDIFIN_IRQ_STATUS 11b Specifies the 01b case operations ...

Page 1686: ...erved 0 5 Reserved 0 stream_header_detected_ir_en 4 Specifies the mask bit for Interrupt 4 0 stream_header_not_detected_ir_en 3 Specifies the mask bit for Interrupt 3 0 wrong_preamble_ir_en 2 Specifies the mask bit for Interrupt 2 0 ch_status_recovered_ir_en 1 Specifies the mask bit for Interrupt 1 0 wrong_signal_ir_en 0 Specifies the mask bit for Interrupt 0 0 For every bit 0 Disables interrupt g...

Page 1687: ...errupt is asserted if SPDIFIN_OP_CTRL op_ctrl is equal to 001b or 011b Cases for interrupt Case1 Initially after power_on Case2 Next stream header at right time if receiving stream data with SPDIFIN_CONFIG data_type set as stream mode Case3 Initially detects stream header if receiving stream data with SPDIFIN_CONFIG data_type is set as PCM mode 0 stream_header_not_detected_ir 3 0 No interrupt 1 Do...

Page 1688: ...nly supports consumer mode so only 36 bits are reconstructed If you want to see the channel status bits through SPDIFIN_CH_STATUS_x read two consecutive ch_status_recovered_ir and the register each time If these two channel status values are the same you can rely on that value 0 wrong_signal_ir 0 0 No interrupt 1 Clock recovery fails Cannot recover the clock from input due to tolerable range viola...

Page 1689: ...e 0 0 PcPd_value_mode 4 0 Automatically sets 1 Manually sets If 0 is used for automatic setting Pc and Pd values are chosen by value of Pc and Pd from decoded stream header as reported in SPDIFIN_Px_INFO If you set this register the receiver will use SPDIFIN_USER_VALUE 31 16 and SPDIFIN_USER_VALUE 15 4 values as Pc and Pd respectively instead of decoded data from stream header as reported in SPDIF...

Page 1690: ...m one subframe with zero padding to MSB part For example 0x00ffffff for 24 bit data With stream mode set word_length_value_mode as 1 and set SPDIFIN_USER_VALUE word_length_manual as 3b000 These two modes will be applied to both modes of SPDIFIN_CONFIG data_type that is PCM or stream For more information see SPDIFIN_DATA_BUF_x 0 10 3 4 6 SPDIF Register SPDIFIN_CONFIG_2 R W Address 0xFA13_0014 SPDIF...

Page 1691: ...rd length Used as size for transferring data to memory via HDMI valid only when SPDIFIN_CONFIG word_length_value_mode is set for manual mode For more information see SPDIFIN_DATA_BUF_x 0 is 1 0 is 0 3 1 101 24 bits 20 bits 001 23 bits 19 bits 010 22 bits 18 bits 011 21 bits 17 bits 100 20 bits 16 bits 0x0 10 3 4 8 SPDIF Register SPDIFIN_USER_VALUE_2 R W Address 0xFA13_0024 SPDIFIN_USER_VALUE_2 Bit...

Page 1692: ...as 16 bits value This register is low by 8 bits Valid only if SPDIFIN_CONFIG PcPd_value_mode is set for manual mode Unit bits 0 10 3 4 10 SPDIF Register SPDIFIN_USER_VALUE_4 R W Address 0xFA13_002C SPDIFIN_USER_VALUE_4 Bit Description Initial State burst_payload_length_manual_ high 7 0 Specifies the burst_payload_length_manual 15 8 Burst_payload_length register has 16 bits value This register is h...

Page 1693: ...er format 1 Professional format 0 This register is updated every 192 frames 1 block of SPDIF format SPDIFIN_CH_STATUS_0_1 7 0 is the matched internal register SPDIFIN_CH_STATUS_0 7 0 10 3 4 12 Channel Status Register SPDIFIN_CH_STATUS_0_2 R Address 0xFA13_0034 SPDIFIN_CH_STATUS_0_2 Bit Description Initial State category_code 7 0 Equipment type 8 15 CD player 1000_0000 DAT player 1100_000L DCC play...

Page 1694: ...sampling frequency 0100 22 05kHz 0000 44 1kHz 1000 88 2kHz 1100 176 4kHz 0110 24kHz 0010 48kHz 1010 96kHz 1110 192kHz 0011 32kHz 0x0 10 3 4 15 Channel Status Register SPDIFIN_CH_STATUS_1 R Address 0xFA13_0040 SPDIFIN_CH_STATUS_1 Bit Description Initial State 7 4 Reserved 0x0 word_length 3 1 Specifies the word length field_size 1 field_size 0 000 not indicated not indicated 101 24 bits 20 bits 100 ...

Page 1695: ...N_CONFIG clk_divisor Unit SPDIF_internal_clk cycles Recommended value for locking incoming signals Over 0x220 8 5timesx64 bits 0x00 10 3 4 17 SPDIFIN Info Register SPDIFIN_CH_STATUS_2 R Address 0xFA13_004C SPDIFIN_CH_STATUS_2 Bit Description Initial State frame_cnt_high 7 0 Specifies the frame count value 15 8 Frame_cnt register has 16 bits value This is high by 8 bits The period of a frame two su...

Page 1696: ...eserved 11d 12d 13d DTS 14d 31d Reserved 5b00000 10 3 4 19 SPDIFIN Info Register SPDIFIN_Pc_INFO_2 R Address 0xFA13_0054 SPDIFIN_Pc_INFO_2 Bit Description Initial State bit_stream_number 7 5 Specifies the bit stream number 3b000 data_type_dependent_info 4 0 Specifies the data type dependent information 5b00000 10 3 4 20 SPDIFIN Info Register SPDIFIN_Pd_INFO_1 R Address 0xFA13_0058 SPDIFIN_Pd_INFO_...

Page 1697: ...G data_align is 0 for 16 bit received_data is equal to data_ N th data_ N 1 th If SPDIFIN_CONFIG data_align is 1 for 32 bit received_data is equal to U V C P zero padding and data n 0 If SPDIFIN_CONFIG U_V_P_report is 0 received_data is equal to zero padding data n 0 where n is dependent on SPDIFIN_CH_STATUS_1 and word_length if SPDIFIN_CONFIG data_type is 0 for PCM n is equal to 15 if SPDIFIN_CON...

Page 1698: ...FIN_CONFIG data_align is 0 for 16 bit received_data is equal to data_ N th data_ N 1 th If SPDIFIN_CONFIG data_align is 1 for 32 bit received_data is equal to U V C P zero padding data n 0 If SPDIFIN_CONFIG U_V_P_report is 0 received_data is equal to zero padding data n 0 where n is dependent on SPDIFIN_CH_STATUS_1 and word_length if SPDIFIN_CONFIG data_type is 0 for PCM n is equal to 15 if SPDIFI...

Page 1699: ...al State 7 2 Reserved 6b000000 r_sc_pol 1 Specifies the SDATA is synchronous to 0 SCLK falling edge 1 SCLK rising edge 0 r_ch_pol 0 Specifies the LRCLK polarity 0 Left channel for low polarity 1 Left channel for high polarity 0 10 3 5 3 I2S Register I2S_CON_2 R W Address 0xFA14_0008 I2S_CON_2 Bit Description Initial State 7 Reserved 0 mlsb 6 0 MSB first mode 1 LSB first mode 0 bit_ch 5 4 Specifies...

Page 1700: ..._i2s_in 4 3b011 i_i2s_in 3 3b010 i_i2s_in 2 3b001 i_i2s_in 1 3b000 i_i2s_in 0 Note LRCK is selected with i_i2s_in 6 0x110 3b111 10 3 5 5 I2S Register I2S_PIN_SEL_1 R W Address 0xFA14_0010 I2S_PIN_SEL_1 Bit Description Initial State 7 Reserved 0 pin_sel_3 6 4 Selects the SDATA_1 I2S 3b111 i_i2s_in 3 3b110 i_i2s_in 6 3b101 i_i2s_in 5 3b100 i_i2s_in 4 3b011 i_i2s_in 3 3b010 i_i2s_in 2 3b001 i_i2s_in ...

Page 1701: ...1 0x001 3b111 3 0 0 pin_sel_4 2 0 Selects the SDATA_2 I2S 3b111 i_i2s_in 4 3b110 i_i2s_in 6 3b101 i_i2s_in 5 3b100 i_i2s_in 4 3b011 i_i2s_in 3 3b010 i_i2s_in 2 3b001 i_i2s_in 1 3b000 i_i2s_in 0 Note SDATA_2 is selected with i_i2s_in 2 0x010 3b111 10 3 5 7 I2S Register I2S_PIN_SEL_3 R W Address 0xFA14_0018 I2S_PIN_SEL_3 Bit Description Initial State 7 3 Reserved 0 pin_sel_6 2 0 Selects the DSD_D5 D...

Page 1702: ...mber of stage of noise filter for I2S input pins 000 no filtering 001 2 stage filter 010 3 stage filter 011 4 stage filter 100 5 stage filter Others Reserved 3b011 in_en 4 Enables i2s_in which is a sub module at the input stage 0 Disables i2s_in module 1 Enables i2s_in module If disabled all output data is 0 0 audio_sel 3 2 Selects the audio 2b00 Enables SPDIF audio data 2b01 Enables I2S audio dat...

Page 1703: ...H_0 I2S_CH_ST_CH4 To reflect the user configuration in the channel status registers set channel_status_reload bit in I2S_CH_ST_CON then I2S Rx module copies the channel status registers into the shadow channel status registers at the beginning of an IEC 60958 block 10 3 5 11 Channel Status Register I2S_CH_ST_0 I2S_CH_ST_SH_0 I2S_CH_ST_0 R W Address 0xFA14_0028 I2S_CH_ST_SH_0 R Address 0xFA14_003C ...

Page 1704: ..._ST_SH_2 R Address 0xFA14_0044 I2S_CH_ST_2 I2S_CH_ST_SH_2 Bit Description Initial State channel_number 7 4 Specifies the channel number Note bit4 is LSB 0 source_number 3 0 Specifies the source number Note bit0 is LSB 0 10 3 5 14 Channel Status Register I2S_CH_ST_3 I2S_CH_ST_SH_3 I2S_CH_ST_3 R W Address 0xFA14_0034 I2S_CH_ST_SH_3 R Address 0xFA14_0048 I2S_CH_ST_3 I2S_CH_ST_SH_3 Bit Description Ini...

Page 1705: ...efer to the original sampling frequency specified in IEC 60958 3 0x0 Word_Length 3 1 Specifies the word length Max length 24 bits 20 bits 3b000 not defined not defined 3b001 20 bits 16 bits 3b010 22 bits 18 bits 3b100 23 bits 19 bits 3b101 24 bits 20 bits 3b110 21 bits 17 bits 3b000 Max_Word_Length 0 Specifies the maximum sample word length 1 24 bits 0 20 bits 0 10 3 5 16 Channel Status Register I...

Page 1706: ...bles channel 2 left audio data output 0 CH1_R_en 3 0 Disables channel 1 right audio data output 1 Enables channel 1 right audio data output 0 CH1_L_en 2 0 Disables channel 1 left audio data output 1 Enables channel 1 left audio data output 0 CH0_R_en 1 0 Disables channel 0 right audio data output 1 Enables channel 0 right audio data output 1 CH0_L_en 0 0 Disables channel 0 left audio data output 1...

Page 1707: ...ster I2S_IRQ_STATUS R W Address 0xFA14_0060 I2S_IRQ_STATUS Bit Description Initial State 7 2 Reserved 0 int_2 1 Specifies the interrupt status that is the wrong register setting This interrupt is asserted if the I2S_CON_2 bit_ch is set to 32fs while I2S_CON_2 data_num is set to either 20 bit or 24 bit According to the wrong register setting some audio data MSB bits may be removed The audio data is...

Page 1708: ...PCMX_Y 15 8 I2S_CHX_Y_2 PCMX_Y 23 16 I2S_CHX_Y_3 PCMX_Y 27 24 Channel 3 has 24 bit width I2S_CH3_Y_0 PCM3_Y 7 0 I2S_CH3_Y_1 PCM3_Y 15 8 I2S_CH3_Y_2 PCM3_Y 23 16 0x00 10 3 5 22 Output Buffer Register I2S_CUV_L_R R Address 0xFA14_00DC I2S_CUV_L_R Bit Description Initial State 7 Reserved 0 CUV_R 6 4 Specifies the VUCP data of right channel CUV_R 3 0 valid bit user bit channel state bit parity bit 3b0...

Page 1709: ...n 1 Enables field mode For 1080i this should be enabled 0 tg_en 0 Specifies the TG global enable bit 0 10 3 6 2 Horizontal Full Size TG_H_FSZ_L R W Address 0xFA15_0018 TG_H_FSZ_L Bit Description Initial State TG_H_FSZ_L 7 0 Specifies the horizontal full size 1 8191 Lower part 0x72 10 3 6 3 Horizontal Full Size TG_H_FSZ_H R W Address 0xFA15_001C TG_H_FSZ_H Bit Description Initial State Reserved 7 5...

Page 1710: ...e horizontal active size 0 4095 Lower part 0x00 10 3 6 7 Horizontal Active Size TG_HACT_SZ_H R W Address 0xFA15_002C TG_HACT_SZ_H Bit Description Initial State Reserved 7 4 Reserved 0x0 TG_HACT_SZ_H 3 0 Specifies the horizontal active size 0 4095 Upper part 0x5 10 3 6 8 Vertical Full Size TG_V_FSZ_L R W Address 0xFA15_0030 TG_V_FSZ_L Bit Description Initial State TG_V_FSZ_L 7 0 Specifies the verti...

Page 1711: ...served 7 3 Reserved 0x0 TG_VSYNC_H 2 0 Specifies the vertical sync position If field enable is set this bit takes the top field vsync position 1 2047 Upper part 0x0 10 3 6 12 Bottom Field VSYNC Position TG_VSYNC2_L R W Address 0xFA15_0040 TG_VSYNC2_L Bit Description Initial State TG_VSYNC2_L 7 0 Specifies the vertical sync position for bottom field 1 2047 Lower part 0x33 10 3 6 13 Bottom Field VSY...

Page 1712: ..._VACT_ST_H Bit Description Initial State Reserved 7 3 Reserved 0x0 TG_VACT_ST_H 2 0 Specifies the vertical active start position 1 2047 Upper part 0x0 10 3 6 16 Vertical Active Size TG_VACT_SZ_L R W Address 0xFA15_0050 TG_VACT_SZ_L Bit Description Initial State TG_VACT_SZ_L 7 0 Specifies the vertical active size 0 2047 Lower part 0xD0 10 3 6 17 Vertical Active Size TG_TACT_SZ_H R W Address 0xFA15_...

Page 1713: ... Reserved 0x0 TG_FIELD_CHG_H 2 0 Specifies the HDMI field position Upper part 0x2 10 3 6 20 Bottom Field Vertical Active Start Position TG_VACT_ST2_L R W Address 0xFA15_0060 TG_VACT_ST2_L Bit Description Initial State TG_VACT_ST2_L 7 0 Specifies the HDMI vertical active start position for bottom field Lower part 0x48 10 3 6 21 Bottom Field VSYNC Position for HDMI TG_VACT_ST2_H R W Address 0xFA15_0...

Page 1714: ...e Reserved 7 3 Reserved 0x0 TG_VSYNC_TOP_HDMI_H 2 0 Specifies the HDMI VSYNC position for top field Upper part 0x0 10 3 6 24 Bottom Field VSYNC Position for HDMI TG_VSYNC_BOT_HDMI_L R W Address 0xFA15_0080 TG_VSYNC_BOT_HDMI_L Bit Description Initial State TG_VSYNC_BOT_HDMI_L 7 0 Specifies the HDMI VSYNC position for bottom field Lower part 0x01 10 3 6 25 Bottom Field VSYNC Position for HDMI TG_VSY...

Page 1715: ...on Initial State Reserved 7 3 Reserved 0x0 TG_FIELD_TOP_HDMI_H 2 0 Specifies the HDMI top field start position Upper part 0x0 10 3 6 28 Bottom Field Change Start Position for HDMI TG_FIELD_BOT_HDMI_L R W Address 0xFA15_0090 TG_FIELD_BOT_HDMI_L Bit Description Initial State TG_FIELD_BOT_HDMI_L 7 0 Specifies the HDMI bottom field start position Lower part 0x33 10 3 6 29 Bottom Field VSYNC Start Posi...

Page 1716: ...ock The HSYNC width is MHL_HSYNC_WIDTH 1 0xF 10 3 6 31 VSYNC width Configuration for MHL Interface MHL_VSYNC_WIDTH R W Address 0xFA15_0180 MHL_VSYNC_WIDTH Bit Description Initial State MHL_VSYNC_WIDTH 7 0 Specifies the VSYNC width for MHL interface Unit line 0x1 10 3 6 32 RGB Clock Inversion for MHL Interface MHL_CLK_INV R W Address 0xFA15_0184 MHL_CLK_INV Bit Description Initial State MHL_CLK_INV...

Page 1717: ...te 7 3 Reserved 4b0000 EFUSE_ECC_FAIL 2 0 Normal 1 ECC fail EFUSE_ECC_BUSY 1 0 Not busy 1 Busy EFUSE_ECC_DONE 0 0 Normal 1 ECC done 0 10 3 6 35 HDCP E FUSE Control Register EFUSE_ADDR_WIDTH R W Address 0xFA16_0008 EFUSE_ADDR_WIDTH Bit Description Initial State EFUSE_ADDR_WIDTH 7 0 Specifies the address width Unit HDMI link PCLK default 83MHz 12n 0x14 10 3 6 36 HDCP E FUSE Control Register EFUSE_SI...

Page 1718: ... Bit Description Initial State EFUSE_PRCHG_ASSERT 7 0 Specifies the PRCHG asserting position Unit HDMI Link PCLK default 83MHz 12n 0x0 10 3 6 39 HDCP E FUSE Control Register EFUSE_PRCHG_DE ASSERT R W Address 0xFA16_0018 EFUSE_PRCHG_DE ASSERT Bit Description Initial State EFUSE_PRCHG_DEASSERT 7 0 Specifies the PRCHG de asserting position Unit HDMI link PCLK default 83MHz 12n 0xC 10 3 6 40 HDCP E FU...

Page 1719: ... Bit Description Initial State EFUSE_SCK_ASSERT 7 0 Specifies the SCK asserting position Unit HDMI link PCLK default 83MHz 12n 0x4 10 3 6 44 HDCP E FUSE Control Register EFUSE_SCK_DEASSERT R W Address 0xFA16_002C EFUSE_SCK_DEASSERT Bit Description Initial State EFUSE_SCK_DEASSERT 7 0 Specifies the SCK de asserting position Unit HDMI link PCLK default 83MHz 12n 0xC 10 3 6 45 HDCP E FUSE Control Reg...

Page 1720: ...also specifies the status of Tx_Done interrupt 0 Running or idle 1 Finishes CEC Tx transfer It will be cleared if Tx_Enable bit of CEC_TX_CTRL_0 is reset if Clear_Intr_Tx_Done or Clear_Intr_Tx_Error bit in CEC_INTR_CLEAR register is set 0 Tx_Transferring 1 If TX Running is set this field is valid 0 Tx waits for the CEC Bus 1 CEC Tx transfers data via CEC Bus 0 Tx_Running 0 0 Tx Idle 1 Enables CEC ...

Page 1721: ...lso specifies the status of Rx_Error interrupt and is valid only if Rx_Done bit is set 0 No error occurs 1 An error occurs while receiving a CEC message It will be cleared if Rx_Enable bit of CEC_RX_CTRL_0 is reset if Clear_Intr_Rx_Done or Clear_Intr_Rx_Error bit in CEC_INTR_CLEAR register is set 0 Rx_Done 2 Specifies the CEC Rx done interrupt flag This bit field also specifies the status of Rx_Do...

Page 1722: ..._Rx_Done or Clear_Intr_Rx_Error bit in CEC_Intr_Clear register is set 0 10 3 6 51 CEC Configure Register CEC_INTR_MASK R W Address 0xE1B0_0010 CEC_INTR_MASK Bit Description Initial State 7 6 Reserved 2b00 Mask_Intr_Rx_Error 5 Specifies the Rx_Error interrupt mask bit 0 Enables 1 Disables 0 Mask_Intr_Rx_Done 4 Specifies the Rx_Done interrupt mask bit 0 Enables 1 Disables 0 3 2 Reserved 2b00 Mask_In...

Page 1723: ...nd Tx_Bytes_Received fields in CEC_TX_STATUS_0 and 1 registers Resets to 0 after one clock 0 Clear_Intr_Tx_Done 0 Specifies the Tx_Done interrupt clear bit 0 No effect 1 Clears Tx_Done and Tx_Bytes_Received fields in CEC_TX_STATUS_0 and 1 registers Resets to 0 after one clock 0 10 3 6 53 CEC Configure Register CEC_LOGIC_ADDR R W Address 0xE1B0_0020 CEC_LOGIC_ADDR Bit Description Initial State 7 4 ...

Page 1724: ...rved 2b00 Tx_BCast 1 Specifies the CEC Tx broadcast message bit This bit also specifies the CEC message in CEC_TX_BUFFER_00 15 which is directly addressed addressed to a single device or broadcast This bit determines whether a block transfer is acknowledged or not according to ACK scheme in CEC specification section CEC 6 1 2 0 Directly addressed message 1 Broadcast message 0 Tx_Start 0 Specifies ...

Page 1725: ...1 CEC Tx sends a start bit 0 Tx_Sending_Hdr_Blk 5 Specifies the CEC Tx header block sending flag bit 0 Tx is in other state 1 CEC Tx sends the header block 0 Tx_Sending_Data_Blk 4 Specifies the CEC Tx data block sending flag bit 0 Tx is in other state 1 CEC Tx sends data blocks 0 Tx_Latest_Initiator 3 Specifies the CEC Tx last initiator flag bit 0 This device is not the latest initiator on the CEC...

Page 1726: ...n other state 1 Tx waits for SFT with a precondition that Tx is the new initiator and wants to send a frame SFT 5x2 4ms 0 Tx_Wait_SFT_Retran 4 Specifies the CEC Tx signal free time for a new initiator waiting flag bit 0 Tx is in other state 1 Tx waits for SFT with a precondition the precondition is that Tx should attempt to retransmit the message SFT 3 x2 4ms 0 Tx_Retrans_Cnt 3 1 Specifies the cur...

Page 1727: ... R W Address 0xE1B0_00A0 CEC_ TX_BUFFER_9 R W Address 0xE1B0_00A4 CEC_ TX_BUFFER_10 R W Address 0xE1B0_00A8 CEC_ TX_BUFFER_11 R W Address 0xE1B0_00AC CEC_ TX_BUFFER_12 R W Address 0xE1B0_00B0 CEC_ TX_BUFFER_13 R W Address 0xE1B0_00B4 CEC_ TX_BUFFER_14 R W Address 0xE1B0_00B8 CEC_ TX_BUFFER_15 R W Address 0xE1B0_00BC CEC_ TX_BUFFER_0 CEC_ TX_BUFFER_15 Bit Description Initial State Tx_Block_0 Tx_Blo...

Page 1728: ...gical 0 from the starting of one bit transfer falling edge on the CEC bus Rx checks whether the duration is longer than the maximum time the CEC bus can be in logical 0 max 1 7 ms 0 Check_Start_Bit_Error 4 Specifies the CEC Rx start bit error check enable bit 0 Does not check start bit error 1 Checks start bit error while receiving a start bit After receiving a start bit from the CEC bus CEC Rx ch...

Page 1729: ...te 1 CEC Rx waits for a message 0 Rx_Receiving_Start_Bit 6 Specifies the CEC Rx start bit receiving flag bit 0 Rx is in other state 1 CEC Rx receives a start bit 0 Rx_Receiving_Hdr_Blk 5 Specifies the CEC Rx header block receiving flag bit 0 Rx is in other state 1 CEC Rx receives a header block 0 Rx_Receiving_Data_Blk 4 Specifies the CEC Rx data block receiving flag bit 0 Rx is in other state 1 CE...

Page 1730: ... CEC RX sets this bit This bit field will be set to 0 if Clear_Intr_Rx_Done or Clear_Intr_Rx_Error bit in CEC_INTR_CLEAR register is set 0 Start_Bit_Error 4 Specifies the CEC Rx start bit error flag bit 0 No start bit error occurs 1 A start bit error occurs while receiving a message While receiving a start bit from the CEC bus CEC Rx checks the duration of logical 0 and 1 of a starting bit as spec...

Page 1731: ..._0114 CEC_RX_BUFFER_6 R Address 0xE1B0_0118 CEC_RX_BUFFER_7 R Address 0xE1B0_011C CEC_RX_BUFFER_8 R Address 0xE1B0_0120 CEC_RX_BUFFER_9 R Address 0xE1B0_0124 CEC_RX_BUFFER_10 R Address 0xE1B0_0128 CEC_RX_BUFFER_11 R Address 0xE1B0_012C CEC_RX_BUFFER_12 R Address 0xE1B0_0130 CEC_RX_BUFFER_13 R Address 0xE1B0_0134 CEC_RX_BUFFER_14 R Address 0xE1B0_0138 CEC_RX_BUFFER_15 R Address 0xE1B0_013C CEC_RX_B...

Page 1732: ...e on the CEC bus that is stable for more than Filter_Th cycles 1 6 1 Reserved 6b000000 Filter_Enable 0 Specifies the CEC filter enable bit 0 Disables filter Directly passes CEC input to CEC Tx Rx 1 Enables filter Filter propagates signals stable for more Filter_Th cycles 1 10 3 6 65 Input Filtering Register CEC_ FILTER_TH R W Address 0xE1B0_0184 CEC_FILTER_TH Bit Description Initial State Filter_T...

Page 1733: ...TATOR The features of image rotator include Image format YCbCr 4 2 2 interleave YCbCr 4 2 0 non interleave 2 plane and 3 plane RGB565 and RGB888 unpacked Rotate degree 0 90 180 and 270 with flip vertical and flip horizontal Windows offset function Image size up to 64K by 64K The maximum sizes are different from the types of image format Image size restriction memory size shouldn t exceed 16 bit ad...

Page 1734: ...S5PC110_UM 11 10BIMAGE ROTATOR 11 2 11 3 BLOCK DIAGRAM OF IMAGE ROTATOR The Figure 11 1 shows the block diagram of Image Rotator Figure 11 1 Image Rotator Block Diagram ...

Page 1735: ...S5PC110_UM 11 10BIMAGE ROTATOR 11 3 11 4 SUPPORTED IMAGE ROTATION FUNCTIONS The Figure 11 2 shows the rotation functions supported by Image Rotator Figure 11 2 Ported Image Rotation Functions ...

Page 1736: ...rts image rotation with window offset function It is useful function to move from a small portion of a large image to move in a portion of a large image Figure 11 3 Source Image Example with window offset function Figure 11 4 Destination Image Example 90 degree rotated with window offset function ...

Page 1737: ...Image size SRCIMGSIZE and DSTIMGSIZE should be set as follows Image Format Minimum Size Maximum Size RGB888 8 x 8 16K x 16K RGB565 16 x 16 32K x 32K YCbCr422 16 x 16 32K x 32K YCbCr420 2 Plane 32 x 32 64K x 64K in case of Y components YCbCr420 3 Plane 64 x 32 64K x 64K in case of Y components Image coordinates to be rotated SRC_XY and DST_XY should set as follows Image Formats Image Size Restricti...

Page 1738: ..._0038 R W Rotator Source Image Base Address 0x0000_0000 SRCIMGSIZE 0xFA30_003C R W Rotator Source Image X Y Size 0x0000_0000 SRC_XY 0xFA30_0040 R W Rotator Source Image X Y Coordinates 0x0000_0000 SRCROTSIZE 0xFA30_0044 R W Rotator Source Image Rotation Size 0x0000_0000 DSTBASEADDR0 0xFA30_0050 R W Rotator Destination Image Base Address 0x0000_0000 DSTBASEADDR1 0xFA30_0054 R W Rotator Destination ...

Page 1739: ...ed 0x0000 Pattern Writing 16 Write pattern to fill a destination image with a designated pattern 0 Disable pattern writing 1 Enable pattern writing Note if this bit set the information of a source image is ignored 0b Reserved 15 11 Reserved 00000b Input Image Format 10 8 Input image format to be rotated 000 YCbCr 4 2 0 3 plane 001 YCbCr 4 2 0 2 plane 010 Reserved 011 YCbCr 4 2 2 interleave 100 RGB...

Page 1740: ...CBASEADDR0 R W Address 0xFA30_0030 SRCADDRREG0 Bit Description Initial State SRC_IMG_ADDR 31 0 Base address of source image for RGB or Y component 0x0000_0000 11 7 1 5 Rotator Source Image Base Address Register 1 SRCBASEADDR1 R W Address 0xFA30_0034 SRCADDRREG1 Bit Description Initial State SRC_IMG_ADDR 31 0 Base Address of source image for Cb component 0x0000_0000 11 7 1 6 Rotator Source Image Ba...

Page 1741: ... 15 0 Horizontal pixel size of a image to be rotated 0x0000 11 7 1 10 Rotator Destination Image Base Address Register 0 DSTBASEADDR0 R W Address 0xFA30_0050 DSTBASEADDR0 Bit Description Initial State DST_IMG_ADDR 31 0 Address of destination image for RGB or Y component 0x0000_0000 11 7 1 11 Rotator Destination Image Base Address Register 1 DSTBASEADDR1 R W Address 0xFA30_0054 DSTBASEADDR1 Bit Desc...

Page 1742: ...6 Vertical pixel size of a source image 0x0000 DST_XSIZE 15 0 Horizontal pixel size of a source image 0x0000 11 7 1 14 Rotator Destination Image Coordinates Register DST_XY R W Address 0xFA30_0060 DST_XY Bit Description Initial State DST_Y 31 16 The pixel coordinates on Y axis of a image to be rotated 0x0000 DST_X 15 0 The pixel coordinates on X axis of a image to be rotated 0x0000 ...

Page 1743: ...itions such as the Huffman table number and restart interval value into internal control registers 12 2 KEY FEATURES OF JPEG CODEC Compression decompression up to 8192x8192 Minimum Image size for compression decompression is 32x32 Supports following format of compression Refer to figure 9 13 2 Input raw image YCbCr4 2 2 or RGB565 Output JPEG file Baseline JPEG of YCbCr4 2 2 or YCbCr4 2 0 Supports ...

Page 1744: ...2 11BJPEG 12 2 12 3 BLOCK DIAGRAM OF JPEG CODEC DCT Quantization Control circuit internal registers AHB interface JPEG encoder Decoder Huffman codec marker process Quantization Table Huffman Table Figure 12 1 JPEG ...

Page 1745: ...8x8 image data to DCT coefficients Then the quantization process is performed over DCT coefficients by utilizing the quantization tables During decompression dequantization is done and then a DCT coefficient is transformed into image data 12 4 3 HUFFMAN CODER AND MARKER PROCESS During compression Huffman encoding is performed based on the Huffman table and marker process generates the JPEG bit str...

Page 1746: ... component as shown in Figure 12 4 12 5 2 IN DECOMPRESSION MODE In decompression mode input file is baseline JPEG in YCbCr4 4 4 YCbCr4 2 2 YCbCr4 2 0 gray with interleaved scan and output raw image has interleaved YCbCr4 2 2 or YCbCr4 2 0 formats Therefore for input file with YCbCr format decimation and interpolation process is done during decompression In this case decimation is same as downsampl...

Page 1747: ...C110_UM 12 11BJPEG 12 5 Figure 12 5 illustrates the input format of YCbCr4 2 2 This JPEG codec supports type a If input YCbCr4 2 2 format is type b decoder does not work Figure 12 5 YCbCr4 2 2 Color Format ...

Page 1748: ... tables AC DC 2 tables for each and four quantization tables must be configured before compression To set any quantization table and Huffman table first access the corresponding table entry register Then write transfers should follow To understand the write transfer refer to Figure 12 6 The access order for each table is shown below 3 4 1 2 7 8 5 6 11 12 9 10 15 16 13 14 19 20 17 18 23 24 21 22 27...

Page 1749: ... Horizontal Size Register lower 8bit Essential QTBL0 Quantizer Table0 Entries Register Essential QTBL1 Quantizer Table1 Entry Register Essential QTBL2 Quantizer Table2 Entry Register Essential QTBL3 Quantizer Table3 Entry Register Essential OUTFORM Output Color Format of Decompression Essential ENC_STREAM_INTSE Compressed Stream Size Interrupt Setting Register Essential HDTBL0 HDCTBLG0 DC Huffman ...

Page 1750: ...G file after header parsing process Actual raw image size after decompression is the minimum among the values which are the multiple of block size known from color format and larger than or equal to the image size in the header For example if JPEG file is YCbCr4 2 0 format and its size is 170x170 actual size of decompressed raw image is 176x176 2 Proper process such as cropping is needed to displa...

Page 1751: ...eration In condition 3 ENC_STREAM_INT_STAT is read as 1 JPEG operation is stopped and there is no further memory access by JPEG This interrupt is cleared by writing 1 in ENC_STREAM_INT_STAT register In this case JPEG needs reset or S W reset before next operation 12 6 7 INTERRUPT SETTING If this JPGINTSE register is set it invokes the interrupt when the input file for decompression is illegal To e...

Page 1752: ...man table DRI FFDD Define restart interval RSTm FFD0 FFD7 Restart with module 8 count m EOI FFD9 End of image The markers Table 12 3 are subject to process during decompression The other markers except SOF1 SOFF and JPG are ignored 12 6 10 BITSTREAM OF COMPRESSED FILE The created JPEG bit stream is shown in Figure 12 7 In the figure ECS is an acronym of entropy coded segment which is a sequence of...

Page 1753: ...er byte Write JPGY_L 0x0 Vertical resolution Lower byte Write JPGX_U 0x0 Horizontal resolution Upper byte Write JPGX_L 0x0 Horizontal resolution Lower byte Write IMGADR 0x1000_0000 Address for an image to compress Write JPGADR 0x1001_0000 Address for the compressed JPEG file Write COEF1 0x4D_971E Color converter coefficients Write COEF2 0x2c_5783 Color converter coefficients Write COEF3 0x83_6e13 ...

Page 1754: ...ding mode Write JPGINTSE 0x0 Interrupt setting Write OUTFORM 0x1 Output raw image is YCbCr4 2 0 Write IMGADR 0x1000_0000 Address for a decompressed raw image Write JPGADR 0x1001_0000 Address for a JPEG file to decompress Decoding operation start Write JSTART 0x1 After interrupt is detected clear the pending register Read JPGINTST It must be read 0x40 it means normal end Write JPGCOM 0x4 Clear inte...

Page 1755: ...per 8 bit 0x0000_0000 JPGY_L 0xFB60_001C R W Specifies the vertical resolution lower 8 bit 0x0000_0000 JPGX_U 0xFB60_0020 R W Specifies the Horizontal resolution upper 8 bit 0x0000_0000 JPGX_L 0xFB60_0024 R W Specifies the Horizontal resolution lower 8 bit 0x0000_0000 JPGCNT_U 0xFB60_0028 R Specifies the amount of the compressed data in bytes upper 8 bit 0x0000_0000 JPGCNT_M 0xFB60_002C R Specifie...

Page 1756: ...r 0x7FFF_FFFF TIMER_ST 0xFB60_0080 R W Specifies the internal timer status register 0x7FFF_FFFF COMSTAT 0xFB60_0084 R Specifies the command status register 0x0000_0000 OUTFORM 0xFB60_0088 R W Specifies the output color format of decompression 0x0000_0000 VERSION 0xFB60_008C R Specifies the version register 0x0000_0003 Reserved 0xFB60_0090 ENC_STREAM_INTSE 0xFB60_0098 R W Specifies the compressed s...

Page 1757: ... Specifies the Huffman AC Table 0 Group number of the order for occurrence 0x0000_0000 HDCTBL1 0xFB60_0C00 0xFB60_0C3C W Specifies the Huffman DC Table 1 the number of code per code length 0x0000_0000 HDCTBLG1 0xFB60_0C40 0xFB60_0C6C W Specifies the Huffman DC Table 1 Group number of the order for occurrence 0x0000_0000 HACTBL1 0xFB60_0C80 0xFB60_0CBC W Specifies the Huffman AC Table 1 the number ...

Page 1758: ...sion these are read only During compression only 0x1 or 0x2 are allowed 0 12 7 1 2 JPEG Operation Status Register JPGOPR R Address 0xFB60_0004 JPGOPR Bit Description Initial State Reserved 31 1 Reserved 0 JPGOPR 0 0 JPEG is not operating 1 JPEG is operating 0 12 7 1 3 Quantization Table Number Register QTBL R W Address 0xFB60_0008 QTBL Bit Description Initial State Reserved 31 8 Reserved 0 QT_NUM4...

Page 1759: ... 1st color component DC 0 12 7 1 5 JPEG Restart Interval Upper byte Register JPGDRI_U R W Address 0xFB60_0010 JPGDRI_U Bit Description Initial State Reserved 31 8 Reserved 0 JPGDRI_U 7 0 This is a restart interval that identifies the distance between two adjacent Restart Maker RST in terms of Minimum Coded Unit MCU It is valid in compression mode If JPGDRI is set to 0 Define Restart Interval Marke...

Page 1760: ...value in the vertical direction You are not allowed to Set 0 This register is read only during decompression 0 12 7 1 9 JPEG Horizontal Resolution Upper byte Register JPGX_U R W Address 0xFB60_0020 JPGX_U Bit Description Initial State Reserved 31 16 Reserved 0 HOR_RES 15 0 Upper byte of the Image size value in the horizontal direction You are not allowed to Set 0 This register is read only during ...

Page 1761: ...ess 0xFB60_002C JPGCNT_M Bit Description Initial State Reserved 31 24 Reserved 0 BYTE_CNT 23 0 Middle byte of the count value the width of 24bits of the amount of compression data Value of the register will be clear when processing starts This register is valid in compression mode 0x00_0000 12 7 1 13 JPEG Byte Count Lower byte Register JPGCNT_L R Address 0xFB60_0030 JPGCNT_L Bit Description Initia...

Page 1762: ... is allowed or not in case there is abnormality in final MCU data number in Huffman coding segments at decompression process In case it is not set error code will not be returned 0 Reserved 4 0 Reserved but should be 0x0 0 12 7 1 15 JPEG Interrupt Status Register JPGINTST R Address 0xFB60_0038 JPGINTST Bit Description Initial State Reserved 31 7 Reserved 0 RESULT_STAT 6 Result status 0 Processing ...

Page 1763: ...Value for this register has to be multiple of 32 In compression mode JPEG file after compression is stored from this address In decompression mode JPEG file before compression is read from this address 0 12 7 1 19 Coefficient for RGB to YCbCr Converter Register COEF1 R W Address 0xFB60_005C COEF1 Bit Description Initial State Reserved 31 24 Reserved 0 COEF11 23 16 Coefficient value of COEF11 0 COE...

Page 1764: ...5 Bitwise Expression of COEFxx Bit 7 6 5 4 3 2 1 0 Value 0 5 0 25 0 125 0 0625 0 03125 0 015625 0 0078125 0 00390625 128 128 1 c B G R 33 COEF 32 COEF 31 COEF 23 COEF 22 COEF 21 COEF COEF13 COEF12 COEF11 Cr Cb Y 12 7 1 22 JPEG Color Mode Register JPGCMOD R W Address 0xFB60_0068 JPGCMOD Bit Description Initial State Reserved 31 8 Reserved 0 MOD_SEL 7 5 Color space of input raw image 0x1 YCbCr4 2 2 ...

Page 1765: ...t 1 Activates Clock 0 12 7 1 24 JPEG Start Register JSTART W Address 0xFB60_0070 JSTART Bit Description Initial State Reserved 31 1 Reserved 0 JSTART 0 To start compression decompression set this value to 1 After one clock it is cleared with 0 internally Before starting operation you must set essential registers 0 12 7 1 25 JPEG SW Reset Register SW_RESET R W Address 0xFB60_0078 SW_RESET Bit Descr...

Page 1766: ...TIMER_INT_STAT 31 Timer interrupt status If timer interrupt is enabled and timer counting value reaches 0 it is set 1 Writing 1 clears this value Writing 0 has no effect 0 TIMER_CNT 30 0 Timer counting value If start or restart it is initiated by TIMER_INIT value and starts to down count If JPEG operation finishes before end of counting it holds the counter value at that time This bit is read only...

Page 1767: ...rupt 1 Enables Compressed stream size interrupt 0 ENC_STREAM_BOUND 23 0 The upper bound of the byte size of output compressed stream is stored in this register This value should be multiple of 32 0xFF_FFE0 12 7 1 31 JPEG Compressed Stream Size Interrupt Status Register ENC_STREAM_INTST R W Address 0xFB60_009C TIMER_ST Bit Description Initial State Reserved 31 1 Reserved 0 ENC_STREAM_INT_ STAT 0 Co...

Page 1768: ...W Quantization of table number 3 64 data with the distance of 4 on address 0x0000 0000 for 64 each data HDCTBL0 0xFB60_0800 0xFB60_0804 0xFB60_083C W JPEG DC Huffman Table 0 Register The number of code per code length 16 data with the distance of 4 on address HDCTBLG0 0xFB60_0840 0xFB60_0844 0xFB60_086C W JPEG DC Huffman Table 0 Register Group number of the order for occurrence 12 data with the di...

Page 1769: ...ance of 4 on address HACTBL1 0xFB60_0C80 0xFB60_0C84 0xFB60_0CBC W JPEG AC Huffman Table 1 Register The number of code per code length 16 data with the distance of 4 on address HACTBLG1 0xFB60_0CC0 0xFB60_0CC4 0xFB60_0F44 W JPEG AC Huffman Table 1 Register Group number of the order for occurrence Group number 162 data with the distance of 4 on address Each data uses the least significant 8 bits of...

Page 1770: ...T support Nearest sampling using Bresnham algorithm o Memory to Screen o Memory to Memory o Reverse Addressing X Positive Negative Y Positive Negative Per pixel Operation Maximum 8000x8000 image size Window Clipping 90 180 270 Rotation X flip Y flip Totally 4 operand Raster Operation ROP4 o Mask Pattern Source Destination Alpha Blending o Alpha Blending with a user specified constant alpha o Per p...

Page 1771: ...ing rule the data of each field is shifted 8 x bits to left where x is the bit width of the field The least significant x bits of the new field data are padded with the most significant x bits of the original field data For example if the R value in RGB_565 format is 5 b11010 it will be converted to 8 b11010110 with three LSBs padded with three MSBs 3 b110 from the original R value Note that the A...

Page 1772: ...data to frame buffer selecting one of two raster operations by mask value combining to bitmap patterns by the selected raster operation changing the dimension of a rectangular image and so on Stretch Bit Block Transfer is implemented using Bresnham algorithm and nearest sampling 13 4 1 1 1 On Screen Rendering On screen bit block transfer copies a rectangular block of pixels on screen to another po...

Page 1773: ... normal mode source image in the memory 2 b01 foreground color 2 b10 background color DST_LEFT_TOP_REG Coordinate of the leftmost topmost coordinate of the destination image DST_RIGHT_BOTTOM_REG Coordinate of the rightmost bottommost coordinate of the destination image DST_SELECT_REG Select one of the following cases 2 b00 normal mode destination image in the memory 2 b01 foreground color 2 b10 ba...

Page 1774: ...ters ROTATE_REG Enable 90 degree rotation SRC_MSK_DIRECT_REG Addressing direction of source mask memory to read DST_PAT_DIRECT_REG Addressing direction of destination pattern memory to read and write 13 4 2 1 2 Rotation Effect 0 Rotated X Original X Rotated Y Original Y 90 Rotated X Original Y Rotated Y Original Width 1 Original X 13 4 2 1 3 Addressing Direction Effect Effect Src X Direction Dst X...

Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...

Page 1776: ...itionally discards a pixel based on the outcome of a comparison between the color value of this pixel of the source destination image and the DR min DR max values If each field R G B A of the color value falls in the range of DR min DR max this pixel is passed to the next stage otherwise discarded User can disable the stencil test on a specific field by clearing the corresponding bits in COLORKEY_...

Page 1777: ... destination image The following equation is used to calculate the pattern pixel coordinate x y X PatternOffsetX x PatternWidth Y PatternOffsetY y PatternHeight where PatternOffsetY and PatternOffsetX are the offset value specified in register PAT_OFFSET_REG and PatternWidth and PatternHeight are size of the pattern specified in register PAT_SIZE_REG Here are some examples on how to use the ROP3 v...

Page 1778: ...mage THIRD_OPERAND_REG Third operand selection for unmasked ROP3 and masked ROP3 ROP4_REG ROP4 Value 13 4 6 ALPHA BLENDING Alpha Blending combines the source color and the destination color in the frame buffer to get the new destination color Alpha Blending equation is decided by source alpha value and user specified alpha value 13 4 6 1 1 Related Registers BITBLT_COMMAND_REG Alpha blending config...

Page 1779: ...A00_0204 R W Source and Mask Direction register 0x0000_0000 DST_PAT_DIRECT_ REG 0xFA00_0208 R W Destination and Pattern Direction register 0x0000_0000 Parameter Setting Registers Source SRC_SELECT_REG 0xFA00_0300 R W Source Image Selection register 0x0000_0000 SRC_BASE_ADDR_ REG 0xFA00_0304 R W Source Image Base Address register 0x0000_0000 SRC_STRIDE_REG 0xFA00_0308 R W Source Stride register 0x0...

Page 1780: ...ftTop coordinates of Clip Window 0x0000_0000 CW_RB_REG 0xFA00_0604 R W RightBottom coordinates of Clip Window 0x0000_0000 Parameter Setting Registers ROP Alpha Setting THIRD_OPERAND_ REG 0xFA00_0610 R W Third Operand Selection register 0x0000_0000 ROP4_REG 0xFA00_0614 R W Raster Operation register 0x0000_0000 ALPHA_REG 0xFA00_0618 R W Alpha value Fading offset value 0x0000_0000 Parameter Setting R...

Page 1781: ...110_UM 13 12BG2D 13 12 Register Address R W Description Reset Value DR_MIN_REG Minimum register DST_COLORKEY_ DR_MAX_REG 0xFA00_0724 R W Destination Colorkey Decision Reference Maximum register 0xFFFF_FFFF ...

Page 1782: ... Command Finished interrupt enable If this bit is set when the graphics engine finishes the execution of command an interrupt occurs and the INTP_CMD_FIN flag in INTC_PEND_REG will be set 0x0 13 5 2 3 Interrupt Pending Register INTC_PEND_REG R W Address 0xFA00_000C INTC_PEND_REG Bit Description Initial State Reserved 31 1 Reserved 0x0 INTP_CMD_FIN 0 Command Finished interrupt flag Writing 1 to thi...

Page 1783: ...ate Reserved 31 3 Reserved 0x0 PATCACHE_CLEAR 2 Pattern cache clear Automatically set to 0b after a cycle This bit is used to invalidate the contents of pattern cache 0 Default stages pattern cache invalidation unchanged 1 Pattern cache starts invalidation 0x0 SRCBUFFER_CLEAR 1 Source buffer clear Automatically set to 0b after a cycle This bit is used to invalidate the contents of source buffer 0 ...

Page 1784: ...1 Alpha Blend with Constant Alpha 2 b10 Alpha Blend with PerPixel Alpha 2 b11 Reserved 0x0 AlphaBlendMode 21 20 Alpha Blending Mode 2 b00 No Alpha Blending 2 b01 Alpha Blending 2 b10 Fading 2 b11 Reserved 0x0 Reserved 19 18 Reserved 0x0 ColorKeyMode 17 16 2 b00 Disable colorkey 2 b01 Enable source colorkey 2 b10 Enable destination colorkey 2 b11 Enable source colorkey and destination colorkey 0x0 ...

Page 1785: ... MskYDirect 5 0 Y positive 1 Y negative 0x0 MskXDirect 4 0 X positive 1 X negative 0x0 Reserved 3 2 Reserved 0x0 SrcYDirect 1 0 Y positive 1 Y negative 0x0 SrcXDirect 0 0 X positive 1 X negative 0x0 NOTE Mask direction is usually same as source direction 13 5 4 3 Destination and Pattern Direction Register DST_PAT_DIRECT_REG R W Address 0xFA00_0208 DST_PAT_DIRECT_REG Bit Description Initial State R...

Page 1786: ...DDR_REG Bit Description Initial State SrcAddr 31 0 Base address of the source image 0x0 13 5 5 3 Source Stride Register SRC_STRIDE_REG R W Address 0xFA00_0308 SRC_STRIDE_REG Bit Description Initial State Reserved 31 16 Reserved 0x0 SrcStride 15 0 Source stride 2 s complement value 0x0 13 5 5 4 Source Image Color Mode Register SRC_COLOR_MODE_REG R W Address 0xFA00_030C SRC_COLOR_MODE_REG Bit Descri...

Page 1787: ... 0x0 Reserved 15 13 Reserved 0x0 SrcLeftX 12 0 Left Top X Coordinate of Source Image Range 0 8000 Requirement SrcLeftX SrcRightX 0x0 13 5 5 6 Source Right Bottom Coordinate Register SRC_RIGHT_BOTTOM_REG R W Address 0xFA00_0314 SRC_RIGHT_ BOTTOM_REG Bit Description Initial State Reserved 31 29 Reserved 0x0 SrcBottomY 28 16 Right Bottom Y Coordinate of Source Image Range 0 8000 0x0 Reserved 15 13 Re...

Page 1788: ...BASE_ADDR_ REG Bit Description Initial State DstAddr 31 0 Base address of the destination image 0x0 13 5 6 3 Destination Stride Register DST_STRIDE_REG R W Address 0xFA00_0408 DST_STRIDE_REG Bit Description Initial State Reserved 31 16 Reserved 0x0 DstStride 15 0 Destination stride 2 s complement value 0x0 13 5 6 4 Destination Image Color Mode Register DST _COLOR_MODE_REG R W Address 0xFA00_040C D...

Page 1789: ...Reserved 15 13 Reserved 0x0 DstLeftX 12 0 Left Top X Coordinate of destination image Range 0 8000 Requirement DstLeftX DstRightX 0x0 13 5 6 6 Destination Right Bottom Coordinate Register DST _RIGHT_BOTTOM_REG R W Address 0xFA00_0414 DST_RIGHT_ BOTTOM_REG Bit Description Initial State Reserved 31 29 Reserved 0x0 DstBottomY 28 16 Right Bottom Y Coordinate of destination image Range 0 8000 0x0 Reserv...

Page 1790: ... 29 Reserved 0x0 PatHeight 28 16 Height of pattern image Range 1 8000 0x1 Reserved 15 13 Reserved 0x0 PatWidth 12 0 Width of pattern image Range 1 8000 0x1 13 5 7 3 Pattern Image Color Mode Register PAT_COLOR_MODE_REG R W Address 0xFA00_0508 PAT_COLOR_ MODE_REG Bit Description Initial State Reserved 31 6 Reserved 0x0 PatChannelOrder 5 4 2 b00 A X RGB 2 b01 RGB A X 2 b10 A X BGR 2 b11 BGR A X 0x0 R...

Page 1791: ... Reserved 0x0 PatOffsetY 28 16 Y value of pattern offset Range 1 8000 0x0 Reserved 15 13 Reserved 0x0 PatOffsetX 12 0 X value of pattern offset Range 1 8000 0x0 13 5 7 5 Pattern Stride Register PAT_STRIDE_REG R W Address 0xFA00_0510 PAT_STRIDE_REG Bit Description Initial State Reserved 31 16 Reserved 0x0 PatStride 15 0 Pattern stride 2 s complement value 0x0 ...

Page 1792: ...itial State MaskAddr 31 0 Base address of the mask image 0x0 13 5 8 2 Mask Stride Register MASK_STRIDE_REG R W Address 0xFA00_0524 MASK_STRIDE_REG Bit Description Initial State Reserved 31 16 Reserved 0x0 MaskStride 15 0 Mask stride 2 s complement value 0x0 NOTE MaskLeftX MaskTopY MaskRightX and MaskBottomY are same as source image FIMG 2D V3 0 supports only 1bpp mask image format ...

Page 1793: ...tTopY CWTopY CWBottomY 0x0 Reserved 15 13 Reserved 0x0 CWLeftX 12 0 Left X Coordinate of Clipping Window Requirement DstLeftX CWLeftX CWRightX 0x0 13 5 9 2 RightBottom Clipping Window Register CW_RB_REG R W Address 0xFA00_0604 CW_RB_REG Bit Description Initial State Reserved 31 29 Reserved 0x0 CWBottomY 28 16 Bottom Y Clipping Window Requirement CWBottomY DstBottomY 0x0 Reserved 15 13 Reserved 0x0...

Page 1794: ...eserved 3 2 Reserved UnmaskedSelect 1 0 2 00 Pattern 2 01 Foreground color 2 10 Background color Others Reserved 0x0 13 5 10 2 Raster Operation Register ROP4_REG R W Address 0xFA00_0614 ROP4_REG Bit Description Initial State Reserved 31 16 Reserved 0x0 MaskedROP3 15 8 Raster Operation Value 0x0 UnmaskedROP3 7 0 Raster Operation Value 0x0 13 5 10 3 Alpha Register ALPHA_REG R W Address 0xFA00_0618 A...

Page 1795: ...lor format BG_COLOR_REG Bit Description Initial State BackgroundColor 31 0 Background Color Value The alpha field of the background color will be discarded 0x0 13 5 11 3 BlueScreen Color Register BS_COLOR_REG R W Address 0xFA00_0708 The color format of the bluescreen color is generally the same as the source color format But if the source color is selected as the foreground color or the background...

Page 1796: ...On for G value 0x0 Reserved 3 1 Reserved SrcStencilOnB 0 0 Stencil Test Off for B value 1 Stencil Test On for B value 0x0 13 5 12 2 Source Colorkey Decision Reference Minimum Register SRC_COLORKEY _DR_MIN_REG R W Address 0xFA00_0714 The color format of source colorkey decision reference register is generally the same as the source color format But if the source color is selected as the foreground ...

Page 1797: ... MAX value 0xFF SrcDRMaxR 23 16 Red DR MAX value 0xFF SrcDRMaxG 15 8 Green DR MAX value 0xFF SrcDRMaxB 7 0 Blue DR MAX value 0xFF 13 5 12 4 Destination Colorkey Control Register DST_COLORKEY_CTRL_REG R W Address 0xFA00_071C DST_COLORKEY_ CTRL_REG Bit Description Initial State Reserved 31 17 Reserved 0x0 DstStencilInv 16 0 Normal stencil test 1 Inversed stencil test 0x0 Reserved 15 13 Reserved DstS...

Page 1798: ...Section 10 AUDIO ETC ...

Page 1799: ... Master Slave Mode 2 3 2 5 Audio Serial Data Format 2 8 2 5 1 IIS bus Format 2 8 2 5 2 MSB Left Justified 2 8 2 5 3 LSB Right Justified 2 9 2 6 PCM BIT Length BLC RFS Divider and BFS Divider for Sampling Frequency iISlrclk SERIAL bitCLK iiSSclk and ROOt Clock RCLK 2 10 2 6 1 PCM Word Length and BFS Divider 2 10 2 6 2 BFS Divider and RFS Divider 2 10 2 6 3 RFS Divider and ROOT CLock 2 11 2 7 Progra...

Page 1800: ...3 4 AC link Digital Interface Protocol 4 5 4 3 5 AC link Input Frame SDATA_IN 4 7 4 3 6 AC97 Power down 4 9 4 4 I O Description 4 12 4 5 Register Description 4 13 4 5 1 Register Map 4 13 5 PCM Audio Interface 5 1 5 1 Overview of PCM Audio Interface 5 1 5 2 Key Features of PCM Audio Interface 5 1 5 3 PCM Audio Interface 5 2 5 4 PCM Timing 5 3 5 5 I O Description 5 5 5 6 Register Description 5 6 5 6...

Page 1801: ...D Conversion Time 7 4 7 4 2 Touch Screen Interface Mode 7 4 7 4 3 Standby Mode 7 6 7 4 4 Two Touch Screen Interfaces 7 6 7 5 ADC Touch Screen Interface Input Clock Diagram 7 8 7 6 I O Descriptions 7 9 7 7 Register Description 7 10 7 7 1 Register Map 7 10 8 KEYPAD Interface 8 1 8 1 Overview of Keypad Interface 8 1 8 2 Debouncing Filter 8 3 8 3 Filter Clock 8 4 8 4 Wakeup Source 8 4 8 5 Keypad Scann...

Page 1802: ...C 10 24 bits channel 3 13 Figure 4 1 AC97 Block Diagram 4 2 Figure 4 2 Internal Data Path 4 3 Figure 4 3 AC97 Operation Flow Chart 4 4 Figure 4 4 Bi directional AC link Frame with Slot Assignments 4 5 Figure 4 5 AC link Output Frame 4 6 Figure 4 6 AC link Input Frame 4 8 Figure 4 7 AC97 Power down Timing 4 9 Figure 4 8 AC97 Power down Power up Flow 4 10 Figure 4 9 AC97 State Diagram 4 11 Figure 5 ...

Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...

Page 1804: ...llowed BFS Value as BLC 2 10 Table 2 3 Allowed RFS Value as BFS 2 10 Table 2 4 Root Clock Table MHz 2 11 Table 3 1 Allowed BFS Value as BLC 3 6 Table 3 2 Allowed RFS Value as BFS 3 6 Table 3 3 Root Clock Table MHz 3 7 Table 4 1 Input Slot 1 Bit Definitions 4 7 Table 6 1 Burst Preamble Words 6 6 Table 8 1 Keypad interface I O Description 8 9 ...

Page 1805: ... port and 214KB SRAM Combined with low power scheme the S5PC110 is designed to play audio with extremely low power 1 2 KEY FEATURES OF AUDIO SUBSYSTEM The key features of audio subsystem include Renders low power music play Small and adequate for audio application RP Supports various audio codecs Contains I2S including AHB master port to get data from subsystem internal SRAM Contains totally 214KB...

Page 1806: ... Specifies LR channel clock input Xi2s0LRCLK Dedicated Xi2s0CDCLK I O Specifies codec clock out Xi2s0CDCLK Dedicated Xi2s0SDI I Specifies I2S serial data input Xi2s0SDI Dedicated Xi2s0SDO0 O Specifies I2S serial data out 0 Xi2s0SDO0 Dedicated Xi2s0SDO1 O Specifies I2S serial data out 1 Xi2s0SDO1 Dedicated Xi2s0SDO2 O Specifies I2S serial data out 2 Xi2s0SDO2 Dedicated ...

Page 1807: ... which is selected by OM 0 XXTI EPLL and I2SCDCLK0 can be supplied to the audio subsystem when the audio system is on and TOP S5PC110 is off The internal RP uses big endian scheme while the external audio subsystem uses little endian scheme Therefore endian converters are used to convert data ordering without using ARM or RP Audio subsystem comprises of I2S V5 1 and its own interrupt and DMA REQ A...

Page 1808: ...64KB and DMEM 96KB IBUF_0 IBUF_1 Specifies input buffers 0 and 1 18KB is allocated for each input buffers in RP These buffers are used by external audio subsystem as data reservoir There are Endian Converters ECs besides IBUF_0 and IBUF_1 OBUF_0 OBUF_1 Specifies output buffers 0 and 1 9KB is allocated for each output buffers in RP These buffers can be used by external audio subsystem as data reser...

Page 1809: ...CLK CON ASS CLK CON specifies the clock controller for audio subsystem It also provides clock for modules in the audio subsystem Figure 1 3 Clock Controller in Audio Subsystem CLKMUX_ASS can be changed at any time However it should stop running before MUXI2S_A is changed The value of divider can also be changed at any time 1 5 3 COMMBOX COMMBOX specifies the communication box It denotes the SFR co...

Page 1810: ...erations is complete After CPU wakes up CPU prepares generates and saves the next audio data to be played in SRAM at audio subsystem Then CPU is powered off again to save power For more information refer to the I2S_V51 User s Manual 1 5 5 SRAM The total memory size in audio subsystem is 214KB SRAM out of which 64KB is reserved for IMEM 96KB is reserved for DMEM 36KB is reserved for IBUF0 and IBUF1...

Page 1811: ...ED0_0000 0xEED0_23FC R W For RP output buffer 1 For external audio subsystem 9KB SRAM Audio Subsystem CLK CON ASS CLK SRC 0xEEE1_0000 R W Specifies the clock source select register 0x0 ASS CLK DIV 0xEEE1_0004 R W Specifies the clock divider register 0x0 ASS CLK GATE 0xEEE1_0008 R W Specifies the clock gate register 0x7f Commbox ASS_INTR 0xEEE2_0000 R W Specifies the interrupt from audio subsystem ...

Page 1812: ...s an SFR that can be freely used in the application 0x0 SW_DEFINE09 0xEEE2_011C R W Specifies an SFR that can be freely used in the application 0x0 SW_DEFINE10 0xEEE2_0120 R W Specifies an SFR that can be freely used in the application 0x0 SW_DEFINE11 0xEEE2_0124 R W Specifies an SFR that can be freely used in the application 0x0 SW_DEFINE12 0xEEE2_0128 R W Specifies an SFR that can be freely used...

Page 1813: ...MUXI2S_A 3 2 10 SCLK_AUDIO0 01 IISCDCLK0 from PAD 00 Main CLK 0 Reserved 1 This bit must be set as 0 0 CLKMUX_ASS 0 1 FOUT_EPLL 0 XXTI 0 1 6 2 2 Audio Subsystem Clock Divider Register Audio Subsystem CLK DIV R W Address 0xEEE1_0004 AUDIO SUBSYSTEM CLK DIV Bit Description Initial State Reserved 31 8 Reserved 0 I2S_A_RATIO 7 4 Specifies the I2S_A clock divider ratio I2SCLK MOUTI2S_A I2S_A_RATIO 1 0 ...

Page 1814: ...S 5 Specifies the gating AUDIO BUS CLK to I2S 0 mask 1 pass 1 AUDIO_BUS_CLK_ UART 4 Specifies the gating AUDIO BUS CLK to UART 0 mask 1 pass 1 AUDIO_BUS_CLK_ HWA 3 Specifies the gating AUDIO BUS CLK to HWA 0 mask 1 pass 1 AUDIO_BUS_CLK_ DMA 2 Specifies the gating AUDIO BUS CLK to DMA 0 mask 1 pass 1 AUDIO_BUS_CLK_ BUF 1 Specifies the gating AUDIO BUS CLK to BUF IBUF0 1 OBUF0 1 0 mask 1 pass 1 AUDI...

Page 1815: ...cifies the instruction code start address for external booting 0 1 6 3 3 Reset Register RESET R W Address 0xEEE2_0100 RESET Bit Description Initial State Reserved 31 1 Reserved 0 Reset 0 1 No action 0 Resets and returns to 1 after two clock cycles 1 1 6 3 4 RP Pending Register RP_PENDING R W Address 0xEEE2_0104 RP_PENDING Bit Description Initial State Reserved 31 1 Reserved 0 Pending 0 1 RP pendin...

Page 1816: ...ep power mode PAD_PDN_CTRL Bit Description Initial State Reserved 31 9 Reserved 0 SDO_PDN 2 8 Configure output value of I2S0 SDO 2 PAD 0 Output 0 1 Output 1 0 SDO_PDN 1 7 Configure output value of I2S0 SDO 1 PAD 0 Output 0 1 Output 1 0 SDO_PDN 0 6 Configure output value of I2S0 SDO 0 PAD 0 Output 0 1 Output 1 0 SCLKO_PDN 5 Configure output value of I2S0 SCLK PAD 0 Output 0 1 Output 1 0 CDCLKO_PDN ...

Page 1817: ...ndian converter 1 Specifies the endian converter for IBUF1 write path 1 Big endian 0 Little endian 0 Endian converter 0 Specifies the endian converter for IBUF0 write path 1 Big endian 0 Little endian 0 There are endian converters between external and internal audio subsystems refer to Figure 1 1 To set them AUDIO_ENDIAN SFR at Clock Management Unit CMU is used ENDIAN converters setting guide Regi...

Page 1818: ...t and receive samples can be supported IIS specific clock can be supplied from internal system clock controller through IIS clock divider or direct clock source IIS V5 1 can handle up to 2 sound sources For example OS Operating Sound controlled sound can be delivered to primary sound path and OS independent sound can be delivered to secondary sound path IIS V5 1 can mix primary sound source and se...

Page 1819: ...S5PC110_UM 2 IIS MULTI AUDIO INTERFACE 2 2 2 3 BLOCK DIAGRAM OF IIS MULTI AUDIO INTERFACE Figure 2 1 IIS Bus Block Diagram ...

Page 1820: ...and I2SSCLK If IIS bus interface transmits I2SLRCLK and I2SSCLK to IIS codec IIS bus is master mode If IIS bus interface receives I2SLRCLK and I2SSCLK from IIS codec IIS bus is slave mode To select master or slave mode set MSS bit of IISMOD register TX RX mode indicates the direction of data flow If IIS bus interface transmits data to IIS codec this indicates TX mode Conversely IIS bus interface r...

Page 1821: ...scaler clock divider is employed to generate a root clock with divided frequency from source clock In master mode the root clock is divided to generate I2SSCLK and I2SLRCLK In slave mode this clock is not used to generate I2SSCLK and I2SLRCLK CDCLKCON controls direction of CDCLK GPIO pad The direction is set by CDCLKCON SFR bit IISMOD 12 When CDCLKCON SRF bit is 0 auxiliary clock out is supported ...

Page 1822: ... mode x slave XXTI Don t care x OP_CLK RCLKSRC I2SCLK ASS_CLK_CON ASS_CLK_CON AudioBusCLK I2SCLK ASS_CLK_CON AudioBusCLK I2SCLK SCLK LRCLK SCLK LRCLK SCLK LRCLK SCLK LRCLK SCLK LRCLK OP_CLK RCLKSRC OP_CLK RCLKSRC External clock Figure 2 4 Master Slave Modes of IIS Table 2 1 Typical Usage of Master Slave Modes AudioSS CLK_CON IIS v5 1 IISMOD Mode AudioBusClk I2SCLK MSS RCLKSRC OP_CLK CDCLKCON Slave...

Page 1823: ...te operation should be performed Reference DMA request point TX mode FIFO is not full TXDMACTIVE is active RX mode FIFO is not empty RXDMACTIVE is active 2 4 1 2 Internal DMA Transfer To transfer up to 2 channel secondary sound to IIS use internal DMA or SFR interface To play secondary sound for 2 channels internal DMA in IIS gets sound data from address range between 0xC000_0000 and 0xC01F_FFFF w...

Page 1824: ...ayer Volume 1 Volume N S W Mixer Master Volume Volume X Master Volume H W Mixer I2S Figure 2 5 Concept of Mixer in IIS This function has two limitations 1 Normalization should be pre processed in S W configurations or settings 2 Synchronization between two sound sources is not guaranteed ...

Page 1825: ...ge of the clock signal The LR channel select line indicates the direction of left or right channel being transmitted I2SLRCLK may be changed either on a trailing or leading edge of the serial clock but it does not need to be symmetrical In the slave this signal is latched on the leading edge of the clock signal The I2SLRCLK line changes one clock period before the MSB is transmitted This allows th...

Page 1826: ...igure the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK BFS is 48 fs where fs is sampling frequency I2SLRCLK frequency SCLK LRCLK Left Right SD I2S Format N 8 or 16 SCLK LRCLK Left Right SD MSB Justified Left Justified Format N 8 or 16 SCLK LRCLK Left Right SD LSB Justified Right Justified Format N 8 or 16 MSB 1st 2nd Bit N 1th Bit MSB 1st 2nd Bit N 1th Bit MSB 1st ...

Page 1827: ...clock is not IISEXTCDCLK In slave mode you must set the value of BLC BFS and RFS similar to master ex Codec Because IIS interface controller needs these value for correct operation 2 6 1 PCM WORD LENGTH AND BFS DIVIDER PCM Word Length BLC value is selected first because the value affects BFS value Table 2 2 shows BFS available value as BLC Table 2 2 Allowed BFS Value as BLC PCM Bit length BLC 8 bi...

Page 1828: ... 025 kHz 16 000 kHz 22 050 kHz 32 000 kHz 44 100 kHz 48 000 kHz 64 000 kHz 88 200 kHz 96 000 kHz 256fs 2 0480 2 8224 4 0960 5 6448 8 1920 11 2896 12 2880 16 3840 22 5792 24 5760 384fs 3 0720 4 2336 6 1440 8 4672 12 2880 16 9344 18 4320 24 5760 33 8688 36 8640 512fs 4 0960 5 6448 8 1920 11 2896 16 3840 22 5792 24 5760 32 7680 45 1584 49 1520 768fs 6 1440 8 4672 12 2880 16 9344 24 5760 33 8688 36 86...

Page 1829: ...fer Master Slave chapter 2 Configure I2SMOD register and I2SPSR IIS pre scaler register 3 To operate system in stability the internal TXFIFO should be almost full before transmission To satisfy this start TXDMA before asserting I2SACTIVE 4 Basically IIS bus does not support the interrupt Therefore you can only check state by polling through accessing SFR 5 If TXFIFO is full you can assert I2SACTIV...

Page 1830: ...Audio bus clock and CDCLK are coming correctly to the IIS controller and FLUSH the TX FIFO using the TFLUSH bit in the I2SFIC Register IIS FIFO Control Register Please ensure that IIS Controller is configured in one of the following modes TX only mode TX RX simultaneous mode This can be done by programming the TXR bit in the I2SMOD Register IIS Mode Register 1 Then Program the following parameters...

Page 1831: ...8 bit channel or 16 bit channel BLC as shown in the Figure 2 7 0 15 16 31 LOC 0 7 BLC 00 BLC 01 Right Channel Left Channel LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 23 BLC 00 BLC 01 Figure 2 7 TX FIFO Structure for BLC 00 or BLC 01 ...

Page 1832: ...in the I2SCON Register IIS Control Register The data is then serially shifted out with respect to the bit clock SCLK and word select clock LRCLK The TXCHPAUSE in the I2SCON Register IIS Control Register can stop the serial data transmission on the I2SSDO The transmission is stopped once the current Left Right channel is transmitted If the control registers in the I2SCON Register IIS Control Regist...

Page 1833: ...ed in any of the modes Receive only Receive Transmit simultaneous mode This can be done by Programming the TXR bit in the I2SMOD Register IIS Mode Register 1 Then Program the following parameters according to the need MSS RCLKSRC SDF BFS BLC LRP For Programming the above mentioned fields please refer I2SMOD Register IIS Mode Register 2 Once ensured that the input clocks for IIS controller are up a...

Page 1834: ...ERFACE 2 17 0 15 16 31 LOC 0 7 BLC 00 BLC 01 Right Channel Left Channel LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 23 BLC 00 BLC 01 Figure 2 9 RX FIFO Structure for BLC 00 or BLC 01 ...

Page 1835: ...t Channel Right Channel Figure 2 10 RX FIF0 Structure for BLC 10 24 bit channel The RXCHPAUSE in the I2SCON register can stop the serial data reception on the I2SSDI The reception is stopped once the current Left Right channel is received If the control registers in the I2SCON Register IIS Control Register and I2SMOD Register IIS Mode Register are to be reprogrammed then it is advisable to disable...

Page 1836: ...0LRCLK I O IIS LR channel clock Xi2s0LRCLK Dedicated Xi2s0CDCLK I O Auxiliary clock out for codec chip IIS external clock input Xi2s0CDCLK Dedicated Xi2s0SDI I IIS serial data input Xi2s0SDI Dedicated Xi2s0SDO0 O IIS serial data out 0 Xi2s0SDO0 Dedicated Xi2s0SDO1 O IIS serial data out 1 Xi2s0SDO1 Dedicated Xi2s0SDO2 O IIS serial data out 2 Xi2s0SDO2 Dedicated ...

Page 1837: ...S 0xEEE3_001C W Specifies the IIS interface secondary transmit data register 0x0 IISAHB 0xEEE3_0020 R W Specifies the IIS AHB DMA control register 0x0 IISSTR0 0xEEE3_0024 R W Specifies the IIS AHB DMA start address0 register 0x0 IISSIZE 0xEEE3_0028 R W Specifies the IIS AHB DMA size register 0x7FFF_0000 IISTRNCNT 0xEEE3_002C R Specifies the IIS AHB DMA transfer count register 0x0 IISLVL0ADDR 0xEEE...

Page 1838: ...occur 1 Interrupt occurs R W 0 FTXSURINTEN 23 Secondary TX FIFO_S Under run Interrupt Enable 0 TXFIFO_S Under run INT disable 1 TXFIFO_S Under run INT enable R W 0 FTXSEMPT 22 Secondary TX FIFO_S empty Status Indication 0 TX FIFO_S is not empty Ready to transmit Data 1 TX FIFO_S is empty Not Ready to transmit Data R 0 FTXSFULL 21 Secondary TX FIFO_S full Status Indication 0 TX FIFO_S is not full 1...

Page 1839: ... Status Indication 0 TX FIFO1 is not full 1 TX FIFO1 is full R 0 LRI 11 Left Right channel clock indication Note that LRI meaning is dependent on the value of LRP bit of I2SMOD register 0 Left when LRP bit is low or right when LRP bit is high 1 Right when LRP bit is low or left when LRP bit is high R 0 FTX0EMPT 10 Primary Tx FIFO0 empty status indication 0 FIFO is not empty ready for transmit data...

Page 1840: ...FOx and TX_S FIFO 1 Pause operation for TX FIFOx an TX_S FIFO R W 0 RXCHPAUSE 3 Rx channel operation pause command Note that when this bit is activated the channel operation will be halted after left right channel data transfer is completed 0 No pause operation 1 Pause operation R W 0 TXDMACTIVE 2 Tx DMA active for primary TX FIFOx start DMA request Note that when this bit is set from high to low ...

Page 1841: ...Bit Length Control Bit which decides transmission of 8 16 24 bits per audio channel for Secondary TX FIFO_S 00 16 Bits per channel 01 8 Bits Per Channel 10 24 Bits Per Channel 11 Reserved R W 00 BLC_P 25 24 Bit Length Control Bit Which decides transmission of 8 16 24 bits per audio channel for Primary TX FIFOx 00 16 Bits per channel 01 8 Bits Per Channel 10 24 Bits Per Channel 11 Reserved R W 00 R...

Page 1842: ... Slave mode R W 0 RCLKSRC 10 Select RCLK clock source 0 Using Audio bus clock 1 Using I2SCLK Refer to Figure 2 3 R W 0 TXR 9 8 Transmit or receive mode select 00 Transmit only mode 01 Receive only mode 10 Transmit and receive simultaneous mode 11 Reserved R W 00 LRP 7 Left Right channel clock polarity select 0 Low for left channel and high for right channel 1 High for left channel and low for righ...

Page 1843: ... 26 IISMOD Bit Description R W Initial State BFS 2 1 Bit clock frequency select 00 32 fs where fs is sampling frequency 01 48 fs 10 16 fs 11 24 fs Note Even in the slave mode this bit should be set for correct operation R W 00 Reserved 0 R 0 ...

Page 1844: ...flush command 0 No flush 1 Flush R W 0 FTX0CNT 14 8 Primary TX FIFO0 data count FIFO has 64 dept so value ranges from 0 to 64 N Data count N of FIFO R 0x00 RFLUSH 7 RX FIFO flush command 0 No flush 1 Flush R W 0 FRXCNT 6 0 RX FIFO data count FIFO has 64 dept so value ranges from 0 to 64 N Data count N of FIFO R 0x00 2 9 1 4 IIS Interface Clock Divider Control Register IISPSR R W Address 0xEEE3_000...

Page 1845: ...D R Address 0xEEE3_0014 IISRXD Bit Description R W Initial State IISRXD 31 0 RX FIFO read data Note that the left right channel data is allocated as the following bit fields R 31 16 L 15 0 when 16 bit BLC R 23 16 L 7 0 when 8 bit BLC Refer Figure 10 2 9 when 24 bit BLC R 0x00 2 9 1 7 IIS Interface TXFIFO_S Control Register IISFICS R W Address 0xEEE3_0018 IISFICS Bit Description R W Initial State R...

Page 1846: ...SLVL0EN 24 Enable buffer level 0 interrupt 0 Disables IISLVL0INT 1 Enables IISLVL0INT R W 0 IISLVL3INT 23 Buffer level 3 interrupt status flag During operation of DMA when generated address in DMA matches with IISLVL3ADDR this flag will be set To clear this flag use IISLVL3CLR field R 0 IISLVL2INT 22 Buffer level 2 interrupt status flag During operation of DMA when generated address in DMA matches...

Page 1847: ...oad IIS internal DMA Configuration when DMA operation is done and re start IIS internal DMA automatically 0 Disables auto reload function 1 Enables auto reload function Before switching to 0 from 1 s w must check if DMA_EN is set R W 0 IISINTMASK 3 Disables interrupt request signal 0 Enables interrupt request when DMA auto reload is on 1 Disables interrupt request when DMA auto reload is on After ...

Page 1848: ...check that IISDMAEN is in stable state R W 0 2 9 1 10 IIS AHB DMA Start Address0 Register IISSTR0 R W Address 0xEEE3_0024 IISSTR0 Bit Description R W Initial State IISSTR 31 0 Start address0 of IIS internal DMA operation When DMAEN is ON internal DMA in IIS will start DMA operation based on IISSTR0 address Internal DMA can handle word aligned address only but to get best performance IISSTR0 should...

Page 1849: ...nsferred data using IIS internal DMA word unit User program can terminate IIS internal DMA operation by turning DMA_EN off After DMA_EN is 0 user program reads IISTRNCNT value to know where IIS internal DMA stops R 2 9 1 14 IIS AHB DMA Level 0 Interrupt Address Register IISLVL0ADDR R W Address 0xEEE3_0030 IISLVL0ADDR Bit Description R W Initial State IISLVL0ADDR 31 10 AHB DMA level 0 interrupt add...

Page 1850: ...A operation when DMA working address is matched with IISLVL1ADDR IISDMAEN in IISAHB will be turned off automatically R W 0 2 9 1 16 IIS AHB DMA Level 2 Interrupt Address Register IISLVL2ADDR R W Address 0xEEE3_0038 IISLVL2ADDR Bit Description R W Initial State IISLVL2ADDR 31 10 AHB DMA level 2 interrupt address While IISLVL2EN in IISAHAB register is set AHB DMA is comparing this register to genera...

Page 1851: ...SLVL3EN in IISAHB register is set AHB DMA is comparing this register to generated address in DMA When two values match IISLVL3INT in IISAHB will be set Valid address range for IISLVL3ADDR is from 0xC000_0000 to 0xC01F_FFFF R 0x00 Reserved 9 1 R 0x00 IISLVL3STOP 0 Enables Precise stop 0 Do not stop DMA operation 1 Stop DMA operation when DMA working address is matched with IISLVL3ADDR IISDMAEN in I...

Page 1852: ...lexed data channels a word select line and a clock line IIS interface transmits or receives sound data from external stereo audio codec To transmit and receive data two 32x64 FIFOs First In First Out data structures are included and DMA transfer mode to transmit and receive samples can be supported IIS specific clock can be supplied from internal system clock controller through IIS clock divider o...

Page 1853: ...M OF IIS BUS INTERFACE TxR Channel Control TxDMA FSM RxDMA FSM Clock Control Tx Shift Register Rx Shift Register TxFIFO RxFIFO TxDREQ TxDACK System Bus RxDREQ RxDACK I2SSCLK I2SLRCLK I2SSDO I2SSDI I2SCDCLK Register File Figure 3 1 IIS Bus Block Diagram ...

Page 1854: ...2SSCLK and I2SLRCLK are supplied from the pin GPIOs in slave mode That is whatever source clock is Only Master can generate I2SLRCLK and I2SSCLK Master Slave mode is different compared to TX RX Master Slave mode presents the direction of I2SLRCLK and I2SSCLK The direction of I2SCDCLK This is only auxiliary is not important If IIS bus interface transmits clock signals to IIS codec IIS bus is master...

Page 1855: ...in 2 s complement with the MSB first with a fixed position whereas the position of the LSB depends on the word length The transmitter sends the MSB of the next word at one clock period after the I2SLRCLK is changed Serial data sent by the transmitter can be synchronized either with the trailing or with the leading edge of the clock signal However the serial data must be latched into the receiver o...

Page 1856: ...e the word length is 16 bit and I2SLRCLK makes transition every 24 cycle of I2SSCLK BFS is 48 fs where fs is sampling frequency I2SLRCLK frequency SCLK LRCLK LEFT RIGHT SD I 2 S Format N 8 or 16 SCLK LRCLK LEFT RIGHT SD MSB Justified Left Justified Format N 8 or 16 SCLK LRCLK LEFT RIGH T SD LSB Justified Right Justified Format N 8 or 16 MSB 1st 2nd Bit N 1th Bit MSB 1st 2nd Bit N 1th Bit MSB 1st 2...

Page 1857: ...ou must set the value of BLC BFS and RFS similar to master ex Codec Because IIS interface controller needs these value for correct operation 3 4 4 PCM WORD LENGTH AND BFS DIVIDER PCM Word Length BLC setting should be preceded before setting the BFS value Table 3 1 shows BFS available value as BLC Table 3 1 Allowed BFS Value as BLC PCM Bit length BLC 8bit 16bit 24bit Available BFS value 16fs 24fs 3...

Page 1858: ...z 11 025 kHz 16 000 kHz 22 050 kHz 32 000 kHz 44 100 kHz 48 000 kHz 64 000 kHz 88 200 kHz 96 000 kHz 256fs 2 0480 2 8224 4 0960 5 6448 8 1920 11 2896 12 2880 16 3840 22 5792 24 5760 384fs 3 0720 4 2336 6 1440 8 4672 12 2880 16 9344 18 4320 24 5760 33 8688 36 8640 512fs 4 0960 5 6448 8 1920 11 2896 16 3840 22 5792 24 5760 32 7680 45 1584 49 1520 768fs 6 1440 8 4672 12 2880 16 9344 24 5760 33 8688 3...

Page 1859: ...onfigure I2SMOD register and I2SPSR IIS pre scaler register 3 To operate system in stability the internal TXFIFO should be almost full before transmission For TXFIFO to be almost full start DMA operation 4 IIS bus does not support the interrupt Therefore you can only check state by polling through accessing SFR 5 After TXFIFO is full then I2SACTIVE must be asserted 3 5 3 RECORDING MODE RX MODE WIT...

Page 1860: ... 64X32 bit wide FIFO where the processor or DMA can write upto 16 left right data samples After enabling the channel for transmission An Example sequence is as follows Ensure the PCLK and CDCLK are coming correctly to the I2S controller and FLUSH the TX FIFO using the TFLUSH bit in the Please ensure that I2S Controller is configured in one of the following modes TX only mode TX RX simultaneous mod...

Page 1861: ...2SCON Register I2S Control Register The data is then serially shifted out with respect to the serial bit clock SCLK and word select clock LRCLK The TXCHPAUSE in the I2SCON Register I2S Control Register can stop the serial data transmission on the I2SSDO The transmission is stopped once the current Left Right channel is transmitted If the control registers in the I2SCON Register I2S Control Registe...

Page 1862: ...rol Register and the I2S controller is configured in any of the modes Receive only Receive Transmit simultaneous mode This can be done by Programming the TXR bit in the I2SMOD Register I2S Mode Register 1 Then Program the following parameters according to the need MMS RCLKSRC SDF BFS BLC LRP For Programming the above mentioned fields please refer I2SMOD Register I2S Mode Register 2 Once ensured th...

Page 1863: ... INTERFACE 3 12 0 15 16 31 LOC 0 7 BLC 00 BLC 01 RIGHT CHANNEL LEFT CHANNEL LOC 1 LOC 2 LOC 3 LOC 4 LOC 5 LOC 6 LOC 7 LOC 8 LOC 9 LOC 10 LOC 11 LOC 12 LOC 13 LOC 14 LOC 15 Figure 3 6 RX FIFO Structure for BLC 00 or BLC 01 ...

Page 1864: ...Channel Right Channel Figure 3 7 RX FIF0 Structure for BLC 10 24 bits channel The RXCHPAUSE in the I2SCON register can stop the serial data reception on the I2SSDI The reception is stopped once the current Left Right channel is received If the control registers in the I2SCON Register I2S Control Register and I2SMOD Register I2S Mode Register are to be reprogrammed then it is advisable to disable t...

Page 1865: ...ation refer to the GPIO chapter of this manual for proper GPIO setting PAD Name I O Description Pad Type Xi2s1CDCLK Xpcm2EXTCLK I O I2S Codec clock input output dedicated Xi2s1SCLK Xpcm2SCLK I O I2S Bit clock input output dedicated Xi2s1LRCK Xpcm2FSYNC I O I2S LR channel clock input output dedicated Xi2s1SDI Xpcm2SIN I I2S serial data input dedicated Xi2s1SDO Xpcm2SOUT O I2S serial data out dedica...

Page 1866: ...he IIS interface transmit data register 0x0 IISRXD 0xE210_0014 R Specifies the IIS interface receive data register 0x0 I2S2 IISCON 0xE2A0_0000 R W Specifies the IIS interface control register 0xE00 IISMOD 0xE2A0_0004 R W Specifies the IIS interface mode register 0x0 IISFIC 0xE2A0_0008 R W Specifies the IIS interface FIFO control register 0x0 IISPSR 0xE2A0_000C R W Specifies the IIS interface clock...

Page 1867: ...e occurred 1 Interrupt was occurred R W 1 b0 FTXURINTEN 16 TX FIFO Under run Interrupt Enable 0 TXFIFO Under run INT disable 1 TXFIFO Under run INT enable R W 1 b0 Reserved 15 12 Reserved Program to zero R W 4 b0 LRI 11 Left Right channel clock indication Note that LRI meaning is dependent on the value of LRP bit of I2SMOD register 0 Left when LRP bit is low or right when LRP bit is high 1 Right w...

Page 1868: ...vated at any time the channel operation will be halted after left right channel data transfer is completed 0 No pause operation 1 Pause operation R W 1 b0 RXCHPAUSE 3 Rx channel operation pause command Note that when this bit is activated at any time the channel operation will be halted after left right channel data transfer is completed 0 No pause operation 1 Pause operation R W 1 b0 TXDMACTIVE 2...

Page 1869: ...0 MSS 11 IIS master or slave mode select 0 Master mode 1 Slave mode R W 1 b0 RCLKSRC 10 Select RCLK clock source 0 PCLK is internal source clock for IIS 1 SCLK_AUDIO SCLK_AUDIO1 for I2S1 SCLK_AUDIO2 for I2S2 Refer to Figure 3 2 R W 1 b0 TXR 9 8 Transmit or receive mode select 00 Transmit only mode 01 Receive only mode 10 Transmit and receive simultaneous mode 11 Reserved R W 2 b00 LRP 7 Left Right...

Page 1870: ... BUS INTERFACE 3 19 IISMOD Bit Description R W Initial State BFS 2 1 Bit clock frequency select 00 32 fs where fs is sampling frequency 01 48 fs 10 16 fs 11 24 fs R W 2 b00 Reserved 0 Reserved Program to zero R W 1 b0 ...

Page 1871: ...7 RX FIFO flush command 0 No flush 1 Flush R W 1 b0 FRXCNT 6 0 RX FIFO data count FIFO has 64 dept so value ranges from 0 to 64 N Data count N of FIFO R 7 b0 3 7 1 4 IIS BUS Interface Special Registers IISPSR IISPSR R W Address 0xE210_000C IISPSR R W Address 0xE2A0_000C IISPSR Bit Description R W Initial State Reserved 31 16 Reserved Program to zero R W 16 b0 PSRAEN 15 Pre scaler Clock divider A a...

Page 1872: ...annel data is allocated as the following bit fields R 31 16 L 15 0 when 16 bit BLC R 23 16 L 7 0 when 8 bit BLC W 32 b0 3 7 1 6 IIS BUS Interface Special Registers IISRXD IISRXD R Address 0xE210_0014 IISRXD R Address 0xE2A0_0014 IISRXD Bit Description R W Initial State IISRXD 31 0 RX FIFO read data Note that the left right channel data is allocated as the following bit fields R 31 16 L 15 0 when 1...

Page 1873: ...le to an analog audio waveform Controller receives the stereo PCM data and the mono Mic data from Codec then store in memories This chapter describes the programming model for the AC97 Controller Unit The prerequisite in this chapter requires an understanding of the AC97 revision 2 0 specifications 4 2 KEY FEATURES OF AC97 CONTROLLER The AC97 Controller includes the following features Independent ...

Page 1874: ...s the functional block diagram of S5PC110 AC97 Controller The AC97 signals from the AC link which is a point to point synchronous serial inter connecting that supports full duplex data transfers All digital audio streams and command status information are communicated via AC link APB I F DMA Eng in e Interrupt Control MIC in FIFO PCM ou t FIFO PCM in FIFO SFR AC link I F FSM Control APB AC link Fi...

Page 1875: ... consist of 16 bit and 16 entries buffer It also has 20 bit I O shift register via AC link Command Addr Register Command Data Register PCM Out Buffer Regfile 16 bit x 2 x 16 Entry PWDATA Response Data Register Mic In Buffer RegFile 16 bit x16 Entry PCM In Buffer Regfile 16 bit x 2 x 16 Entry PRDATA Input Shift Register 20 bit Output Shift Register 20 bit SDATA_IN SDATA_OUT AC Link APB Figure 4 2 I...

Page 1876: ...terrupt When interrupt occurs you must de assert codec ready interrupt Use DMA or PIO directly to write data to register to transmit data from memory to register or from register to memory If internal FIFOs TX FIFO or RX FIFO are not empty then let data be transmitted System reset or Cold reset Set GPIO and Release INTMSK SUBINTMSK bits Enable Codec Ready interrupt Codec Ready interrupt Time out c...

Page 1877: ...for all data transaction on the AC link A data transaction is made up of 256 bits of information broken into groups of 13 time slots and is called a frame Time slot 0 is called the Tag Phase and it is 16 bits long The other 12 time slots are called the Data Phase The Tag Phase contains one bit that identifies a valid frame and 12 bits that identify the time slots in the Data Phase that contain val...

Page 1878: ... slot 1 are configured to specify the index to the CODEC register Others are filled with 0 s reserved In slot 2 it configured with the data which is for writing because of output frame Slot 2 Command Data Port In slot 2 this is the write data with 16 bit resolution 19 4 is valid data Slot 3 PCM Playback Left channel Slot 3 is audio output frame is the composite digital audio left stream If a sampl...

Page 1879: ...ued during the most recent read command For multiple sample rate output the CODEC examines its sample rate control registers its FIFOs states and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active low SLOTREQ bits asserted during the current audio input frame indicate which output slots require data from the controller in the n...

Page 1880: ... less than 16 bits the AC97 Codec fills all training non valid bit positions in the slot with zeroes Slot 4 PCM Record Right channel Slot 4 which is audio input frame is the right channel audio output of the AC97 Codec If a sample has a resolution that is less than 16 bits the AC97 Codec fills all training non valid bit positions in the slot with zeroes Slot 6 Microphone Record Data The AC97 Contr...

Page 1881: ...logic low voltage level The sequence follows the timing diagram as shown in Figure 4 7 The AC97 Controller transmits the write to Power down register 0x26 via AC link Set up the AC97 Controller so that it does not transmit data to slots 3 12 when it writes to the Power down register bit PR4 data 0x1000 and it does not require the Codec to process other data when it receives a power down request Wh...

Page 1882: ...alog off PR2 or PR3 Digitial I F off PR4 Shut off AC link Default PR0 1 PR1 1 PR2 1 PR4 1 Warm Reset PR2 0 ANL 1 PR1 0 DAC 1 PR0 0 ADC 1 Cold Reset Ready 1 Figure 4 8 AC97 Power down Power up Flow 4 3 6 3 Cold AC97 Reset A cold reset is generated when the nRESET pin is asserted through the AC_GLBCTRL Asserting and deasserting nRESET activates BITCLK and SDATA_OUT All AC97 control registers are ini...

Page 1883: ... TRANS_DATA POWER_DOWN WARM_RESET ACLINK_ON 5 CODEC_WAKEUP 5 4 3 6 8 7 6 7 8 2 3 4 9 9 9 9 9 9 COLD_RESET PRESETn Figure 4 9 AC97 State Diagram Figure 4 9 shows the state diagram of AC97 controller It is useful to check AC97 controller state machine State machine shown in above figure is synchronized by peripheral clock PCLK Use AC_GLBSTAT register to monitor state ...

Page 1884: ...rmation refer to the GPIO chapter of this manual for exact GPIO setting Signal I O Description Pad Type AC_nRESET O Active low CODEC reset Xi2s1CDCLK muxed AC_BIT_CLK I 12 288MHz bit rate clock Xi2s1SCLK muxed AC_SYNC O 48 kHz frame indicator and synchronizer Xi2s1LRCK muxed AC_SDATA_OUT O Serial audio output data Xi2s1SDO muxed AC_SDATA_IN I Serial audio input data Xi2s1SDI muxed ...

Page 1885: ... W Specifies the AC97 Codec Command Register 0x00000000 AC_CODEC_STAT 0xE220_000C R Specifies the AC97 Codec Status Register 0x00000000 AC_PCMADDR 0xE220_0010 R Specifies the AC97 PCM Out In Channel FIFO Address Register 0x00000000 AC_MICADDR 0xE220_0014 R Specifies the AC97 MIC In Channel FIFO Address Register 0x00000000 AC_PCMDATA 0xE220_0018 R W Specifies the AC97 PCM Out In Channel FIFO Data R...

Page 1886: ... 0 PCM in channel threshold interrupt clear 25 1 Interrupt clear write only 0 MIC in channel threshold interrupt clear 24 1 Interrupt clear write only 0 23 Reserved 0 Codec ready interrupt enable 22 0 Disables 1 Enables 0 PCM out channel underrun interrupt enable 21 0 Disables 1 Enables FIFO is empty 0 PCM in channel overrun interrupt enable 20 0 Disables 1 Enables FIFO is full 0 Mic in channel ov...

Page 1887: ...rm reset 1 0 Normal 1 Wake up codec from power down 0 Cold reset 0 0 Normal 1 Reset Codec and Controller logic Notes 1 During Cold reset writing to any AC97 Registers is not affected 2 When recovering from Cold reset writing to any AC97 Registers is not affected Example For consecutive Cold reset and Warm reset first set AC_GLBCTRL 0x1 then set AC_GLBCTRL 0x0 After recovering from cold reset set A...

Page 1888: ...0 PCM out channel underrun interrupt 21 0 Not requested 1 Requested 0 PCM in channel overrun interrupt 20 0 Not requested 1 Requested 0 MIC in channel overrun interrupt 19 0 Not requested 1 Requested 0 PCM out channel threshold interrupt 18 0 Not requested 1 Requested 0 PCM in channel threshold interrupt 17 0 Not requested 1 Requested 0 MIC in channel threshold interrupt 16 0 Not requested 1 Reque...

Page 1889: ...en on the AC_CODDEC_CMD register it is recommended to have more than 1 48 kHz delay time between the command and the next command 4 5 1 4 AC97 Codec Status Register AC_CODEC_STAT R Address 0xE220_000C If the Read enable bit is 1 and Codec command address is valid Codec status data is also valid AC_CODEC_STAT Bit Description Initial State 31 23 Reserved 0x00 Address 22 16 Codec status address 0x00 ...

Page 1890: ...9 16 PCM in channel FIFO read address 0000 15 12 Reserved 0000 Out write address 11 8 PCM out channel FIFO write address 0000 7 4 Reserved 0000 In write address 3 0 PCM in channel FIFO write address 0000 4 5 1 6 AC97 MIC IN Channel FIFO Address Register AC_MICADDR R Address 0xE220_0014 To index the internal MIC in FIFO address AC_MICADDR Bit Description Initial State 31 20 Reserved 0000 Read addre...

Page 1891: ...in right channel FIFO data Read PCM in right channel Write PCM out right channel 0x0000 Left data 15 0 PCM out in left channel FIFO data Read PCM in left channel Write PCM out left channel 0x0000 4 5 1 8 AC97 MIC IN Channel FIFO Data Register AC_MICDATA R W Address 0xE220_001C This is MIC in channel FIFO data register AC_MICDATA Bit Description Initial State 31 16 Reserved 0x0000 Mono data 15 0 MI...

Page 1892: ...he PCM Audio interface includes the following features 16 bit PCM 3 ports audio interface Supports only master mode All PCM serial timings and strobes including the main shift clock are based on an PCM_EXTCLK OSC EPLL_FOUT or AUDIO_SCLK can be used as PCM_EXTCLK source clock Optional timing based on the internal APB PCLK Input 16 bit x 32depth and output 16 bit x 32depth FIFOs to buffer data Optio...

Page 1893: ...ovides the 16 bit data word to be serially shifted out This data is serially shifted out MSB first one bit per PCMSCLK The PCM serial output data PCMSOUT is clocked out using the rising edge of the PCMSCLK The MSB bit position relative to the PCMSYNC is programmable to either match the PCMSYNC or one PCMCLK later After all 16 bit have been shifted out to indicate the end of the transfer you can ge...

Page 1894: ...actual shift clock PCMSCLK is synchronized with the data Furthermore even if the PCMSCLK output is not used the skew will be significantly less than the period of the PCMCODEC_CLK and does not represent a problem since most PCM interfaces capture data on the falling edge of the clock Figure 5 1 shows a PCM transfer with the MSB configured to be coincident with the PCMSYNC This MSB positioning corr...

Page 1895: ...L register to be 1 PCMFSYNC PCMSOUT 15 14 1 0 dont care 15 output output output PCMSCLK input pcm_irq sync to DSP clk 15 14 1 0 dont care 15 input internal PCMSIN PCMCODEC_CLK datain_reg_valid Figure 5 2 PCM timing POS_MSB_WR RD 1 Figure 5 3 Input Clock Diagram for PCM S5PC110 PCM can select clock either PCLK or External Clock Refer Figure 5 3 To enable clock gating please refer to the SYSCON part...

Page 1896: ...ter of this manual for proper GPIO setting PAD Name I O Description Pad Type Xi2s0CDCLK Xi2s1CDCLK Xpcm0EXTCLK I O PCM Codec clock input output dedicated Xi2s0SCLK Xi2s1SCLK Xpcm0SCLK I O PCM Bit clock input output dedicated Xi2s0LRCK Xi2s1LRCK Xpcm0FSYNC I O PCM FSYNC channel clock input output dedicated Xi2s0SDI Xi2s1SDI Xpcm0SIN I PCM serial data input dedicated Xi2s0SDO Xi2s1SDO Xpcm0SOUT O PC...

Page 1897: ...nd Shift control 0x00000000 PCM_TXFIFO 0xE120_0008 R W Specifies the PCM TxFIFO write port 0x00010000 PCM_RXFIFO 0xE120_000C R W Specifies the PCM RxFIFO read port 0x00010000 PCM_IRQ_CTL 0xE120_0010 R W Specifies the PCM Interrupt Control 0x00000000 PCM_IRQ_STAT 0xE120_0014 R Specifies the PCM Interrupt Status 0x00000000 PCM_FIFO_STAT 0xE120_0018 R Specifies the PCM FIFO Status 0x00000000 PCM_CLRI...

Page 1898: ...s ALMOST_FULL as the DMA request keep requesting data until the FIFO is almost full In some circumstances the DMA write one more word after the DMA_req fall to low Thus the ALMOST_FULL flag most go active with at least space for one extra word in the FIFO 0 RXFIFO _DIPSTICK 12 7 Determines when the ALMOST_FULL ALMOST_EMPTY flags go active for the RXFIFO ALMOST_EMPTY fifo_depth fifo_dipstick ALMOST...

Page 1899: ...MSCLK during the same cycle that PCMSYNC is high 1 MSB is captured on the falling edge of PCMSCLK during the cycle after the PCMSYNC is high 0 PCM_TXFIFO _EN 2 Enables the TXFIFO When the enable is LOW the internal FIFOs will clear and reinitialize 0 PCM_RXFIFO _EN 1 Enables the RXFIFO When the enable is LOW the internal FIFOs will clear and reinitialize 0 PCM_PCM _ENABLE 0 PCM enable signal Enabl...

Page 1900: ...MCODEC_CLK Final clock will be source_clk 2 sclk_div 1 000 SYNC_DIV 8 0 Controls the frequency of the PCMSYNC signal based on the PCMSCLK 000 5 6 1 3 The PCM Tx FIFO Register PCM_TXFIFO PCM_TXFIFO R W Address 0xE230_0008 PCM_TXFIFO R W Address 0xE120_0008 PCM_TXFIFO R W Address 0xE2B0_0008 The bit definitions for the PCM_TXFIFO Register are described below PCM_TXFIFO Bit Description Initial State ...

Page 1901: ...elow PCM_RXFIFO Bit Description Initial State Reserved 31 17 Reserved 0 RXFIFO_DVALID 16 RXFIFO data is valid Write Not Valid Read TXFIFO read data valid 1 Valid 0 Invalid probably read an empty fifo 1 RXFIFO_DATA 15 0 RXFIFO DATA Write RXFIFO_DATA is written into the RXFIFO Note writing the RXFIFO is meant to support debugging Online the RXFIFO is written by the PCM serial shift engine not the AP...

Page 1902: ... a word completes 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_EMPTY 11 Interrupt is generated whenever the TxFIFO is empty 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_ALMOST _EMPTY 10 Interrupt is generated whenever the TxFIFO is ALMOST empty Almost empty is defined as TX_FIFO_DEPTH TX_FIFO_DIPSTICK 1 IRQ source enabled 0 IRQ source disabled 0 TXFIFO_FULL 9 Interrupt is generated w...

Page 1903: ...Q source disabled 0 RX_FIFO_FULL 3 Interrupt is generated whenever the RxFIFO is full 1 IRQ source enabled 0 IRQ source disabled 0 RX_FIFO _ALMOST _FULL 2 Interrupt is generated whenever the RxFIFO is ALMOST full Almost full is defined as RX_FIFO_DEPTH 32 RX_FIFO_DIPSTICK 1 IRQ source enabled 0 IRQ source disabled 0 RXFIFO_ERROR _STARVE 1 Interrupt is generated for RxFIFO starve ERROR This occurs ...

Page 1904: ...0 TXFIFO_ALMOST _EMPTY 10 Interrupt is generated whenever the TxFIFO is ALMOST empty 1 IRQ is occurred 0 IRQ is not occurred 0 TXFIFO_FULL 9 Interrupt is generated whenever the TX FIFO is full 1 IRQ is occurred 0 IRQ is not occurred 0 TXFIFO_ALMOST _FULL 8 Interrupt is generated whenever the TX FIFO is ALMOST full 1 IRQ is occurred 0 IRQ is not occurred 0 TXFIFO_ERROR _STARVE 7 Interrupt is genera...

Page 1905: ...rupt is generated whenever the RX FIFO is ALMOST full 1 IRQ is occurred 0 IRQ is not occurred 0 RXFIFO_ERROR _STARVE 1 Interrupt is generated for RX FIFO starve ERROR This occurs whenever the RX FIFO is read when it is still empty This is considered as an ERROR and will have unexpected results 1 IRQ is occurred 0 IRQ is not occurred 0 RXFIFO_ERROR _OVERFLOW 0 Interrupt is generated for RX FIFO ove...

Page 1906: ... whether TXFIFO is almost full 0 RXFIFO_COUNT 9 4 RXFIFO data count 0 32 0 RXFIFO_EMPTY 3 To indicate whether RXFIFO is empty 0 RXFIFO_ALMOST_EMPTY 2 To indicate whether RXFIFO is almost empty 0 RX_FIFO_FULL 1 To indicate whether RXFIFO is full 0 RX_FIFO_ALMOST_FULL 0 To indicate whether RXFIFO is almost full 0 5 6 1 8 PCM Interrupt Clear Register PCM_CLRINT The PCM_CLRINT register is used to clea...

Page 1907: ...ssible If you use SPDIF in a broadcasting studio environment the interface is primarily intended to carry monophonic or stereophonic programs at a 48 kHz sampling frequency and with a resolution of up to 24 bits per sample it can carry one or two signals sampled at 32 kHz In both cases the clock references and auxiliary information are transmitted with the program Provision in IEC60958 is made to ...

Page 1908: ...nerator block This block generates 128fs sampling frequency clock used in out_spdif block from system audio clock MCLK Clock Multiplex block system audio clock MCLK can be selected as internal MCLK or external MCLK Audio_if_core block This block acts as interface block between data buffer and out_spdif block Finite state machine controls the flow of PCM data spdif_tx block This block inserts burst...

Page 1909: ...reamble is changed to preamble B once every 192 frame This unit composed of 192 frames defines the block structure used to organize the channel status information Sub frames of channel 2 right or B in stereophonic operation and secondary channel in monophonic operation always use preamble W In the single channel operation mode in broadcasting studio environment the frame format is identical to the...

Page 1910: ...f the source provides fewer bits than the interface allows 24 or 20 the unused least significant bits shall be set to a logical 0 This procedure supports to connect equipment using different numbers of bits Time slot 28 carries the validity flag associated with the audio sample word This flag is set to logical 0 if the audio sample is reliable Time slot 29 carries one bit of the user data associat...

Page 1911: ...bit to be transmitted is logical 0 is different from the first if the bit is logical 1 Clock twice bit rate Source coding Channel coding bi phase mark Figure 6 4 Channel Coding 6 4 3 PREAMBLE Preambles are specific patterns providing synchronization and identification of the sub frames and blocks A set of three preambles M B and W is used These preambles are transmitted in the time allocated to fo...

Page 1912: ... 16 bit words Pa Pb Pc Pd followed by the burst payload which contains data of an encoded audio frame The burst preamble consists of four mandatory fields Pa and Pb represent a synchronization word Pc gives information about the type of data and some information control for the receiver Pd gives the length of the burst payload limited to 216 65 535 bits The four preamble words are contained in two...

Page 1913: ...ts of Pa Pb Pc and Pd before burst payload and zero is padded from the end of burst payload to the repetition count Pa 16 hF872 and Pb 16 h4E1F is fixed in the module and Pc and Pd is set in the register SPDBSTAS To stuff zero the end of burst payload is calculated from Pd value and repetition count which depends on data type in the preamble Pc is acquired from register SPDCNT Audio data are justi...

Page 1914: ...and SPDCNT register because previous information is copied to their respective shadowed registers 4 Set next stream information to SPDBSTAS and SPDCNT register 5 Wait for stream end interrupt which signals the end of the first stream 6 With stream end interrupt the 2nd stream data will start to transfer Set 3rd stream information to registers The usage of user bit registers is similar to stream in...

Page 1915: ...der to use these pads for SPDIF GPIO must be set before the SPDIF starts For more information refer to the GPIO chapter of this manual for exact GPIO setting Signal I O Description Pad Type I_MLCK_EXT I Global audio main clock External MCLK Xpcm0EXTCLK muxed O_SPDIF_DATA O SPDIFOUT data output Xpcm0SCLK muxed ...

Page 1916: ...petition count register 0x0000_0000 SPDBSTAS_SHD 0XE110_0018 R Specifies the Shadowed Burst Status Register 0x0000_0000 SPDCNT_SHD 0XE110_001C R Specifies the Shadowed Repetition Count Register 0x0000_0000 USERBIT1 0XE110_0020 R W Specifies the Subcode Q1 Q32 0x0000_0000 USERBIT2 0XE110_0024 R W Specifies the Subcode Q33 Q64 0x0000_0000 USERBIT3 0XE110_0028 R W Specifies the Subcode Q65 Q96 0x0000...

Page 1917: ...Level Monitoring Read Only FIFO depth is 16 0 Empty of FIFO Level 16 Full of FIFO Level 00000 FIFO Level Threshold 21 19 FIFO Threshold Level is controllable 000 0 FIFO Level 001 1 FIFO Level 010 4 FIFO Level 011 6 FIFO Level 100 10 FIFO Level 101 12 FIFO Level 110 14 FIFO Level 111 15 FIFO Level 000 FIFO transfer mode 18 17 00 DMA transfer mode 01 Polling mode 10 Interrupt mode 11 Reserved 00 FIF...

Page 1918: ...his flag 0 User Data Interrupt Enable 10 0 Interrupt masked 1 Interrupt enable 0 Buffer Empty Interrupt Status 9 Read Operation 0 No interrupt pending 1 Interrupt pending Write Operation 0 No effect 1 Clear this flag 0 Buffer Empty Interrupt Enable 8 0 Interrupt masked 1 Interrupt enable 0 Stream End Interrupt Status 7 Read Operation 0 No interrupt pending 1 Interrupt pending when the number of ou...

Page 1919: ... data length bit 31 16 ES size in bits Burst Preamble Pd ES size Elementary Stream size This indicates Burst payload length 0 Bitstream number 15 13 Bit_stream_number shall be set to 0 0 Data type dependent info 12 8 Data type dependent information 0 Error flag 7 0 Error flag indicates a valid burst_payload 1 Error flag indicates that the burst payload may contain errors 0 6 5 Reserved 0 Compresse...

Page 1920: ...layer 0000_0001 DAT player L000_0011 DCC player L100_0011 Mini disc L100_1001 L information about generation status of the material 0 Channel status mode 7 6 00 Mode 0 Others Reserved 0 Emphasis 5 3 When bit1 0 000 2 audio channels without pre emphasis 001 2 audio channels with 50us 15us pre emphasis When bit1 1 000 default state 0 Copyright assertion 2 0 Copyright 1 No copyright 0 Audio sample wo...

Page 1921: ...umber 15 13 Bit_stream_number shall be set to 0 0 Data Type Dependent Info 12 8 Data type dependent information 0 Error Flag 7 0 Error flag indicating a valid burst_payload 1 Error flag indicating that the burst payload may contain errors 0 6 5 Reserved 0 Compressed Data Type 4 0 00000 Null Data 00001 AC 3 00010 Reserved 00011 Pause 00100 MPEG1 layer1 00101 MPEG1 layer2 3 MPEG2 bc 00110 MPEG2 exte...

Page 1922: ...tate User Data Bit subcode Q for CD 31 0 USERBIT1 Q1 Q32 USERBIT2 Q33 Q64 USERBIT3 Q65 Q96 User Data Bit has the Digital Audio Track information Track NO Play Time etc 1176 bits of these being taken out in a row 0 6 6 1 10 Shadowed User Data Register USERBIT_SHD USERBIT1_SHD R Address 0XE110_002C USERBIT2_SHD R Address 0XE110_0030 USERBIT3_SHD R Address 0XE110_0034 USERBIT_SHD Bit Description Init...

Page 1923: ...n on the external touch screen device Touch Screen Interface contains three main blocks namely touch screen pads control logic ADC interface logic and interrupt generation logic There are two set of touch screen interfaces which share one ADC 7 2 KEY FEATURES OF ADC TOUCH SCREEN INTERFACE The ADC Touch Screen interface includes the following features Resolution 10 bit 12 bit optional Differential ...

Page 1924: ... D Converter ADC interface Touch screen control ADC input control Interrupt generation INT_ADC0 INT_PEN0 Waiting for interrupt VDDA_ADC VDDA_ADC AIN5 XP0 AIN9 XP1 AIN1 AIN0 VDDA_ADC AIN4 XM0 AIN8 XM1 AIN3 YP0 AIN7 YP1 AIN2 YM0 AIN6 YM1 YM_SEN0 1 XP_SEN0 1 YP_SEN0 1 INT_ADC1 INT_PEN1 Figure 7 1 ADC and Touch Screen Interface Functional Block Diagram NOTE When Touch Screen device is not used XM XP Y...

Page 1925: ...om TSDATX0 ADC conversion data X register NOTE TSADCCON1 register is useless in normal conversion mode Therefore TSSEL bit of TSADCCON0 register should be 0 TSADCCON1 register is meaningless if TSSEL bit is 0 2 Separate X Y Position Conversion Mode AUTO_PST 0 XY_PST control This mode consists of two states namely X position measurement state and Y position measurement state Steps to operate X posi...

Page 1926: ...Mode Set 0x5c to TSCONn XY_PST 0 AUTO_PST 1 PULL_UP disable XP disable XM disable YP disable YM disable Start conversion by setting TSADCCONn Touch screen controller converts X Position and writes it to TSDATXn Touch screen controller converts Y Position and writes it to TSDATYn Touch screen interface generates interrupt INT_ADCn In other words INT_ADCn is occurred only once not twice 4 Waiting fo...

Page 1927: ...WO TOUCH SCREEN INTERFACES There are two set of touch screen interfaces namely AIN 5 AIN 2 for touch screen 0 and AIN 9 AIN 6 for touch screen 1 There are separate switches for XP XM YP and YM control and separate registers to interface with two touch screens They share one analog digital converter so interfacing with the two touch screens should be performed in turn TSSEL bit of TSADCCON0 registe...

Page 1928: ... A D conversion can be activated in different way After TSADCCONn 1 A D conversion start by read mode is set to 1 A D conversion starts simultaneously when converted data is read Stylus Down X Conversion Y Conversion Stylus Up A B C A D x 1 X tal clock or D x 1 RTCCLK clock B D x 1 PCLK clock 5 x 1 PCLK clock C D x 1 PCLK clock 5 x 1 PCLK clock D Delay value of ADCDLY register XP YP Figure 7 2 ADC...

Page 1929: ...S5PC110_UM 7 ADC TOUCH SCREEN INTERFACE 7 8 7 5 ADC TOUCH SCREEN INTERFACE INPUT CLOCK DIAGRAM FILCLK Figure 7 3 Input Clock Diagram for ADC Touch Screen Interface ...

Page 1930: ...annel 7 Analog input XadcAIN 7 Analog AIN 6 Input ADC Channel 6 Analog input XadcAIN 6 Analog AIN 5 Input ADC Channel 5 Analog input XadcAIN 5 Analog AIN 4 Input ADC Channel 4 Analog input XadcAIN 4 Analog AIN 3 Input ADC Channel 3 Analog input XadcAIN 3 Analog AIN 2 Input ADC Channel 2 Analog input XadcAIN 2 Analog AIN 1 Input ADC Channel 1 Analog input XadcAIN 1 Analog AIN 0 Input ADC Channel 0 ...

Page 1931: ...C0 0xE170_0018 W Specifies the TS0 Clear ADC0 Interrupt ADCMUX 0xE170_001C R W Specifies the Analog input channel selection 0x0000_0000 CLRINTPEN0 0xE170_0020 W Specifies the TS0 Clear Pen0 Down Up Interrupt TSADCCON1 0xE170_1000 R W Specifies the TS1 ADC Control Register 0x0000_3FC4 TSCON1 0xE170_1004 R W Specifies the TS1 Touch Screen Control Register 0x0000_0058 TSDLY1 0xE170_1008 R W Specifies...

Page 1932: ...converter prescaler enable 0 Disable 1 Enable 0 PRSCVL 13 6 A D converter prescaler value Data value 5 255 The division factor is N 1 when the prescaler value is N For example ADC frequency is 3 3MHz if PCLK is 66MHz and the prescaler value is 19 Note This A D converter is designed to operate at maximum 5MHz clock so the prescaler value should be set such that the resulting clock does not exceed 5...

Page 1933: ...C 0 XP_SEN 4 XP to VDD Switch Enable 0 Switch enable XP VDDA_ADC 1 Switch disable XP Hi z 1 PULL_UP 3 Pull up Switch Enable 0 XP Pull up Enable 1 XP Pull up Disable 1 AUTO_PST 2 Automatic sequencing conversion of X Position and Y Position 0 Normal ADC conversion 1 Auto Sequential measurement of X position Y position 0 XY_PST 1 0 Manually measurement of X Position or Y Position 00 No operation mode...

Page 1934: ...l State FILCLKsrc 16 Reference clock source for delay 0 X tal clock 1 RTC clock 0 DELAY 15 0 In case of ADC conversion mode Normal Separate Auto conversion ADC conversion is delayed by counting this value Counting clock is PCLK ADC conversion delay value In case of waiting for Interrupt mode When stylus down occurs in waiting for interrupt mode it generates interrupt signal INT_PENn at interval of...

Page 1935: ... 11 Waiting for Interrupt Mode XPDATA Normal ADC 11 0 X Position conversion data value includes normal ADC conversion data value Data value 0x0 0xFFF 7 7 1 5 ADC Conversion Data Y Register TSDATYn TSDATY0 R Address 0xE170_0010 TSDATY1 R Address 0xE170_1010 TSDATYn Bit Description Initial State UPDOWN 15 Up or Down state of stylus pen at Waiting for Interrupt Mode 0 Pen down state 1 Pen up state AU...

Page 1936: ...hould be cleared manually 0 No pen down state 1 Pen down interrupt has been occurred 0 7 7 1 7 ADC Interrupt Clear Register CLRINTADCn CLRINTADC0 W Address 0xE170_0018 CLRINTADC1 W Address 0xE170_1018 These registers are used to clear the interrupts Interrupt service routine is responsible to clear interrupts after the interrupt service is completed Writing any values on this register will clear u...

Page 1937: ...0 AIN 8 XM1 1001 AIN 9 XP1 0 NOTE 1 When touch screen is not used the touch screen ports AIN2 AIN9 can be used as analog input ports for ADC 2 SEL_MUX value is invalid when TSADC is set as 1 separate X Y position conversion mode or 2 auto sequential X Y position conversion mode 7 7 1 9 Pen Interrupt Clear Register CLRINTPENn CLRINTPEN0 W Address 0xE170_0020 CLRINTPEN1 W Address 0xE170_1020 CLRINTP...

Page 1938: ...1 for 14x8 You can also make your own mapping that can be mix of port0 and port1 The events of key press or key release are delivered to the CPU by an interrupt If one of the interrupt from row lines occurs the software must scan the column lines using the proper procedure to detect one or multiple key press or release It provides interrupt status register bits at the time of key pressed or key re...

Page 1939: ...59 60 5 13 33 47 61 70 71 72 73 74 75 GPIO KEYIF 84 85 86 87 88 89 98 99 100 101 102 103 7 21 35 49 63 77 91 105 6 20 34 48 62 76 90 104 22 23 24 25 26 27 36 37 38 39 40 41 50 51 52 53 54 55 64 65 66 67 68 69 78 79 80 81 82 83 92 93 94 95 96 97 106 107 108 109 110 111 14 15 16 17 18 19 Figure 8 1 Key Matrix Interface External Connection Guide ...

Page 1940: ...k when the FCLK is 32kHz The keypad interrupt key pressed or key released to the CPU is an ANDed signal of the all row input lines after filtering FILTER _IN FILTER_OUT Filter width FCLK two clock Filter Clock FCLK is a FLT _ CLK or the division of that clock FLT _ CLK is come from System Controller OSC_ IN or USB_ XTI FCLK two clock width Figure 8 2 Internal Debouncing Filter Operation ...

Page 1941: ...vider does not divide FLT_CLK 8 4 WAKEUP SOURCE KEYPAD inputs using Port0 can be used as a wakeup source When the Key input is used for wakeup source from IDLE STOP or SLEEP mode KEYPAD interface register setting is not required GPIO register setting GPH2CON GPH3CON for KEYPAD interface and SYSCON register PWR_CFG for masking are required for wakeup Therefore to use 14x8 KEYIF which can be used by...

Page 1942: ...on the corresponding row line generating a keypad interrupt The CPU software outputs a LOW on one column line and Hi Z on the others by setting KEYIFCOLEN and KEYIFCOL fields in KEYIFCOL register Each write time the CPU reads the value of the KEYIFROW register and detects if one key of the corresponding column line is pressed Because the KEYIF has pull up PAD each KEYIFROW bits will be read as HIG...

Page 1943: ...H H H H H H H L L L L L L L L interrupt generated and knows which row is pressed Key Pressed Short H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Scan Procedure S W make one output LOW the others HIGH and Read KEYIN Read KEYIN register All High if not matched Figure 8 4 Keypad Scanning Procedure II Figure 8 5 Keypad Scanning Procedure III ...

Page 1944: ...detected row column 2nd Row Key pressed state 1st Row Key interrupt set to Released key state 2nd Row Key interrupt S W in ISR pressed key is detected S W detect when the 1st Row Key pressed state 2nd Row Key Interrupt set to Released key state 1st Row Key pressed state Pressed Key filtered view 1st Row Key 2nd Row Key Figure 8 6 Keypad Scanning Procedure when the two key Pressed with Different Ro...

Page 1945: ...ng Filter 2 filter clock SCAN _Y 7 0 SFR Write Read FLT_ CLK APB bus Interface Positive One pulse keypress Keyrelease control signals KEYIFFC 10 bit Counter OSCIN clock 12MHz Or USB_XTI 48 MHz FC_EN WAKEUP _ INT_EN KEYFLT6 KEYFLT13 KEY _ WAKEUP _ INT from ALIVE block INT_R_ EN INT_F_ EN Figure 8 7 Keypad I F Block Diagram ...

Page 1946: ...0 GPH3 6 XmsmDATA 13 GPJ3 5 muxed ROW_IN 5 I KEYPAD Interface Row 5 Data XEINT 29 GPH3 5 XmsmDATA 12 GPJ3 4 muxed ROW_IN 4 I KEYPAD Interface Row 4 Data XEINT 28 GPH3 4 XmsmDATA 11 GPJ3 3 muxed ROW_IN 3 I KEYPAD Interface Row 3 Data XEINT 27 GPH3 3 XmsmDATA 10 GPJ3 2 muxed ROW_IN 2 I KEYPAD Interface Row 2 Data XEINT 26 GPH3 2 XmsmDATA 9 GPJ3 1 muxed ROW_IN 1 I KEYPAD Interface Row 1 Data XEINT 25...

Page 1947: ...ce Column 3 Data XEINT 19 GPH2 3 XmsmDATA 2 GPJ2 0 Muxed COL_OUT 2 O KEYPAD Interface Column 2 Data XEINT 18 GPH2 2 XmsmDATA 1 GPJ2 0 muxed COL_OUT 1 O KEYPAD Interface Column 1 Data XEINT 17 GPH2 1 XmsmDATA 0 GPJ2 0 muxed COL_OUT 0 O KEYPAD Interface Column 0 Data XEINT 16 GPH2 0 XmsmADDR 13 GPJ2 0 muxed ...

Page 1948: ...00000 KEYIFSTSCLR 0xE160_0004 R W Specifies the KEYPAD interface status and clear register 0x00000000 KEYIFCOL 0xE160_0008 R W Specifies the KEYPAD interface column data output register 0x0000FF00 KEYIFROW 0xE160_000C R Specifies the KEYPAD interface row data input register Reflects input ports KEYIFFC 0xE160_0010 R W Specifies the KEYPAD interface debouncing filter clock division register 0x00000...

Page 1949: ...0 Disables 1 Enables 1 b0 NOTE Both edge interrupt is selected when both INT_F_EN and INT_R_EN are set 8 7 1 2 KEYPAD Interrupt Status and Clear Register KEYIFSTSCLR R W Address 0xE160_0004 KEYIFSTSCLR Bit Description Initial State R_INT 29 16 KEYPAD input release interrupt rising edge status read and clear write Read 1 Released interrupt occurred 0 Not occurred Write Released interrupt is cleared...

Page 1950: ... 1 4 KEYPAD Interface Row Data Input Register KEYIFROW R Address 0xE160_000C KEYIFROW Bit Description Initial State Reserved 31 16 Reserved for future use KEYIFROW 13 0 KEYPAD interface row data input register read only This register values from input ports are not filtered data Reflects input ports 8 7 1 5 KEYPAD Interface Debouncing Filter Clock Division Register KEYIFFC R W Address 0xE160_0010 ...

Page 1951: ...Section 11 SECURITY ...

Page 1952: ...e 2 1 2 1 Overview of Advanced Crypto Engine 2 1 2 1 1 KEY Features of SSS 2 3 2 2 Functional Description OF SSS 2 4 2 2 1 CPU Mode 2 4 2 2 2 FIFO Mode 2 4 2 2 3 Byte Swapping Options 2 8 2 3 Register Description 2 11 2 3 1 Register Map 2 11 2 3 2 TDES Control TDES_OUTPUT_0 R Address 0xEA00_5038 2 33 ...

Page 1953: ... 4 Data flow of AES and Hash with Shared Input 2 5 Figure 2 5 Data Flow of Hashing the Output of AES 2 6 Figure 2 6 FIFO and FIFO Interconnections 2 6 Figure 2 7 Interrupt Controller Scheme for one Interrupt Signal 2 7 Figure 2 8 AES Byte Swapping Scheme 2 8 Figure 2 9 DES Byte Swapping Scheme 2 9 Figure 2 10 Hash Byte Swapping Scheme 2 10 Figure 2 11 PKA Byte Swapping Scheme 2 10 ...

Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...

Page 1955: ...is also embedded in S5PC110 which authenticates multi level H W access right There is built in 80 bit e fuse which has hashed key value to support secure JTAG Additionally users can design security solution more conveniently using H W security engine such as DES TDES AES SHA 1 PRNG and PKA Table 1 1 Security Features of S5PC110 Description Secure Booting On chip 64KB secure boot ROM On chip 96KB s...

Page 1956: ...3DES SHA 1 MD5 HMAC and PRNG Public Key Accelerator PKA Feed Controller FeedCtrl FeedCtrl comprises of the following components Block Cipher Receiving DMA BRDMA Block Cipher Transmission DMA BTDMA Hash Receiving DMA HRDMA PKA Bi directional DMA PKDMA FIFO and FIFO Interconnections Interrupt Controller FIFO Controller SSS comprises of the following external interfaces One bus slave port for SFR set...

Page 1957: ...S DES 3DES SHA 1 and MD5 DMA supplies input data to each IP through FIFO DMA drains output data from each IP except SHA 1 and MD5 through FIFO Block ciphers and hashes can share input data Output data of block ciphers can be used as input of the hash PKA SRAM PKDMA SRAM I F BTDMA BRDMA HRDMA AHB Security Sub System Boundary Bus Port AHB Mux FIFO I F unidir Control FeedCtrl AES DES 3DES HASH PRNG F...

Page 1958: ...ECB and CBC modes 3DES ECB CBC EDE and EEE modes SHA 1 with hardware padding and SHA 1 HMAC MD5 w hardware padding and MD5 HMAC Pseudo Random Number Generator PRNG Public Key Accelerator PKA DMA Support for AES DES 3DES SHA 1 MD5 and PKA Block Ciphers combined with Hashing Concurrent AES DES and SHA1 MD5 SHA 1 MD5 after AES DES ...

Page 1959: ...ta trigger an operation and extract the output data 2 2 2 FIFO MODE BRDMA supplies input data to block ciphers such as AES or DES as shown in Figure 2 2 On the other hand BTDMA receives output data from AES or DES Only one block either AES or DES can use the DMA The other block that does not occupy the DMA can be used in CPU or buffered CPU modes Figure 2 2 DES or 3DES Only Data Flow 2 4 ...

Page 1960: ... Hash Receiving DMA HRDMA can work independently of BRDMA or BTDMA In this case the hash processes different data stream than block ciphers Figure 2 3 AES and Hash parallel data flow Figure 2 4 shows the configuration of AES and hash with shared input data from external memory Figure 2 4 Data flow of AES and Hash with Shared Input 2 5 ...

Page 1961: ...r the above two cases HRDMA cannot be used 2 2 2 1 FIFO Configuration The FCFIFOCTRL register affects FIFO configuration The DESSEL bit of FCFIFOCTRL selects between DES and AES Also the HASHINSEL bits select hash input data from three possible inputs that comes from HRDMA input of block cipher and output of block cipher Figure 2 6 FIFO and FIFO Interconnections 2 6 ...

Page 1962: ...ddress and the length is 0 The flushing state should be released by writing value 0 to this bit 2 2 2 3 Interrupt Controller for DMA Interrupt Figure 2 7 shows the interrupt controller scheme for one interrupt signal Each of the four DMA interrupt signals have the following control scheme that is each interrupt signal is generated by a DMA in pulse form and latched by the FCINTPEND register to for...

Page 1963: ...tions for every data be it data input data output initial value key and counter Moreover all DMA BRDMA and BTDMA have their own swapping option The byte swapping option of DMA should follow the bus endian 1 For little endian bus the DMA should swap data 2 For big endian bus the DMA should not swap data The only reason why option 2 must be used is that S5PC110 supports little endian case In case DE...

Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...

Page 1965: ...O ENGINE Data Input Data Output Initial Value Hash Engine AHB Bus DMA Engine AHB Bus SWAP_DI SWAP_DO SWAP_IV HASH BRDMA or HRDMA Byte Swapping Logic Figure 2 10 Hash Byte Swapping Scheme Figure 2 11 PKA Byte Swapping Scheme 2 10 ...

Page 1966: ... the length of block cipher receiving DMA 0x0000_0000 FCBRDMAC 0xEA00_0028 R W Specifies the control of block cipher receiving DMA 0x0000_0000 FCBTDMAS 0xEA00_0030 R W Specifies the start address of block cipher transmitting DMA 0x0000_0000 FCBTDMAL 0xEA00_0034 R W Specifies the length of block cipher transmitting DMA 0x0000_0000 FCBTDMAC 0xEA00_0038 R W Specifies the control of block cipher trans...

Page 1967: ...pecifies the Initialization vector to be used in encryption decryption 95 64 0x0000_0000 AES_ivdata_03 0xEA00_4038 W Specifies the Initialization vector to be used in encryption decryption 63 32 0x0000_0000 AES_ivdata_04 0xEA00_403C W Specifies the Initialization vector to be used in encryption decryption 31 0 0x0000_0000 AES_cntdata_01 0xEA00_4040 W Specifies the Counter data be used in encryptio...

Page 1968: ...ey 3 31 0 0x0000_0000 TDES_IV_0 0xEA00_5028 W Specifies the TDES Initial vector 63 32 0x0000_0000 TDES_IV_1 0xEA00_502C W Specifies the TDES Initial vector 31 0 0x0000_0000 TDES_INPUT_0 0xEA00_5030 W Specifies the TDES Input Data 63 32 0x0000_0000 TDES_INPUT_1 0xEA00_5034 W Specifies the TDES Input Data 31 0 0x0000_0000 TDES_OUTPUT_0 0xEA00_5038 R Specifies the TDES output Data 63 32 0x0000_0000 T...

Page 1969: ...ASH_SEED_IN_2 0xEA00_6044 W Specifies the PRNG seed data input 2 HASH_SEED_IN_3 0xEA00_6048 W Specifies the PRNG seed data input 3 HASH_SEED_IN_4 0xEA00_604C W Specifies the PRNG seed data input 4 HASH_SEED_IN_5 0xEA00_6050 W Specifies the PRNG seed data input 5 HASH_RESULT_1 0xEA00_6060 R Specifies the Hash HMAC Partial result 1 0x6745_2301 HASH_RESULT_2 0xEA00_6064 R Specifies the Hash HMAC Part...

Page 1970: ...MSG_ LENG_HIGH 0xEA00_60C0 W Specifies the Pre message length 63 32 0 HASH_PRE_MSG_ LENG_LOW 0xEA00_60C4 W Specifies the Pre message length 31 0 0 PKA PKA_SFR0 0xEA00_7000 R W CHNK_SZ PREC_ID 0x0000_0000 PKA_SFR1 0xEA00_7004 R W PLDM_ON EXEC_ON 0x0000_0000 PKA_SFR2 0xEA00_7008 R W SEG_ID A B M S 0x0000_0000 PKA_SFR3 0xEA00_700C R W SEG_SIGN 0x0000_0000 PKA_SFR4 0xEA00_7010 R W SEG_SIZE FUNC_ID 0x0...

Page 1971: ...cifies the interrupt enable set signal of block cipher receiving DMA 0 BTDMAINTENSET 2 Specifies the interrupt enable set signal of block cipher transmitting DMA 0 HRDMAINTENSET 1 Specifies the interrupt enable set signal of hash receiving DMA 0 PKDMAINTENSET 0 Specifies the interrupt enable signal of PKA DMA 0 2 3 1 3 Feed Control FCINTENCLR R W Address 0xEA00_0008 FCINTENCLR Bit Description R W ...

Page 1972: ...gnal of PKA DMA 0 2 3 1 5 Feed Control FCFIFOSTAT R Address 0xEA00_0010 FCFIFOSTAT Bit Description R W Initial State Reserved 31 8 Reserved 0 BRFIFOFUL 7 Specifies the Full state of Block cipher Receiving FIFO 0 BRFIFOEMP 6 Specifies the Empty state of Block cipher Receiving FIFO 1 BTFIFOFUL 5 Specifies the Full state of Block cipher Transmitting FIFO 0 BTFIFOEMP 4 Specifies the Empty state of Blo...

Page 1973: ...nput 1 Data from block cipher output 2 Reserved 3 0 2 3 1 7 Feed Control FCBRDMAS R W Address 0xEA00_0020 FCBRDMAS Bit Description R W Initial State STARTADDR 31 0 Specifies the Start Address of DMA The address does not to be aligned by 32 bit Its value increases by 4 after every transaction 0 2 3 1 8 Feed Control FCBRDMAL R W Address 0xEA00_0024 FCBRDMAL Bit Description R W Initial State LENGTH 3...

Page 1974: ... FIFO and DMA After flushing the start address keeps the stopped address and the length is 0 The flushing state should be released by writing value 0 to this bit 0 2 3 1 10 Feed Control FCBTDMAS R W Address 0xEA00_0030 FCBTDMAS Bit Description R W Initial State STARTADDR 31 0 Specifies the Start Address of DMA The address needs not to be aligned by 32 bit Its value increases by 4 after every trans...

Page 1975: ...m FIFO and DMA After flushing the start address keeps the stopped address and the length is 0 The flushing state should be released by writing value 0 to this bit 0 2 3 1 13 Feed Control FCHRDMAS R W Address 0xEA00_0040 FCHRDMAS Bit Description R W Initial State STARTADDR 31 0 Specifies the Start Address of DMA The address does not to be aligned by 32 bit Its value increases by 4 after every trans...

Page 1976: ...from FIFO and DMA After flushing the start address keeps the stopped address and the length is 0 The flushing state should be released by writing value 0 to this bit 0 2 3 1 16 Feed Control FCPKDMAS R W Address 0xEA00_0050 FCPKDMAS Bit Description R W Initial State STARTADDR 31 0 Specifies the Start Address of DMA The address needs to be aligned by 32 bit Its value increases by 4 after every trans...

Page 1977: ... this bit is high then offset value in FCPKDMAO decreases by 4 after every transfer 0 TRANSMIT 1 Selects receiving 0 or transmitting 1 0 FLUSH 0 If this bit is high then data flushes out from FIFO and DMA After flushing the start address keeps the stopped address and the length is 0 The flushing state should be released by writing value 0 to this bit 0 2 3 1 19 Feed Control FCPKDMAO R W Address 0x...

Page 1978: ...d 0 AES Key Size 5 4 Specifies the AES key size selection signal 00 128 bit key 01 192 bit key 10 256 bit key 00 FIFO Mode 3 Specifies the ARM FIFO mode selection signal 0 ARM mode ARM Slave 1 FIFO mode 0 AES Chain Mode 2 1 Specifies the AES chain mode selection signal 00 ECB mode 01 CBC mode 10 CTR mode 00 AES Mode 0 Specifies the Encryption Decryption mode selection signal 0 Encryption 1 Decrypt...

Page 1979: ...gnal 0 AES output is not available 1 AES output is available to the host for retrieval 0 NOTE To clear the Output Ready bit write 0x1 at that bit AES_status 0 2 3 1 22 AES Control AES_indata_01 W Address 0xEA00_4010 AES_indata_01 Bit Description R W Initial State AES_indata_01 31 0 Specifies the Input data 127 96 0 2 3 1 23 AES Control AES_indata_02 W Address 0xEA00_4014 AES_indata_02 Bit Descript...

Page 1980: ...31 0 Specifies the Output data 127 96 0 2 3 1 27 AES Control AES_outdata_02 R Address 0xEA00_4024 AES_outdata_02 Bit Description R W Initial State AES_outdata_02 31 0 Specifies the Output data 95 64 0 2 3 1 28 AES Control AES_outdata_03 R Address 0xEA00_4028 AES_outdata_03 Bit Description R W Initial State AES_outdata_03 31 0 Specifies the Output data 63 32 0 2 3 1 29 AES Control AES_outdata_04 R ...

Page 1981: ...0xEA00_4034 AES_ivdata_02 Bit Description R W Initial State AES_ivdata_02 31 0 Specifies the Initialization vector 95 64 0 2 3 1 32 AES Control AES_ivdata_03 W Address 0xEA00_4038 AES_ivdata_03 Bit Description R W Initial State AES_ivdata_03 31 0 Specifies the Initialization vector 63 32 0 2 3 1 33 AES Control AES_ivdata_04 W Address 0xEA00_403C AES_ivdata_04 Bit Description R W Initial State AES_...

Page 1982: ...ddress 0xEA00_4044 AES_cntdata_02 Bit Description R W Initial State AES_cntdata_02 31 0 Specifies the Counter data 95 64 0 2 3 1 36 AES Control AES_cntdata_03 W Address 0xEA00_4048 AES_cntdata_03 Bit Description R W Initial State AES_cntdata_03 31 0 Specifies the Counter data 63 32 0 2 3 1 37 AES Control AES_cntdata_04 W Address 0xEA00_404C AES_cntdata_04 Bit Description R W Initial State AES_cntd...

Page 1983: ...Specifies the Input key data 223 192 0 2 3 1 40 AES Control AES_keydata_03 W Address 0xEA00_4088 AES_keydata_03 Bit Description R W Initial State AES_keydata_03 31 0 Specifies the Input key data 191 160 0 2 3 1 41 AES Control AES_keydata_04 W Address 0xEA00_408C AES_keydata_04 Bit Description R W Initial State AES_keydata_04 31 0 Specifies the Input key data 159 128 0 2 3 1 42 AES Control AES_keyd...

Page 1984: ... 0 Specifies the Input key data 95 64 0 2 3 1 44 AES Control AES_keydata_07 W Address 0xEA00_4098 AES_keydata_07 Bit Description R W Initial State AES_keydata_07 31 0 Specifies the Input key data 63 32 0 2 3 1 45 AES Control AES_keydata_08 W Address 0xEA00_409C AES_keydata_08 Bit Description R W Initial State AES_keydata_08 31 0 Specifies the Input key data 31 0 0 ...

Page 1985: ...byte swap R W 0 TDES_ByteSwap_ Key 6 0 Disables key byte swap 1 Enables key byte swap R W 0 TDES_FiFo 5 0 CPU 1 FiFo R W 0 TDES_EEE 4 0 TDES EDE mode 1 TDES EEE mode R W 0 TDES_Select 3 0 DES 1 TDES R W 0 Reseved 2 TDES_Mode 1 0 ECB mode 1 CBC mode R W 0 TDES_Enc 0 0 Encryption 1 Decryption R W 0 2 3 1 47 TDES Control TDES_STAT R W Address 0xEA00_5004 TDES_CONF Bit Description R W Initial State Re...

Page 1986: ...DES_ KEY1_1 31 0 Specifies the Input key 1 31 0 0 2 3 1 50 TDES Control TDES_KEY2_0 W Address 0xEA00_5018 TDES_KEY2_0 Bit Description R W Initial State TDES_KEY2_0 31 0 Specifies the Input key 2 63 32 W 0 2 3 1 51 TDES Control TDES_KEY2_1 W Address 0xEA00_501C TDES_KEY2_1 Bit Description R W Initial State TDES_KEY2_1 31 0 Input key 2 31 0 W 0 2 3 1 52 TDES Control TDES_KEY3_0 W Address 0xEA00_5020...

Page 1987: ...ecifies the Input Initial vector 63 32 W 0 2 3 1 55 TDES Control TDES_IV_1 W Address 0xEA00_502C TDES_IV_1 Bit Description R W Initial State TDES_IV_1 31 0 Specifies the Input Initial vector 31 0 W 0 2 3 1 56 TDES Control TDES_INPUT_0 W Address 0xEA00_5030 TDES_INPUT_0 Bit Description R W Initial State TDES_INPUT_0 31 0 Specifies the Input data 63 32 W 0 2 3 1 57 TDES Control TDES_INPUT_1 W Addres...

Page 1988: ...DRESS 0XEA00_5038 TDES_OUTPUT_0 Bit Description R W Initial State TDES_OUTPUT_0 31 0 Specifies the Output data 63 32 R 0 2 3 2 1 TDES Control TDES_OUTPUT_1 R Address 0xEA00_503C TDES_OUTPUT_1 Bit Description R W Initial State TDES_OUTPUT_1 31 0 Specifies the Output data 31 0 R 0 ...

Page 1989: ...4 Starts initializes the hash HMAC PRNG software reset Automatically cleared by hardware 0 USER_IV_EN 5 Uses customized IV Automatically cleared by hardware 0 2 3 2 3 HASH and PRNG Control HASH_CONTROL_2 W Address 0xEA00_6004 HASH_CONTROL_2 Bit Description R W Initial State HASH_PAUSE 3 Pauses a hash operation Automatically cleared by hardware 0 2 3 2 4 HASH and PRNG Control HASH_FIFO_MODE_EN R W ...

Page 1990: ...n the same order as HWDATA 31 0 Otherwise the 32 bit word is byte swapped before entering the hash core Note that the hash core is designed with big endian in mind so you should turn on byte swapping if the bus is little endian 2 SHA1 abcd 81fe8bfe_87576c3e_cb22426f_8e578473_82917acf READ HASH_RESULT_1 Æ HRDATA 0x81fe8bfe when HASH_SWAP_DO 0 READ HASH_RESULT_1 Æ HRDATA 0xfe8bfe81 when HASH_SWAP_DO...

Page 1991: ... PARTIAL_DONE 4 R W The partial result is done Write 1 in this bit to clear it 0 PRNG_DONE 5 R W PRNG is done Write 1 in this bit to clear it 0 MSG_DONE 6 R W Hash HMAC is done Write 1 in this bit to clear it 0 PRNG_ERROR 7 Specifies the PRNG error bit This bit goes HIGH if a PRNG request occurs without a complete seed setup In order to clear this bit you must perform a complete seed setup operati...

Page 1992: ...DATA_IN Bit Description R W Initial State HASH_DATA_IN 31 0 Specifies the key message input register 1 8 Only effective when the FIFO mode is disabled Supports burst up to 8 words 2 3 2 10 HASH and PRNG Control HASH_SEED_IN_1 W Address 0xEA00_6040 HASH_SEED_IN_1 Bit Description R W Initial State HASH_SEED_IN_1 31 0 Specifies the PRNG seed buffer 159 128 2 3 2 11 HASH and PRNG Control HASH_SEED_IN_...

Page 1993: ...RNG seed buffer 63 32 2 3 2 14 HASH and PRNG Control HASH_SEED_IN_5 W Address 0xEA00_6050 HASH_SEED_IN_5 Bit Description R W Initial State HASH_SEED_IN_5 31 0 Specifies the PRNG seed buffer 31 0 2 3 2 15 HASH and PRNG Control HASH_RESULT_1 R Address 0xEA00_6060 HASH_RESULT_1 Bit Description R W Initial State HASH_RESULT_1 31 0 Specifies the Hash HMAC Partial result 1 0x6745_2301 2 3 2 16 HASH and ...

Page 1994: ...1 0 Specifies the Hash HMAC Partial result 4 0x1032_5476 2 3 2 19 HASH and PRNG Control HASH_RESULT_5 R Address 0xEA00_6070 HASH_RESULT_5 Bit Description R W Initial State HASH_RESULT_5 31 0 Specifies the Hash HMAC Partial result 5 0xc3d2_e1f0 2 3 2 20 HASH and PRNG Control HASH_PRNG_1 R Address 0xEA00_6080 HASH_PRNG_1 Bit Description R W Initial State HASH_PRNG_1 31 0 Specifies the PRNG output 1 ...

Page 1995: ... HASH_PRNG_5 R Address 0xEA00_6090 HASH_PRNG_5 Bit Description R W Initial State HASH_PRNG_5 31 0 Specifies the PRNG output 5 0 2 3 2 25 HASH and PRNG Control HASH_IV_1 W Address 0xEA00_60A0 HASH_IV_1 Bit Description R W Initial State HASH_IV_1 31 0 Specifies the Custom IV input 1 2 3 2 26 HASH and PRNG Control HASH_IV_2 W Address 0xEA00_60A4 HASH_IV_2 Bit Description R W Initial State HASH_IV_2 3...

Page 1996: ...HIGH Bit Description R W Initial State HASH_PRE_MSG_ LENG_HIGH 31 0 Specifies the pre message length 63 32 0 2 3 2 31 HASH and PRNG Control HASH_PRE_MSG_LENG_LOW W Address 0xEA00_60C4 HASH_PRE_MSG _LENG_LOW Bit Description R W Initial State HASH_PRE_MSG_ LENG_LOW 31 0 Specifies the pre message length 31 0 0 NOTE 1 HASH_CONTROL_1 ENGINE_SELECTION START_INIT_BIT and USER_IV_EN can be set at the same...

Page 1997: ...l result is involved without knowing the total message size in advance In this case you can initialize the counter with a big number such as 64 h80000000_00000000 for all the parts except the last one While processing the last part through which the message will be known you should initialize this counter with the real message size HASH_IV_1 HASH_IV_5 The values in these five registers are sampled...

Page 1998: ...1 Quadruple precision that is x4 00 Reserved 2 CHNK_SZ 6 3 Sets the chunk size 0000 don t use Default 0001 don t use 0010 don t use 0011 128 bits 0100 160 bits 0101 192 bits 0110 224 bits 0111 256 bits 1000 288 bits 1001 320 bits 1010 352 bits 1011 384 bits 1100 416 bits 1101 448 bits 1110 480 bits 1111 512 bits 0000 Reserved 31 7 NOTE Operand s bit length Chunk s size Precision For example 160 bi...

Page 1999: ...ads the least significant chunk of modulus M 0 NOTE If PLDM_ON is set to 1 PKA loads modulus M s least significant chunk data from memory to PKA s internal register at the initial time of multiplication For the whole modular exponentiation only the first modular multiplication needs to pre load the least significant chunk of modulus M When PKA performs a number of modular multiplications except th...

Page 2000: ... Segment 6 00111 Segment 7 01000 Segment 8 01001 Segment 9 01010 Segment 10 01011 Segment 11 01100 Segment 12 01101 Segment 13 01110 Segment 14 01111 Segment 15 10000 Segment 16 10001 Segment 17 10010 Segment 18 10011 Segment 19 10100 Segment 20 10101 Segment 21 10110 Segment 22 10111 Segment 23 11000 Segment 24 11001 Segment 25 11010 Segment 26 11011 Segment 27 11100 Segment 28 11101 Segment 29 1...

Page 2001: ..._xxxx_xxxx_x1xx Segment 2 is negative xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_0xxx Segment 3 is positive xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_1xxx Segment 3 is negative xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxx0_xxxx Segment 4 is positive xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxx1_xxxx Segment 4 is negative xx_xxxx_xxxx_xxxx_xxxx_xxxx_xx0x_xxxx Segment 5 is positive xx_xxxx_xxxx_xxxx_xxxx_xxxx_xx1x_xxxx Segment 5 is negative xx...

Page 2002: ...xx_xxxx_xxxx_x1xx_xxxx_xxxx_xxxx Segment 14 is negative xx_xxxx_xxxx_xxxx_0xxx_xxxx_xxxx_xxxx Segment 15 is positive xx_xxxx_xxxx_xxxx_1xxx_xxxx_xxxx_xxxx Segment 15 is negative xx_xxxx_xxxx_xxx0_xxxx_xxxx_xxxx_xxxx Segment 16 is positive xx_xxxx_xxxx_xxx1_xxxx_xxxx_xxxx_xxxx Segment 16 is negative xx_xxxx_xxxx_xx0x_xxxx_xxxx_xxxx_xxxx Segment 17 is positive xx_xxxx_xxxx_xx1x_xxxx_xxxx_xxxx_xxxx S...

Page 2003: ...xxx_xxxx_xxxx_xxxx_xxxx_xxxx Segment 24 is negative xx_xx0x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx Segment 25 is positive xx_xx1x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx Segment 25 is negative xx_x0xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx Segment 26 is positive xx_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx Segment 26 is negative xx_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx Segment 27 is positive xx_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx Segme...

Page 2004: ...unction to be executed 0 Montgomery multiplication A by B Default 1 Montgomery multiplication A by 1 0 Reserved 4 1 SEG_SIZE 6 5 Size of the memory segments 00 Full size that is 256 bytes Default 01 Half size that is 128 bytes 10 Quarter size that is 64 bytes 00 Reserved 31 7 NOTE Selecting the half size and quarter size segments is only possible in PKA 2 mode ...

Page 2005: ...Section 12 ETC ...

Page 2006: ...cteristics 1 13 1 7 NFCON AC Electrical Characteristics 1 16 1 8 LPDDR1 mDDR SDRAM Electrical Characteristics 1 18 1 9 LPDDR2 Electrical Characteristi 1 20 1 10 Modemif AC Electrical Characteristics 1 20 1 11 LCD Controller AC Electrical Characteristics 1 21 1 12 Camera Interface AC Electrical Characteristics 1 24 1 13 SDMMC AC Electrical Characteristics 1 26 1 14 SPI AC Electrical Characteristics...

Page 2007: ... 1 13 Figure 1 7 NAND Flash Timing 1 16 Figure 1 8 LPDDR1 SDRAM Read Write Timing Trp 2 Trcd 2 Tcl 2 DW 16 bit 1 18 Figure 1 9 LCD Controller Timing 1 21 Figure 1 10 LCD I80 Interface Timing 1 23 Figure 1 11 Camera Interface VSYNC Timing 1 24 Figure 1 12 Camera Interface HREF Timing 1 24 Figure 1 13 Camera Interface Data Timing 1 25 Figure 1 14 High Speed SDMMC Interface Timing 1 26 Figure 1 15 SP...

Page 2008: ...ming Constants 1 12 Table 1 8 OneNAND Bus Timing Constants 1 14 Table 1 9 NFCON Bus Timing Constants 1 17 Table 1 10 Memory Port 1 2 Interface Timing Constants LPDDR1 SDRAM 1 19 Table 1 11 TFT LCD Controller Module Signal Timing Constants 1 22 Table 1 12 LCD I80 Interface Signal Timing Constants 1 23 Table 1 13 Camera Controller Module Signal Timing Constants 1 25 Table 1 14 High Speed SDMMC Inter...

Page 2009: ...te Maximum Rating Rating Symbol Parameter Minimum Maximum Unit 1 8V VDD 0 5 2 5 VDD DC Supply Voltage 3 3V VDD 0 5 4 6 1 8v Input buffer 0 5 2 5 3 3v Input buffer 0 5 4 6 VIN DC Input Voltage 3 3v Input buffer 5v Tolerant Input buffer 0 5 8 0 1 8v output buffer 0 5 2 5 3 3v output buffer 0 5 4 6 VOUT DC Output Voltage 3 3v output buffer 5V Tolerant Output buffer 0 5 8 0 V II O In Out Current 20 mA...

Page 2010: ... SYS0 Block XEINT0 7 XOM XnRESET XusbXtal JTAG VDD_SYS0 1 7 1 8 2 5 3 0 3 6 DC Supply Voltage for SYS1 Block XEINT8 15 VDD_SYS1 1 7 1 8 2 5 3 0 3 6 DC Supply Voltage for EXT0 VDD_EXT0 1 7 1 8 2 5 3 0 3 6 DC Supply Voltage for EXT1 VDD_EXT1 1 7 1 8 2 5 3 0 3 6 DC Supply Voltage for EXT2 VDD_EXT2 1 7 1 8 2 5 3 0 3 6 DC Supply Voltage for CKO VDD_CKO 1 7 2 5 3 0 3 6 DC Supply Voltage for RTC VDD_RTC ...

Page 2011: ...DRAMA_IO 4 1 7 1 8 1 9 DC Supply Voltage for OneDRAMTM B port IO of MCP H type DC Supply Voltage for MCP DRAM0 IO VDD_ODRAMB_IO 4 H type VDD_MDDR0_IO 4 1 7 1 8 1 9 DC Supply Voltage for OneDRAMTM Core of MCP H type DC Supply Voltage for MCP DRAM0 Core VDD_ODRAM 5 H type VDD_MDDR0 5 1 7 1 8 1 9 DC Supply Voltage for Mobile DRAM IO of MCP H type DC Supply Voltage for MCP DRAM1 IO VDD_MDDR_IO 6 H typ...

Page 2012: ...1 05V 0 95V 0 95V VDD_INT 1 1V 1 1V 1 1V 1 1V 1 0V Caution In case over 800MHz VDD_ARM should be higher than VDD_INT 3 VDD_M1 M2 power depends on MCP voltage 4 In the MCP pin Name is VDDQa VDDQb 5 In the MCP pin Name is VDD 6 In the MCP pin Name is VDDQd 7 In the MCP pin Name is VDD 8 In the MCP pin Name is VCCQo 9 In the MCP pin Name is VCCo ...

Page 2013: ...lerant external voltage VDD Power On VDD 1 8V 3 6 V High Level Input Voltage Vih LVCMOS Interface 0 7VDD VDD V Low Level Input Voltage Vil LVCMOS Interface 0 0 3VDD V ΔV Hysteresis Voltage 0 1VDD V High Level Input Current Input Buffer 10 10 uA Iih Input Buffer with pull down Vin VDD VDD min 45 1 uA Low Level Input Current Input Buffer 10 10 uA Iil Input Buffer with pull up Vin VSS Vss min 45 1 uA...

Page 2014: ... 10 μA IIL Low level input current 10 10 μA Table 1 5 USB DC Electrical Characteristics Symbol Parameter Condition Minimum Maximum Unit VIH High level input voltage 2 0 V VIL Low level input voltage 0 8 V IIH High level input current Vin 3 3v 10 10 μA IIL Low level input current Vin 0 0v 10 10 μA VOH Static Output High 14 25Kohm to GND 2 8 3 6 V VOL Static Output Low 1 425Kohm to 3 6V 0 3 V VBUS V...

Page 2015: ...utput capacitance These factors determine the loading for external drivers and other load analyses 1 2 VDD_SYS 1 2 VDD_SYS tXTALCYC NOTE The clock input from the XTIpll pin Figure 1 1 XTIpll Clock Timing tEXTHIGH 1 2 VDD_SYS VIL VIL VIH VIH 1 2 VDD_SYS tEXTLOW tEXTCYC NOTE The clock input from the EXTCLK pin Figure 1 2 EXTCLK Clock Input Timing 1 8 ...

Page 2016: ...or crystal oscillator clock input tXTALCYC 40 ns High width for external clock input tEXTHIGH 20 ns Low width for external clock input tEXTLOW 20 ns APLL lock time tAPLL 100 usec MPLL lock time tMPLL_LT 400 XTIpll or EXTCLK EPLL lock time tEPLL_LT 3000 XTIpll or EXTCLK 1 9 VPLL lock time tVPLL_LT 400 XTIpll or EXTCLK EXTCLK tRESW nRESET Figure 1 3 Manual Reset Input Timing ...

Page 2017: ...ns 0ns 3 3V 2 5V 1 8V 0 6V 1 1V Power on transition 0ns 0ns Figure 1 4 Power On Reset Sequence Figure 1 4 OSC STABLE in indicates the time required for the oscillator pad to be stabilized Table 1 7 Power on Reset Timing Specifications VDDINT 1 1V 5 TA 25 to 85 C VDDSYS 3 3V 5 2 5V 0 25V 1 8V 0 15V Parameter Symbol Minimum Typical Maximum Unit tRESW 4 Reset assert time after clock stabilization XTI...

Page 2018: ...S5PC110_UM 1 ELECTRICAL DATA 1 5 ROM SRAM AC ELECTRICAL CHARACTERISTICS Figure 1 5 ROM SRAM Timing Tacs 0 Tcos 0 Tacc 2 Tcoh 0 Tcah 0 PMC 0 ST 0 DW 16 bit 1 11 ...

Page 2019: ... 3 48 8 33 ns ROM SRAM Chip Select 2 Delay tRCD 4 13 7 29 ns ROM SRAM Chip Select 3 Delay tRCD 3 14 7 22 ns ROM SRAM Chip Select 4 Delay tRCD 2 16 4 21 ns ROM SRAM Chip Select 5 Delay tRCD 2 30 4 53 ns ROM SRAM nOE Output Enable Delay tROD 2 78 5 46 ns ROM SRAM nWE Write Enable Delay tRWD 2 02 3 96 ns ROM SRAM Byte Enable Delay tRBED 2 95 6 52 ns ROM SRAM Output Data Delay tRDD 3 50 7 41 ns ROM SR...

Page 2020: ...S5PC110_UM 1 ELECTRICAL DATA 1 6 ONENAND AC ELECTRICAL CHARACTERISTICS Figure 1 6 OneNand Flash Timing 1 13 ...

Page 2021: ...AND ADRVALID Setup time to SMCLK tAVDS 4 ns OneNAND ADRVALID Hold time to SMCLK tAVDH 6 ns OneNAND Write Data Setup time to SMCLK tWDS 4 ns OneNAND Write Data Hold time to SMCLK tWDH 2 ns OneNAND WEn Setup time to SMCLK tWES 4 ns OneNAND WEn Hold time to SMCLK tWEH 6 ns OneNAND ADRVALID high to OEn low tAVDO 0 ns OneNAND Access time from CSn low tCE 76 ns OneNAND Asynchronous Access time from ADRV...

Page 2022: ...L DATA 1 15 Parameter Symbol Minimum Maximum Unit OneNAND Data Hold time tDH 0 ns OneNAND CSn Setup time tCS 0 ns OneNAND CSn Hold time tCH 0 ns OneNAND WEn Pulse width low tWPL 40 ns OneNAND WEn Pulse width high tWPH 30 ns ...

Page 2023: ... 0 TWRPH 1 ADDRESS Xm0 DATA HCLK tCLED tCLED tWED tWED tWDD tWDD tALED tWED tALED tWED tWDD TACLS tWDD HCLK TWRPH0 TWRPH 1 Xm0DATA HCLK TWRPH0 TWRPH 1 Xm0DATA RDATA tWED tWED tWDD tRED tRED tRDS tRDH tWDD WDATA Xm0 DATA HCLK Xm0FCLE Xm0FWEn Xm0FWEn Xm0FALE Xm0FWEn Xm0FREn Figure 1 7 NAND Flash Timing 1 16 ...

Page 2024: ...l Minimum Maximum Unit NFCON Chip Enable delay tCED 8 40 ns NFCON CLE delay tCLED 4 45 ns NFCON ALE delay tALED 5 36 ns NFCON Write Enable delay tWED 8 15 ns NFCON Read Enable delay tRED 8 21 ns NFCON Write Data delay tWDD 5 39 ns NFCON Read Data Setup requirement time tRDS 1 00 ns NFCON Read Data Hold requirement time tRDH 0 20 ns ...

Page 2025: ...S5PC110_UM 1 ELECTRICAL DATA 1 8 LPDDR1 MDDR SDRAM ELECTRICAL CHARACTERISTICS Figure 1 8 LPDDR1 SDRAM Read Write Timing Trp 2 Trcd 2 Tcl 2 DW 16 bit 1 18 ...

Page 2026: ...K tSAC 2 00 5 50 ns DDR SDRAM Row Precharge time tRP 18 00 ns DDR SDRAM RAS to CAS delay tRCD 18 00 ns DDR SDRAM Write recovery time tWR 12 00 ns DDR SDRAM Clock low level width tCL 0 45 0 55 tCK DDR SDRAM Read Preamble tRPRE 0 90 1 10 tCK DDR SDRAM Read Postamble tRPST 0 40 0 60 tCK DDR SDRAM Write Postamble time tWPST 0 40 0 60 tCK DDR SDRAM Clock to valid DQS In tDQSS 0 75 1 25 tCK DDR SDRAM DQ...

Page 2027: ...S5PC110_UM 1 ELECTRICAL DATA 1 20 1 9 LPDDR2 ELECTRICAL CHARACTERISTI TBD 1 10 MODEMIF AC ELECTRICAL CHARACTERISTICS For more information Refer to Section 8 6 S5PC110_Modem Interface user s manual ...

Page 2028: ...L DATA 1 11 LCD CONTROLLER AC ELECTRICAL CHARACTERISTICS VSYNC HSYNC VDEN Tf2hsetup Tf2hhold Tvspw Tvbpd Tvfpd HSYNC VCLK VD VDEN Tl2csetup Tvclkh Tvclk Tvclkl Tvdhold Tvdsetup Tve2hold Figure 1 9 LCD Controller Timing 1 21 ...

Page 2029: ... VSPW 1 Phclk 2 Vertical back porch delay Tvbpd VBPD 1 Phclk Vertical front porch dealy Tvfpd VFPD 1 Phclk Hsync setup to VCLK falling edge Tl2csetup 0 3 Pvclk VDEN setup to VCLK falling edge Tde2csetup 0 3 Pvclk VDEN hold from VCLK falling edge Tde2chold 0 3 Pvclk VD setup to VCLK falling edge Tvd2csetup 0 3 Pvclk VD hold from VCLK falling edge Tvd2chold 0 3 Pvclk VSYNC setup to HSYNC falling edg...

Page 2030: ...terface Signal Timing Constants VDDINT 1 1V 5 TA 25 to 85 C VDDlcd 1 7V 3 6V Parameter Symbol Minimum Typical Maximum Unit SYS_RS to SYS_CSn Low Tcssetup LCD_CS_SETUP 1 Pvclk SYS_CSn Low to SYS_WR Low Twrsetup LCD_WR_SETUP 1 Pvclk SYS_WE Pulse Width Twract LCD_WR_ACT 1 Pvclk SYS_WE Hight to SYS_CSn High Twrhold LCD_WR_HOLD 1 s Pvclk NOTE Internal VCLK period 1 23 ...

Page 2031: ...nvPolPCLK 1 CAM_PCLK_A CAM_PCLK_B CAM_VSYNC _A CAM_VSYNC_B CAM_PCLK_A CAM_PCLK_B CAM_VSYNC _A CAM_VSYNC_B Figure 1 11 Camera Interface VSYNC Timing XciPCLK XEINT 24 XciHREF XEINT 26 Tsshrefa Tsshrefb Thhrefa Thhrefb XciPCLK XEINT 24 XciHREF XEINT 26 Tsshrefa Tsshrefb Thhrefa Thhrefb InvPolPCLK 1 CAM_PCLK_A CAM_PCLK_B CAM_PCLK_A CAM_PCLK_B CAM_HREF_A CAM_HREF_B CAM_HREF_A CAM_HREF_B Figure 1 12 Cam...

Page 2032: ...put Hold time Thvsynca 1 35 PA 1 84 ns XciHREF CAM_HREF_A input Setup time Tsshrefa 3 15 PA 0 59 ns XciHREF CAM_HREF_A input Hold time Thhrefa 0 59 PA 3 15 ns XciDATA CAM_DATA_A input Setup time Tssdataa 0 75 PA 1 75 ns XciDATA CAM_DATA_A input Hold time Thdataa 1 75 PA 0 75 ns NOTE PA denotes period ns of CAM_PCLK_A Parameter Symbol Minimum Typ Maximum Unit XEINT 25 CAM_VSYNC_B input Setup time T...

Page 2033: ...ical Maximum Unit SD Command output Delay time tSDCD 1 0 14 0 ns SD Command input Setup time tSDCS 4 0 1 ns SD Command input Hold time tSDCH 0 1 ns SD Data output Delay time tSDDD 1 0 14 0 ns SD Data input Setup time tSDDS 4 0 2 ns tSDDH 0 1 ns SD Data input Hold time NOTE 1 2 This values are visible of the Rx Feedback Clock selections are enabled If the Rx Feedback Clock selection disabled setup ...

Page 2034: ... DATA 1 14 SPI AC ELECTRICAL CHARACTERISTICS SPICLK tSPIMIH tSPIMIS XspiMOSI MO XspiMOSI SI XspiMISO MI tSPIMOD tSPISIS tSPISIH XspiMISO SO tSPISOD XspiCS tSPICSSS tSPICSSD Figure 1 15 SPI Interface Timing CPHA 0 CPOL 1 1 27 ...

Page 2035: ...SPI MISO Slave Output Delay time tSPISOD 17 ns SPI nSS Master Output Delay time tSPICSSD 7 ns Ch 0 SPI nSS Slave Input Setup time tSPICSSS 5 ns SPI MOSI Master Output Delay time tSPIMOD 4 ns SPI MISO Master Input Setup time FB_CLK_SEL 00 13 ns SPI MISO Master Input Setup time FB_CLK_SEL 01 8 ns SPI MISO Master Input Setup time FB_CLK_SEL 10 3 ns SPI MISO Master Input Setup time FB_CLK_SEL 11 tSPIM...

Page 2036: ...me tSPISOD 18 ns SPI nSS Master Output Delay time tSPICSSD 8 ns Ch 0 SPI nSS Slave Input Setup time tSPICSSS 6 ns SPI MOSI Master Output Delay time tSPIMOD 5 ns SPI MISO Master Input Setup time FB_CLK_SEL 00 14 ns SPI MISO Master Input Setup time FB_CLK_SEL 01 9 ns SPI MISO Master Input Setup time FB_CLK_SEL 10 4 ns SPI MISO Master Input Setup time FB_CLK_SEL 11 tSPIMIS 1 ns SPI MISO Master Input ...

Page 2037: ...th tSCLLOW std 4 7 fast 1 3 us Bus free time between STOP and START tBUF std 4 7 fast 1 3 us START hold time tSTARTS std 4 0 fast 0 6 us SDA hold time tSDAH std 0 fast 0 std fast 0 9 us SDA setup time tSDAS std 250 fast 100 ns std 4 0 tSTOPH STOP setup time us fast 0 6 NOTE std refers to Standard Mode and fast refers to Fast Mode 1 The IIC data hold time tSDAH is minimum 0ns IIC data hold time is ...

Page 2038: ... 25 to 85 C VDDext 1 8V 10 load 35pF Parameter Symbol Minimum Maximum Unit TSI synchronization signal setup time tSS 3 ns TSI synchronization signal hold time tSH 3 ns TSI valid signal setup time tVS 3 ns TSI valid signal hold time tVH 3 ns TSI error signal setup time tES 3 ns TSI error signal hold time tEH 3 ns TSI input data setup time tDS 3 ns tDH 3 ns TSI input data hold time 1 31 ...

Page 2039: ...Section 13 SIZE BALL MAP ...

Page 2040: ...pe SIZE BALL MAP 3 1 3 1 Pin Assignment 3 1 3 1 1 Pin Assignment Diagram 596 ball FCFBGA POP 3 1 3 1 2 Pin Number Order 3 2 3 1 3 Power Pins 3 10 3 1 4 Pin Discription 3 13 3 1 5 Power Domain 3 39 3 1 6 Package Dimension 3 54 4 F type SIZE BALL MAP 4 1 4 1 Pin Assignment 4 1 4 1 1 Pin Assignment Diagram 596 ball FCFBGA POP 4 1 4 1 2 Pin Number Order 4 2 4 1 3 Power Pins 4 10 4 1 4 Pin Discription ...

Page 2041: ... 1 3 Power Pins 6 10 6 1 4 Pin Discription 6 13 6 1 5 Power Domain 6 39 6 1 6 Package Dimension 6 52 7 I type SIZE BALL MAP 7 1 7 1 Pin Assignment 7 1 7 1 1 Pin Assignment Diagram 596 ball FCFBGA POP 7 1 7 1 2 Pin Number Order 7 2 7 1 3 Power Pins 7 10 7 1 4 Pin Discription 7 13 7 1 5 Power Domain 7 39 7 1 6 Package Dimension 7 54 ...

Page 2042: ...nsion 596 FCFBGA Side View 3 55 Figure 4 1 S5PC110 Pin Assignment 596 FCFBGA Bottom View 4 1 Figure 4 2 S5PC110 Package Dimension 596 FCFBGA Top View 4 53 Figure 4 3 S5PC110 Package Dimension 596 FCFBGA Side View 4 54 Figure 5 1 S5PC110 Pin Assignment 596 FCFBGA Bottom View 5 1 Figure 5 2 S5PC110 Package Dimension 596 FCFBGA Top View 5 55 Figure 5 3 S5PC110 Package Dimension 596 FCFBGA Side View 5...

Page 2043: ... Pin to Ball Assignment 1 2 2 11 Table 2 10 S5PC110 Power Pin to Ball Assignment 2 2 2 13 Table 3 1 S5PC110 596 FCFBGA Pin Assignment Pin Number Order 1 8 3 2 Table 3 2 S5PC110 596 FCFBGA Pin Assignment Pin Number Order 2 8 3 3 Table 3 3 S5PC110 596 FCFBGA Pin Assignment Pin Number Order 3 8 3 4 Table 3 4 S5PC110 596 FCFBGA Pin Assignment Pin Number Order 4 8 3 5 Table 3 5 S5PC110 596 FCFBGA Pin A...

Page 2044: ...r 4 8 6 5 Table 6 5 S5PC110 596 FCFBGA Pin Assignment Pin Number Order 5 8 6 6 Table 6 6 S5PC110 596 FCFBGA Pin Assignment Pin Number Order 6 8 6 7 Table 6 7 S5PC110 596 FCFBGA Pin Assignment Pin Number Order 7 8 6 8 Table 6 8 S5PC110 596 FCFBGA Pin Assignment Pin Number Order 8 8 6 9 Table 6 9 S5PC110 Power Pin to Ball Assignment 1 2 6 10 Table 6 10 S5PC110 Power Pin to Ball Assignment 2 2 6 12 T...

Page 2045: ...S5PC110_UM 1 B TYPE SIZE BALL MAP 1 B TYPE SIZE BALL MAP 1 1 PIN ASSIGNMENT 1 1 1 PIN ASSIGNMENT DIAGRAM 596 BALL FCFBGA POP Figure 1 1 S5PC110 Pin Assignment 596 FCFBGA Bottom View 1 1 ...

Page 2046: ...A7 VDD_ODRAMA_IO A27 VSS B20 NC11 C13 POP_A6_A A8 NC21 B1 VSS B21 POP_UDQS_A C14 POP_A8_A A9 NC19 B2 POP_DQ2_A B22 NC13 C15 POP_A9_A A10 POP_BA1_A B3 NC3 B23 VSS C16 POP_INTB_A A11 POP_RASB_A B4 POP_DQ3_A B24 POP_DQ14_A C17 NC20 A12 POP_CLKB_A B5 NC6 B25 XVVD_10 C18 POP_DQ9_A A13 NC17 B6 POP_DQ6_A B26 XVVD_13 C19 POP_DQ11_A A14 NC18 B7 NC8 B27 VSS C20 POP_DQ15_A A15 POP_A7_A B8 VSS C1 NC2 C21 NC14...

Page 2047: ...D_ODRAM F18 XMIPISDN2 G13 XMIPIMDN2 D9 XUOTGVBUS E25 XVVD_7 F19 XMIPISDN3 G14 XMIPIMDN3 D10 XUHOSTREXT E26 XVVD_14 F20 XVVD_20 G15 XMIPISDN0 D11 VDD_UHOST_A E27 XVVD_22 F21 XVVD_9 G16 XMIPISDP1 D12 VSS_UHOST_A F1 XCIPCLK F22 XVVCLK G17 XMIPISDPCLK D13 POP_CKE_A F2 XI2C1SCL F24 VDD_ODRAM G18 XMIPISDP2 D14 XADCAIN_9 F3 XCIFIELD F25 VSS G19 XMIPISDP3 D15 XADCAIN_1 F4 VDD_MDDR F26 VDD_ONAND G20 XVVD_3...

Page 2048: ... XUSBXTI H9 VSS_UOTG_D J3 XCIDATA_7 K11 XUTXD_2 L7 VDD_SYS1 H10 VDD_UOTG_D J4 XI2C2SCL K12 VDD_UHOST_D L8 VDD_ALIVE H11 VSS_UOTG_A J6 XUOTGREXT K13 VDD_MIPI_PLL L10 VDD_KEY H12 VSS_UHOST_D J7 XCIDATA_0 K14 XMIPIVREG_0P4V L11 XURXD_3 H13 VSS_MIPI J8 VDD_SYS0 K15 VDD_MIPI_A L12 XUTXD_3 H14 VDD_MIPI_D J20 VDD_AUD K16 XADCAIN_6 L13 VSS_UHOST_AC H15 VDD_MIPI_D J21 VSS_DAC K17 XADCAIN_5 L14 XVHSYNC H16 ...

Page 2049: ...25 XM0DATA_3 P25 XM0DATA_4 M2 XEINT_14 M26 XHDMITX1N N26 XHDMITX0N P26 XHDMITXCN M3 XEINT_19 M27 XHDMITX1P N27 XHDMITX0P P27 XHDMITXCP M4 XCIDATA_1 N1 VDD_MDDR_IO P1 VSS R1 VDD_ARM M6 XCIHREF N2 XEINT_17 P2 XEINT_12 R2 VDD_ARM M7 VDD_EPLL N3 XEINT_16 P3 XEINT_7 R3 VDD_ARM M8 VDD_SYS0 N4 VDD_MDDR P4 XEINT_27 R4 VDD_ARM M10 XI2C2SDA N6 VDD_APLL P6 VSS_APLL R6 VDD_ARM M11 VDD_INT N7 VSS_EPLL P7 VSS_V...

Page 2050: ... XJTRSTN V15 VDD_INT R27 XM0DATA_10 T24 Xpcm2SOUT U20 VDD_M0 V16 VDD_INT T1 VSS T25 Xpcm2EXTCLK U21 XI2S0LRCK V17 VDD_INT T2 XEINT_30 T26 VDD_MDDR U22 XM0CSN_0 V18 XJTMS T3 XEINT_5 T27 VDD_ONAND_IO U24 XEFFSOURCE_0 V20 XM0ADDR_2 T4 VSS U1 VDD_MDDR_IO U25 VSS V21 XM0FRNB_2 T6 VDD_MPLL U2 XEINT_10 U26 XM0DATA_1 V22 XM0WAITN T7 VSS_MPLL U3 XEINT_23 U27 XM0DATA_9 V24 Xpcm2SCLK T8 EPLL_FILTER U4 VSS V1...

Page 2051: ...LKO W24 XM0CSN_1 Y18 VDD_EXT0 AA13 VSS AB8 XI2C0SDA W25 XM0FALE Y19 XMMC3CMD AA14 XURXD_1 AB9 XURTSN_1 W26 Xpcm2FSYNC Y20 XMMC2CDN AA15 VSS AB10 XURTSN_0 W27 XM0FREN Y21 XM0BEN_1 AA16 XPWMTOUT_3 AB11 XUTXD_0 Y1 XOM_4 Y22 XMMC2CMD AA17 XMMC3DATA_3 AB12 XUCTSN_1 Y2 XOM_2 Y24 XM0CSN_5 AA18 XMMC2CLK AB13 XUTXD_1 Y3 XOM_1 Y25 XM0CSN_4 AA19 XMMC2DATA_0 AB14 XURXD_0 Y4 XOM_0 Y26 XM0FCLE AA20 XMSMADDR_10 ...

Page 2052: ... XNWRESET AD18 XMSMADDR_1 AE13 XMSMWEN AF6 VDD_INT AC3 VDD_ODRAM AD19 XMSMADDR_8 AE14 XMSMDATA_3 AF7 VSS AC25 XM0ADDR_0 AD20 XMSMADDR_6 AE15 XMSMDATA_15 AF8 XMMC0CLK AC26 XM0FRNB_1 AD21 NC AE16 XMSMDATA_13 AF9 XMMC1DATA_2 AC27 XM0FRNB_3 AD22 NC AE17 XMSMADDR_3 AF10 XMMC0DATA_3 AD1 VSS AD25 VDD_ODRAMB_IO AE18 XMSMADDR_12 AF11 XMMC0DATA_1 AD2 XEINT_4 AD26 XM0ADDR_6 AE19 XMSMADDR_7 AF12 XMSMADVN AD3 ...

Page 2053: ...ADDR_4 AG14 XMSMDATA_2 AF22 XM0ADDR_13 AG15 VSS AF23 XM0ADDR_12 AG16 VDD_ODRAM AF24 XM0ADDR_8 AG17 XMSMADDR_13 AF25 XM0ADDR_7 AG18 XMSMDATA_6 AF26 XM0ADDR_15 AG19 XMSMADDR_0 AF27 VSS AG20 VDD_ODRAMB_IO AG1 VSS AG21 VSS AG2 VSS AG22 XMSMADDR_9 AG3 VDD_ODRAMB_IO AG23 XMSMADDR_11 AG4 XSPIMOSI_1 AG24 XJDBGSEL AG5 XSPICLK_0 AG25 VDD_ODRAMB_IO AG6 VDD_INT AG26 VSS AG7 VSS AG27 VSS AG8 VDD_ODRAMB_IO AG9 ...

Page 2054: ...H8 L18 EXT1 VDD_EXT2 AB17 EXT2 VDD_CKO N10 RTC CLKO VDD_RTC N8 RTC Internal Logic VDD_INT AD6 AE6 AF6 AG6 M11 M12 M13 M14 M15 M16 T17 U17 V14 V15 V16 V17 Internal logic VDD_ARM R1 R2 R3 R4 R6 R7 R8 R10 R11 R12 T10 T11 T12 U11 Cortex A8 core VDD_ALIVE K8 L8 Alive logic Analog High Speed VDD_ADC H17 P20 ADC VDD_DAC_A K20 DAC Analog VDD_DAC J22 DAC Digital VDD_MIPI_A K15 MIPI 1 8V VDD_MIPI_D H14 H15 ...

Page 2055: ... M7 EPLL MCP VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAM A VDDQ VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM B VDDQ VDD_ODRAM A16 AC3 AG16 E3 F24 OneDRAM CORE VDD VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 DDR VDDQ VDD_MDDR AB4 AB25 F4 H25 N4 T26 DDR CORE VDD VDD_ONAND_IO J26 T27 OneNAND VCCQ VDD_ONAND AA26 F26 OneNAND VCC ...

Page 2056: ...2 AG7 AG15 AG21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H...

Page 2057: ...UART_2_RTSn O GPI I L Signal I O Description UART_0_RXD I UART 0 receives data input UART_0_TXD O UART 0 transmits data output UART_0_CTSn I UART 0 clear to send input signal UART_0_RTSn O UART 0 request to send output signal UART_1_RXD I UART 1 receives data input UART_1_TXD O UART 1 transmits data output UART_1_CTSn I UART 1 clear to send input signal UART_1_RTSn O UART 1 request to send output ...

Page 2058: ..._1_MISO IO GPI I L XSPIMOSI_1 SPI_1_MOSI IO GPI I L Signal I O Description SPI_0_CLK IO SPI clock for channel 0 SPI_0_nSS IO SPI chip select only for slave mode for channel 0 SPI_0_MISO IO SPI master input slave output line for channel 0 SPI_0_MOSI IO SPI master output slave input line for channel 0 SPI_1_CLK IO SPI clock for channel 1 SPI_1_nSS IO SPI chip select only for slave mode for channel 1...

Page 2059: ...el 1 I2S_1_LRCK IO IIS bus channel select clock for channel 1 I2S_1_SDI I IIS bus serial data input for channel 1 I2S_1_SDO O IIS bus serial data output for channel 1 PCM_2_SCLK O PCM Serial Shift Clock for channel 2 PCM_2_EXTCLK I PCM External Clock for channel 2 PCM_2_FSYNC O PCM Sync indicating start of word for channel 2 PCM_2_SIN I PCM Serial Data Input for channel 2 PCM_2_SOUT O PCM Serial D...

Page 2060: ... AC97SDO O AC link Serial Data output to AC97 Codec I2S_2_SCLK IO IIS bus serial clock for channel 2 I2S_2_CDCLK IO IIS CODEC system clock for channel 2 I2S_2_LRCK IO IIS bus channel select clock for channel 2 I2S_2_SDI I IIS bus serial data input for channel 2 I2S_2_SDO O IIS bus serial data output for channel 2 ...

Page 2061: ...XI2C1SDA I2C1_SDA IO GPI I L XI2C1SCL I2C1_SCL IO GPI I L XI2C2SDA I2C2_SDA IO IEM_SCLK IO GPI I L XI2C2SCL I2C2_SCL IO IEM_SPWI IO GPI I L Signal I O Description TOUT_0 1 2 3 O PWM Timer Output I2C0_SDA IO IIC bus clock for channel 0 I2C0_SCL IO IIC bus data for channel 0 I2C1_SDA IO IIC bus clock for channel 1 I2C1_SCL IO IIC bus data for channel 1 I2C2_SDA IO IIC bus clock for channel 0 I2C2_SC...

Page 2062: ...ATA 5 I GPI I L XCIDATA_6 CAM_A_DATA 6 I GPI I L XCIDATA_7 CAM_A_DATA 7 I GPI I L XCICLKENB CAM_A_CLKOUT O GPI I L XCIFIELD CAM_A_FIELD I GPI I L Signal I O Description CAM_A_PCLK I Pixel Clock driven by the Camera processor A CAM_A_VSYNC I Vertical Sync driven by the Camera processor A CAM_A_HREF I Horizontal Sync driven by the Camera processor A CAM_A_DATA 7 0 I Pixel Data for YCbCr in 8 bit mod...

Page 2063: ... SYS_VD 7 IO VEN_DATA 7 O GPI I L XVVD_8 LCD_VD 8 O SYS_VD 8 IO V656_DATA 0 O GPI I L XVVD_9 LCD_VD 9 O SYS_VD 9 IO V656_DATA 1 O GPI I L XVVD_10 LCD_VD 10 O SYS_VD 10 IO V656_DATA 2 O GPI I L XVVD_11 LCD_VD 11 O SYS_VD 11 IO V656_DATA 3 O GPI I L XVVD_12 LCD_VD 12 O SYS_VD 12 IO V656_DATA 4 O GPI I L XVVD_13 LCD_VD 13 O SYS_VD 13 IO V656_DATA 5 O GPI I L XVVD_14 LCD_VD 14 O SYS_VD 14 IO V656_DATA...

Page 2064: ...ect i80 System interface SYS_RS O Register State Select Signal for LCD Indirect i80 System interface SYS_WE O Write Enable for LCD Indirect i80 System interface SYS_VD 23 0 IO Video data input output for LCD Indirect i80 System interface SYS_OE O Output Enable for LCD Indirect i80 System interface VEN_HSYNC O Horizontal Sync Signal for 601 interface VEN_VSYNC O Vertical Sync Signal for 601 interfa...

Page 2065: ..._0_DATA 4 IO GPI I L XMMC1DATA_1 SD_1_DATA 1 IO SD_0_DATA 5 IO GPI I L XMMC1DATA_2 SD_1_DATA 2 IO SD_0_DATA 6 IO GPI I L XMMC1DATA_3 SD_1_DATA 3 IO SD_0_DATA 7 IO GPI I L XMMC2CLK SD_2_CLK O GPI I L XMMC2CMD SD_2_CMD IO GPI I L XMMC2CDN SD_2_CDn I GPI I L XMMC2DATA_0 SD_2_DATA 0 IO GPI I L XMMC2DATA_1 SD_2_DATA 1 IO GPI I L XMMC2DATA_2 SD_2_DATA 2 IO GPI I L XMMC2DATA_3 SD_2_DATA 3 IO GPI I L XMMC...

Page 2066: ...nel 1 SD_1_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 1 SD_2_CLK O CLOCK SD SDIO MMC card interface channel 2 SD_2_CMD IO COMMAND RESPONSE SD SDIO MMC card interface channel 2 SD_2_CDn I CARD DETECT SD SDIO MMC card interface channel 2 SD_2_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 2 SD_3_CLK O CLOCK SD SDIO MMC card interface channel 3 SD_3_CMD IO COMMAND RESPONSE SD SD...

Page 2067: ... GPI I L XEINT_13 I HDMI_HPD I GPI I L XEINT_14 I GPI I L XEINT_15 I GPI I L XEINT_16 I KP_COL 0 IO GPI I L XEINT_17 I KP_COL 1 IO GPI I L XEINT_18 I KP_COL 2 IO GPI I L XEINT_19 I KP_COL 3 IO GPI I L XEINT_20 I KP_COL 4 IO GPI I L XEINT_21 I KP_COL 5 IO GPI I L XEINT_22 I KP_COL 6 IO GPI I L XEINT_23 I KP_COL 7 IO GPI I L XEINT_24 I KP_ROW 0 I GPI I L XEINT_25 I KP_ROW 1 I GPI I L XEINT_26 I KP_R...

Page 2068: ...10_UM 1 B TYPE SIZE BALL MAP 1 24 Signal I O Description XEINT 31 0 I External interrupts KP_COL 7 0 O KeyIF_Column_data 7 0 KP_ROW 7 0 I KeyIF_Row_data 7 0 HDMI_CEC IO HDMI CEC port HDMI_HPD I HDMI Hot plug ...

Page 2069: ...al I O Description I2S_0_SCLK IO IIS bus serial clock for channel 0 Lower Power Audio I2S_0_CDCLK IO IIS CODEC system clock for channel 0 Lower Power Audio I2S_0_LRCK IO IIS bus channel select clock for channel 0 Lower Power Audio I2S_0_SDI I IIS bus serial data input for channel 0 Lower Power Audio I2S_0_SDO 2 0 O IIS bus serial data output for channel 0 Lower Power Audio PCM_0_SCLK O PCM Serial ...

Page 2070: ...I L XMSMADDR_10 MSM_ADDR 10 I CAM_B_HREF I SROM_ADDR_16to22 2 O MHL_D3 O GPI I L XMSMADDR_11 MSM_ADDR 11 I CAM_B_FIELD I SROM_ADDR_16to22 3 O MHL_D4 O GPI I L XMSMADDR_12 MSM_ADDR 12 I CAM_B_CLKOUT O SROM_ADDR_16to22 4 O MHL_D5 O GPI I L XMSMADDR_13 MSM_ADDR 13 I KP_COL 0 I O SROM_ADDR_16to22 5 O MHL_D6 O GPI I L XMSMDATA_0 MSM_DATA 0 I O KP_COL 1 I O CF_DATA 0 I O MHL_D7 O GPI I L XMSMDATA_1 MSM_...

Page 2071: ...KP_ROW 13 I SROM_ADDR_16to22 6 O MHL_DE O GPI I L Signal I O Description MSM_ADDR 13 0 I MODEM MSM IF Address MSM_ADDR 13 should be 0 MSM_DATA 15 0 IO MODEM MSM IF Data MSM_CSn I MODEM MSM IF Chip Select MSM_WEn I MODEM MSM IF Write enable MSM_Rn I MODEM MSM IF Read enable MSM_IRQn O MODEM MSM IF Interrupt to MODEM MSM_ADVN I MODEM MSM IF Address Valid from MODEM Chip CAM_B_DATA 7 0 I Pixel Data d...

Page 2072: ... TS_CLK I TSI system clock 66MHz TS_SYNC I TSI synchronization control signal TS_VAL I TSI valid signal TS_DATA I TSI input data TS_ERROR I TSI error indicate signal MHL_D0 O MHL Data 0 MHL_D1 O MHL Data 1 MHL_D2 O MHL Data 2 MHL_D3 O MHL Data 3 MHL_D4 O MHL Data 4 MHL_D5 O MHL Data 5 MHL_D6 O MHL Data 6 MHL_D7 O MHL Data 7 MHL_D8 O MHL Data 8 MHL_D9 O MHL Data 9 MHL_D10 O MHL Data 10 MHL_D11 O MH...

Page 2073: ...110_UM 1 B TYPE SIZE BALL MAP 1 29 Signal I O Description MHL_D22 O MHL Data 22 MHL_D23 O MHL Data 23 MHL_HSYNC O MHL Hsync MHL_IDCK O MHL Interface Data Clock MHL_VSYNC O MHL Vsync MHL_DE O MHL Data Enable ...

Page 2074: ...LE O ONANDXL_ADDRVALID O Func3 O L XM0FALE NF_ALE O ONANDXL_SMCLK O Func3 O L XM0FWEN NF_FWEn O ONANDXL_RPn O Func3 O H XM0FREN NF_FREn O Func3 O H XM0FRNB_0 NF_RnB 0 I ONANDXL_INT 0 I Func3 I XM0FRNB_1 NF_RnB 1 I ONANDXL_INT 1 I Func3 I XM0FRNB_2 NF_RnB 2 I Func3 I XM0FRNB_3 NF_RnB 3 I Func3 I XM0ADDR_0 EBI_ADDR 0 O Func0 O L XM0ADDR_1 EBI_ADDR 1 O Func0 O L XM0ADDR_2 EBI_ADDR 2 O Func0 O L XM0AD...

Page 2075: ...5 EBI_DATA 15 IO Func0 O L Signal I O Description SROM_CSn 5 4 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 3 2 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 1 0 O Memory Port 0 SROM Chip select support up to 2 memory bank EBI_OEn O Memory Port 0 SROM OneNAND Output Enable EBI_WEn O Memory Port 0 SROM OneNAND Write Enable EBI_BEn 1 0 O Memory Port 0...

Page 2076: ... O Memory Port 0 NAND Chip Select bank 2 NFCSn 3 O Memory Port 0 NAND Chip Select bank 3 ONANDXL_ADDRVALID O OneNANDXL Flash Address valid ONANDXL_SMCLK O OneNANDXL Flash clock ONANDXL_RPn O OneNANDXL Flash reset ONANDXL_INT 1 0 I OneNANDXL Flash Interrupt signal from OneNAND Device POP_CEB_O I POP OneNAND Chip Enable ...

Page 2077: ...3 IO Memory port 1DRAM Data Differential Strobe neg 4bit XM1DQM_0 XM1DQM_3 IO Memory port 1DRAM Data Mask 4bit XM1CKE_0 XM1CKE_1 IO Memory port 1DRAM Clock Enable 2bit XM1SCLK IO Memory port 1DRAM Clock XM1nSCLK IO Memory port 1DRAM Inverted Clock of Xm1SCLK XM1CSn_0 XM1CSn_1 IO Memory port 1DRAM Chip Select support up to 2 memory bank 2bit XM1RASn IO Memory port 1DRAM Row Address Strobe XM1CASn I...

Page 2078: ...3 IO Memory port 2DRAM Data Differential Strobe neg 4bit XM2DQM_0 XM2DQM_3 IO Memory port 2DRAM Data Mask 4bit XM2CKE_0 XM2CKE_1 IO Memory port 2DRAM Clock Enable 2bit XM2SCLK IO Memory port 2DRAM Clock XM2nSCLK IO Memory port 2DRAM Inverted Clock of Xm1SCLK XM2CSn_0 XM2CSn_1 IO Memory port 2DRAM Chip Select support up to 2 memory bank 2bit XM2RASn IO Memory port 2DRAM Row Address Strobe XM2CASn I...

Page 2079: ...gic Pull down resistor is connected XJTDI I XjTDI TAP Controller Data Input is the serial input for test instructions and data Pull up resistor is connected XJTDO O XjTDO TAP Controller Data Output is the serial output for test instructions and data XJDBGSEL I JTAG selection 0 CORTEXA8 Core JTAG 1 Peripherals JTAG RESET etc Dedicated Ball Name I O Description XOM_0 XOM_5 I Operating Mode control s...

Page 2080: ...nal capacitor connection XHDMITX0P O HDMI Phy TX0 P XHDMITX0N O HDMI Phy TX0 N XHDMITX1P O HDMI Phy TX1 P XHDMITX1N O HDMI Phy TX1 N XHDMITX2P O HDMI Phy TX2 P XHDMITX2N O HDMI Phy TX2 N XHDMITXCP O HDMI Phy TX Clock P XHDMITXCN O HDMI Phy TX Clock N XHDMIREXT I HDMI Phy Registance XHDMIXTI I HDMI crystal input XHDMIXTO O HDMI crystal output XMIPIMDP0 IO Master DATA LANE0 DP for MIPI DPHY XMIPIMDP...

Page 2081: ...PI DPHY XMIPISDPCLK IO Slave CLK Lane DP for MIPI DPHY XMIPISDNCLK IO Slave CLK Lane DN for MIPI DPHY XMIPIVREG_0P4V IO Regulator capacitor for MIPI DPHY USB OTG USB HOST 1 1 Dedicated Ball Name I O Description XUOTGDRVVUBS O USB OTG charge pump enable XUHOSTPWREN O USB HOST charge pump enable XUHOSTOVERCUR I USB HOST over current flag XUOTGDP IO USB OTG Data pin DATA XUOTGREXT IO USB OTG External...

Page 2082: ...IO POP_A DRAM CLK differential system clock POP_CKE_A IO POP_A DRAM Clock Enable POP_CSB_A IO POP_A DRAM Chip Select POP_RASB_A IO POP_A DRAM Row Address Strobe POP_CASB_A IO POP_A DRAM Column Address Strobe POP_WEB_A IO POP_A DRAM Write Enable POP_BA0_A POP_BA1_A IO POP_A DRAM Bank Address POP_LDM_A IO POP_A DRAM Lower data input mask POP_LDQS_A IO POP_A DRAM Lower data strobe POP_UDM_A IO POP_A ...

Page 2083: ...6 K16 XADCAIN_7 L15 XADCAIN_8 D16 XADCAIN_9 D14 VDD_ADC H17 P20 VSS_ADC H18 N20 DAC XDACCOMP K25 XDACIREF K22 XDACOUT K24 XDACVREF L22 VDD_DAC_A K20 VSS_DAC_A K21 VDD_DAC J22 VSS_DAC J21 MIPI DPHY XMIPIMDN0 G10 XMIPIMDN1 F11 XMIPIMDN2 G13 XMIPIMDN3 G14 XMIPIMDNCLK G12 XMIPIMDP0 F10 XMIPIMDP1 G11 XMIPIMDP2 F13 XMIPIMDP3 F14 XMIPIMDPCLK F12 XMIPISDN0 G15 XMIPISDN1 F16 XMIPISDN2 F18 XMIPISDN3 F19 XMI...

Page 2084: ...PLL K13 VSS_MIPI H13 H16 HDMI PHY XHDMIREXT P22 XHDMITX0N N26 XHDMITX0P N27 XHDMITX1N M26 XHDMITX1P M27 XHDMITX2N L26 XHDMITX2P L27 XHDMITXCN P26 XHDMITXCP P27 XHDMIXTI T22 XHDMIXTO R22 VDD_HDMI M22 VDD_HDMI_PLL N21 VDD_HDMI_OSC L20 VSS_HDMI M21 VSS_HDMI_PLL N22 VSS_HDMI_OSC L21 USB OTG XUOTGDM F6 XUOTGDP G6 XUOTGID D8 XUOTGREXT J6 XUOTGVBUS D9 VDD_UOTG_A F9 VDD_UOTG_D H10 VSS_UOTG_A H11 VSS_UOTG_...

Page 2085: ...SS_UOTG_D H9 USB HOST XUHOSTDM G8 XUHOSTDP F8 XUHOSTREXT D10 VDD_UHOST_A D11 VDD_UHOST_D K12 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 APLL VDD_APLL N6 VSS_APLL P6 MPLL VDD_MPLL T6 VSS_MPLL T7 VPLL VDD_VPLL P8 VSS_VPLL P7 EPLL VDD_EPLL M7 VSS_EPLL N7 EPLL_FILTER T8 ...

Page 2086: ...DDR_11 AE26 XM0ADDR_12 AF23 XM0ADDR_13 AF22 XM0ADDR_14 AE23 XM0ADDR_15 AF26 XM0ADDR_2 V20 XM0ADDR_3 W21 XM0ADDR_4 W22 XM0ADDR_5 AD27 XM0ADDR_6 AD26 XM0ADDR_7 AF25 XM0ADDR_8 AF24 XM0ADDR_9 AE22 XM0BEN_0 AA24 XM0BEN_1 Y21 XM0CSN_0 U22 XM0CSN_1 W24 XM0CSN_2 AE24 XM0CSN_3 AA25 XM0CSN_4 Y25 XM0CSN_5 Y24 XM0DATA_0 V25 XM0DATA_1 U26 XM0DATA_10 R27 XM0DATA_11 R25 XM0DATA_12 P24 XM0DATA_13 M25 XM0DATA_14 J...

Page 2087: ...ATA_RDN AB26 XM0FALE W25 XM0FCLE Y26 XM0FREN W27 XM0FRNB_0 H26 XM0FRNB_1 AC26 XM0FRNB_2 V21 XM0FRNB_3 AC27 XM0FWEN AA27 XM0OEN G27 XM0WAITN V22 XM0WEN G26 VDD_M0 T20 U20 LCD XVHSYNC L14 XVSYS_OE G21 XVVCLK F22 XVVD_0 D20 XVVD_1 D21 XVVD_10 B25 XVVD_11 G24 XVVD_12 G22 XVVD_13 B26 XVVD_14 E26 XVVD_15 D27 XVVD_16 C25 XVVD_17 H22 XVVD_18 C26 XVVD_19 G25 XVVD_2 D22 XVVD_20 F20 ...

Page 2088: ...VD_9 F21 XVVDEN D19 XVVSYNC D18 XVVSYNC_LDI H24 VDD_LCD H19 CAMERA XCICLKENB H3 XCIDATA_0 J7 XCIDATA_1 M4 XCIDATA_2 G2 XCIDATA_3 H2 XCIDATA_4 H1 XCIDATA_5 G3 XCIDATA_6 J2 XCIDATA_7 J3 XCIFIELD F3 XCIHREF M6 XCIPCLK F1 XCIVSYNC K7 VDD_CAM H7 AUDIO XI2S0CDCLK M17 XI2S0LRCK U21 XI2S0SCLK N17 XI2S0SDI R24 XI2S0SDO_0 M24 XI2S0SDO_1 R20 XI2S0SDO_2 P18 XI2S1CDCLK T21 XI2S1LRCK R21 ...

Page 2089: ... AG19 XMSMADDR_1 AD18 XMSMADDR_10 AA20 XMSMADDR_11 AG23 XMSMADDR_12 AE18 XMSMADDR_13 AG17 XMSMADDR_2 AE20 XMSMADDR_3 AE17 XMSMADDR_4 AF21 XMSMADDR_5 AE21 XMSMADDR_6 AD20 XMSMADDR_7 AE19 XMSMADDR_8 AD19 XMSMADDR_9 AG22 XMSMADVN AF12 XMSMCSN AD14 XMSMDATA_0 AG11 XMSMDATA_1 AF14 XMSMDATA_10 AD15 XMSMDATA_11 AG13 XMSMDATA_12 AF15 XMSMDATA_13 AE16 XMSMDATA_14 AF16 XMSMDATA_15 AE15 XMSMDATA_2 AG14 XMSMD...

Page 2090: ...MSMRN AD13 XMSMWEN AE13 VDD_MODEM AA21 KEY XEINT_16 N3 XEINT_17 N2 XEINT_18 W4 XEINT_19 M3 XEINT_20 V2 XEINT_21 L3 XEINT_22 K1 XEINT_23 U3 XEINT_24 L2 XEINT_25 V4 XEINT_26 K3 XEINT_27 P4 XEINT_28 K2 XEINT_29 L4 XEINT_30 T2 XEINT_31 K4 VDD_KEY L10 System 0 XXTI AB2 XXTO AB3 XOM_0 Y4 XOM_1 Y3 XOM_2 Y2 XOM_3 AA6 XOM_4 Y1 XOM_5 AA2 XPWRRGTON AA7 XNRESET AB6 XNRSTOUT Y7 ...

Page 2091: ...VBUS F7 XUHOSTPWREN D6 XUHOSTOVERCUR H6 XDDR2SEL G7 XUSBXTI L6 XUSBXTO K6 XJTRSTN U18 XJTMS V18 XJTCK W20 XJTDI T18 XJTDO R18 XJDBGSEL AG24 VDD_SYS0 J8 M8 P21 System 1 XEINT_8 Y6 XEINT_9 V6 XEINT_10 U2 XEINT_11 AE2 XEINT_12 P2 XEINT_13 W3 XEINT_14 M2 XEINT_15 W1 VDD_SYS1 L7 External Peri 0 XMMC0CDN AG10 XMMC0CLK AF8 XMMC0CMD AD11 XMMC0DATA_0 AE11 XMMC0DATA_1 AF11 XMMC0DATA_2 AD12 ...

Page 2092: ...PICSN_0 AF4 XSPIMISO_0 AE3 XSPIMOSI_0 AE5 XURXD_0 AB14 XUTXD_0 AB11 XUCTSN_0 AE12 XURTSN_0 AB10 XURXD_1 AA14 XUTXD_1 AB13 XUCTSN_1 AB12 XURTSN_1 AB9 XI2C0SDA AB8 XI2C0SCL AD7 XPWMTOUT_0 Y16 XPWMTOUT_1 AB16 XPWMTOUT_2 AD9 XPWMTOUT_3 AA16 VDD_EXT0 Y18 External Peri 1 XMMC2CDN Y20 XMMC2CLK AA18 XMMC2CMD Y22 XMMC2DATA_0 AA19 XMMC2DATA_1 AA22 XMMC2DATA_2 AB22 XMMC2DATA_3 AB21 XI2C1SCL F2 XI2C1SDA H4 XI...

Page 2093: ...3 L12 VDD_EXT1 H8 L18 External Peri 2 XMMC3CDN Y15 XMMC3CLK AB20 XMMC3CMD Y19 XMMC3DATA_0 AB18 XMMC3DATA_1 Y17 XMMC3DATA_2 AB15 XMMC3DATA_3 AA17 XSPICLK_1 AF3 XSPICSN_1 AF5 XSPIMISO_1 AE4 XSPIMOSI_1 AG4 VDD_EXT2 AB17 RTC Clock Out XRTCCLKO AB7 VDD_CKO N10 RTC XRTCXTI AA3 XRTCXTO AA4 VDD_RTC N8 EFUSE Security XEFFSOURCE_0 U24 ...

Page 2094: ...50 Internal Power Power Domain Ball Name Ball No Internal Internal Logic VDD_INT AD6 AE6 AF6 AG6 M11 M12 M13 M14 M15 M16 T17 U17 V14 V15 V16 V17 ARM Cortex A8 VDD_ARM R1 R2 R3 R4 R6 R7 R8 R10 R11 R12 T10 T11 T12 U11 Alive VDD_ALIVE K8 L8 ...

Page 2095: ..._A6_A C13 POP_A7_A A15 POP_A8_A C14 POP_A9_A C15 POP_A10_A B10 POP_A11_A B13 POP_A12_A C12 POP_BA0_A B11 POP_BA1_A A10 POP_CASB_A C11 POP_RASB_A A11 POP_WEB_A B14 POP_CKE_A D13 POP_CLK_A B12 POP_CLKB_A A12 POP_CSB_A C10 POP_DQ0_A D2 POP_DQ1_A C2 POP_DQ2_A B2 POP_DQ3_A B4 POP_DQ4_A C5 POP_DQ5_A A5 POP_DQ6_A B6 POP_DQ7_A C6 POP_DQ8_A B18 POP_DQ9_A C18 POP_DQ10_A A19 POP_DQ11_A C19 POP_DQ12_A A23 ...

Page 2096: ...1 VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAM B IO Power POP_INTB_B AF19 VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM Core Power VDD_ODRAM A16 AC3 AG16 E3 F24 MDDR IO Power POP_TQ E1 POP_NC AC1 VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 MDDR Core Power VDD_MDDR AB4 AB25 F4 H25 N4 T26 OneNAND IO Power POP_CEB_O Y27 VDD_ONAND_IO J26 T27 OneNAND Core Power VDD_ONAND AA26 F26 ...

Page 2097: ...21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 VSS_UOTG_A...

Page 2098: ...S5PC110_UM 1 B TYPE SIZE BALL MAP 1 1 6 PACKAGE DIMENSION Figure 1 2 S5PC110 Package Dimension 596 FCFBGA Top View 1 54 ...

Page 2099: ...S5PC110_UM 1 B TYPE SIZE BALL MAP Figure 1 3 S5PC110 Package Dimension 596 FCFBGA Side View 1 1 ...

Page 2100: ...S5PC110_UM 2 D TYPE SIZE BALL MAP 2 D TYPE SIZE BALL MAP 2 1 PIN ASSIGNMENT 2 1 1 PIN ASSIGNMENT DIAGRAM 596 BALL FCFBGA POP Figure 2 1 S5PC110 Pin Assignment 596 FCFBGA Bottom View 2 2 ...

Page 2101: ...A7 VDD_ODRAMA_IO A27 VSS B20 NC11 C13 POP_A6_A A8 NC21 B1 VSS B21 POP_UDQS_A C14 POP_A8_A A9 NC19 B2 POP_DQ2_A B22 NC13 C15 POP_A9_A A10 POP_BA1_A B3 NC3 B23 VSS C16 POP_INTB_A A11 POP_RASB_A B4 POP_DQ3_A B24 POP_DQ14_A C17 NC20 A12 POP_CLKB_A B5 NC6 B25 XVVD_10 C18 POP_DQ9_A A13 NC17 B6 POP_DQ6_A B26 XVVD_13 C19 POP_DQ11_A A14 NC18 B7 NC8 B27 VSS C20 POP_DQ15_A A15 POP_A7_A B8 VSS C1 NC2 C21 NC14...

Page 2102: ...D_ODRAM F18 XMIPISDN2 G13 XMIPIMDN2 D9 XUOTGVBUS E25 XVVD_7 F19 XMIPISDN3 G14 XMIPIMDN3 D10 XUHOSTREXT E26 XVVD_14 F20 XVVD_20 G15 XMIPISDN0 D11 VDD_UHOST_A E27 XVVD_22 F21 XVVD_9 G16 XMIPISDP1 D12 VSS_UHOST_A F1 XCIPCLK F22 XVVCLK G17 XMIPISDPCLK D13 POP_CKE_A F2 XI2C1SCL F24 VDD_ODRAM G18 XMIPISDP2 D14 XADCAIN_9 F3 XCIFIELD F25 VSS G19 XMIPISDP3 D15 XADCAIN_1 F4 VDD_MDDR F26 VDD_ONAND G20 XVVD_3...

Page 2103: ... XUSBXTI H9 VSS_UOTG_D J3 XCIDATA_7 K11 XUTXD_2 L7 VDD_SYS1 H10 VDD_UOTG_D J4 XI2C2SCL K12 VDD_UHOST_D L8 VDD_ALIVE H11 VSS_UOTG_A J6 XUOTGREXT K13 VDD_MIPI_PLL L10 VDD_KEY H12 VSS_UHOST_D J7 XCIDATA_0 K14 XMIPIVREG_0P4V L11 XURXD_3 H13 VSS_MIPI J8 VDD_SYS0 K15 VDD_MIPI_A L12 XUTXD_3 H14 VDD_MIPI_D J20 VDD_AUD K16 XADCAIN_6 L13 VSS_UHOST_AC H15 VDD_MIPI_D J21 VSS_DAC K17 XADCAIN_5 L14 XVHSYNC H16 ...

Page 2104: ...25 XM0DATA_3 P25 XM0DATA_4 M2 XEINT_14 M26 XHDMITX1N N26 XHDMITX0N P26 XHDMITXCN M3 XEINT_19 M27 XHDMITX1P N27 XHDMITX0P P27 XHDMITXCP M4 XCIDATA_1 N1 VDD_MDDR_IO P1 VSS R1 VDD_ARM M6 XCIHREF N2 XEINT_17 P2 XEINT_12 R2 VDD_ARM M7 VDD_EPLL N3 XEINT_16 P3 XEINT_7 R3 VDD_ARM M8 VDD_SYS0 N4 VDD_MDDR P4 XEINT_27 R4 VDD_ARM M10 XI2C2SDA N6 VDD_APLL P6 VSS_APLL R6 VDD_ARM M11 VDD_INT N7 VSS_EPLL P7 VSS_V...

Page 2105: ... XJTRSTN V15 VDD_INT R27 XM0DATA_10 T24 Xpcm2SOUT U20 VDD_M0 V16 VDD_INT T1 VSS T25 Xpcm2EXTCLK U21 XI2S0LRCK V17 VDD_INT T2 XEINT_30 T26 VDD_MDDR U22 XM0CSN_0 V18 XJTMS T3 XEINT_5 T27 VDD_ONAND_IO U24 XEFFSOURCE_0 V20 XM0ADDR_2 T4 VSS U1 VDD_MDDR_IO U25 VSS V21 XM0FRNB_2 T6 VDD_MPLL U2 XEINT_10 U26 XM0DATA_1 V22 XM0WAITN T7 VSS_MPLL U3 XEINT_23 U27 XM0DATA_9 V24 Xpcm2SCLK T8 EPLL_FILTER U4 VSS V1...

Page 2106: ...LKO W24 XM0CSN_1 Y18 VDD_EXT0 AA13 VSS AB8 XI2C0SDA W25 XM0FALE Y19 XMMC3CMD AA14 XURXD_1 AB9 XURTSN_1 W26 Xpcm2FSYNC Y20 XMMC2CDN AA15 VSS AB10 XURTSN_0 W27 XM0FREN Y21 XM0BEN_1 AA16 XPWMTOUT_3 AB11 XUTXD_0 Y1 XOM_4 Y22 XMMC2CMD AA17 XMMC3DATA_3 AB12 XUCTSN_1 Y2 XOM_2 Y24 XM0CSN_5 AA18 XMMC2CLK AB13 XUTXD_1 Y3 XOM_1 Y25 XM0CSN_4 AA19 XMMC2DATA_0 AB14 XURXD_0 Y4 XOM_0 Y26 XM0FCLE AA20 XMSMADDR_10 ...

Page 2107: ... XNWRESET AD18 XMSMADDR_1 AE13 XMSMWEN AF6 VDD_INT AC3 VDD_ODRAM AD19 XMSMADDR_8 AE14 XMSMDATA_3 AF7 VSS AC25 XM0ADDR_0 AD20 XMSMADDR_6 AE15 XMSMDATA_15 AF8 XMMC0CLK AC26 XM0FRNB_1 AD21 NC AE16 XMSMDATA_13 AF9 XMMC1DATA_2 AC27 XM0FRNB_3 AD22 NC AE17 XMSMADDR_3 AF10 XMMC0DATA_3 AD1 VSS AD25 VDD_ODRAMB_IO AE18 XMSMADDR_12 AF11 XMMC0DATA_1 AD2 XEINT_4 AD26 XM0ADDR_6 AE19 XMSMADDR_7 AF12 XMSMADVN AD3 ...

Page 2108: ...ADDR_4 AG14 XMSMDATA_2 AF22 XM0ADDR_13 AG15 VSS AF23 XM0ADDR_12 AG16 VDD_ODRAM AF24 XM0ADDR_8 AG17 XMSMADDR_13 AF25 XM0ADDR_7 AG18 XMSMDATA_6 AF26 XM0ADDR_15 AG19 XMSMADDR_0 AF27 VSS AG20 VDD_ODRAMB_IO AG1 VSS AG21 VSS AG2 VSS AG22 XMSMADDR_9 AG3 VDD_ODRAMB_IO AG23 XMSMADDR_11 AG4 XSPIMOSI_1 AG24 XJDBGSEL AG5 XSPICLK_0 AG25 VDD_ODRAMB_IO AG6 VDD_INT AG26 VSS AG7 VSS AG27 VSS AG8 VDD_ODRAMB_IO AG9 ...

Page 2109: ...DD_EXT1 H8 L18 EXT1 VDD_EXT2 AB17 EXT2 VDD_CKO N10 RTC CLKO VDD_RTC N8 RTC Internal Logic VDD_INT AD6 AE6 AF6 AG6 M11 M12 M13 M14 M15 M16 T17 U17 V14 V15 V16 V17 Internal logic VDD_ARM R1 R2 R3 R4 R6 R7 R8 R10 R11 R12 T10 T11 T12 U11 Cortex A8 core VDD_ALIVE K8 L8 Alive logic Analog High Speed VDD_ADC H17 P20 ADC VDD_DAC_A K20 DAC Analog VDD_DAC J22 DAC Digital VDD_MIPI_A K15 MIPI 1 8V VDD_MIPI_D ...

Page 2110: ... VDD_EPLL M7 EPLL MCP VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAMA VDDQ VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAMB VDDQ VDD_ODRAM A16 AC3 AG16 E3 F24 OneDRAM CORE VDD VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 MDDR VDDQ VDD_MDDR AB4 AB25 F4 H25 N4 T26 MDDR CORE VDD VDD_ONAND_IO J26 T27 OneNAND VCCQ VDD_ONAND AA26 F26 OneNAND VCC ...

Page 2111: ...2 AG7 AG15 AG21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H...

Page 2112: ...UART_2_RTSn O GPI I L Signal I O Description UART_0_RXD I UART 0 receives data input UART_0_TXD O UART 0 transmits data output UART_0_CTSn I UART 0 clear to send input signal UART_0_RTSn O UART 0 request to send output signal UART_1_RXD I UART 1 receives data input UART_1_TXD O UART 1 transmits data output UART_1_CTSn I UART 1 clear to send input signal UART_1_RTSn O UART 1 request to send output ...

Page 2113: ..._1_MISO IO GPI I L XSPIMOSI_1 SPI_1_MOSI IO GPI I L Signal I O Description SPI_0_CLK IO SPI clock for channel 0 SPI_0_nSS IO SPI chip select only for slave mode for channel 0 SPI_0_MISO IO SPI master input slave output line for channel 0 SPI_0_MOSI IO SPI master output slave input line for channel 0 SPI_1_CLK IO SPI clock for channel 1 SPI_1_nSS IO SPI chip select only for slave mode for channel 1...

Page 2114: ...el 1 I2S_1_LRCK IO IIS bus channel select clock for channel 1 I2S_1_SDI I IIS bus serial data input for channel 1 I2S_1_SDO O IIS bus serial data output for channel 1 PCM_2_SCLK O PCM Serial Shift Clock for channel 2 PCM_2_EXTCLK I PCM External Clock for channel 2 PCM_2_FSYNC O PCM Sync indicating start of word for channel 2 PCM_2_SIN I PCM Serial Data Input for channel 2 PCM_2_SOUT O PCM Serial D...

Page 2115: ... AC97SDO O AC link Serial Data output to AC97 Codec I2S_2_SCLK IO IIS bus serial clock for channel 2 I2S_2_CDCLK IO IIS CODEC system clock for channel 2 I2S_2_LRCK IO IIS bus channel select clock for channel 2 I2S_2_SDI I IIS bus serial data input for channel 2 I2S_2_SDO O IIS bus serial data output for channel 2 ...

Page 2116: ...XI2C1SDA I2C1_SDA IO GPI I L XI2C1SCL I2C1_SCL IO GPI I L XI2C2SDA I2C2_SDA IO IEM_SCLK IO GPI I L XI2C2SCL I2C2_SCL IO IEM_SPWI IO GPI I L Signal I O Description TOUT_0 1 2 3 O PWM Timer Output I2C0_SDA IO IIC bus clock for channel 0 I2C0_SCL IO IIC bus data for channel 0 I2C1_SDA IO IIC bus clock for channel 1 I2C1_SCL IO IIC bus data for channel 1 I2C2_SDA IO IIC bus clock for channel 0 I2C2_SC...

Page 2117: ...A 5 I GPI I L XCIDATA_6 CAM_A_DATA 6 I GPI I L XCIDATA_7 CAM_A_DATA 7 I GPI I L XCICLKENB CAM_A_CLKOUT O GPI I L XCIFIELD CAM_A_FIELD I GPI I L Signal I O Description CAM_A_PCLK O Pixel Clock driven by the Camera processor A CAM_A_VSYNC IO Vertical Sync driven by the Camera processor A CAM_A_HREF IO Horizontal Sync driven by the Camera processor A CAM_A_DATA 7 0 IO Pixel Data for YCbCr in 8 bit mo...

Page 2118: ... SYS_VD 7 IO VEN_DATA 7 O GPI I L XVVD_8 LCD_VD 8 O SYS_VD 8 IO V656_DATA 0 O GPI I L XVVD_9 LCD_VD 9 O SYS_VD 9 IO V656_DATA 1 O GPI I L XVVD_10 LCD_VD 10 O SYS_VD 10 IO V656_DATA 2 O GPI I L XVVD_11 LCD_VD 11 O SYS_VD 11 IO V656_DATA 3 O GPI I L XVVD_12 LCD_VD 12 O SYS_VD 12 IO V656_DATA 4 O GPI I L XVVD_13 LCD_VD 13 O SYS_VD 13 IO V656_DATA 5 O GPI I L XVVD_14 LCD_VD 14 O SYS_VD 14 IO V656_DATA...

Page 2119: ...rect i80 System interface SYS_RS O Register State Select Signal for LCD Indirect i80 System interface SYS_WE O Write Enable for LCD Indirect i80 System interface SYS_VD 23 0 IO Video data input output for LCD Indirect i80 System interface SYS_OE O Output Enable for LCD Indirect i80 System interface VEN_HSYNC O Horizontal Sync Signal for 601 interface VEN_VSYNC O Vertical Sync Signal for 601 interf...

Page 2120: ..._0_DATA 4 IO GPI I L XMMC1DATA_1 SD_1_DATA 1 IO SD_0_DATA 5 IO GPI I L XMMC1DATA_2 SD_1_DATA 2 IO SD_0_DATA 6 IO GPI I L XMMC1DATA_3 SD_1_DATA 3 IO SD_0_DATA 7 IO GPI I L XMMC2CLK SD_2_CLK O GPI I L XMMC2CMD SD_2_CMD IO GPI I L XMMC2CDN SD_2_CDn I GPI I L XMMC2DATA_0 SD_2_DATA 0 IO GPI I L XMMC2DATA_1 SD_2_DATA 1 IO GPI I L XMMC2DATA_2 SD_2_DATA 2 IO GPI I L XMMC2DATA_3 SD_2_DATA 3 IO GPI I L XMMC...

Page 2121: ...nel 1 SD_1_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 1 SD_2_CLK O CLOCK SD SDIO MMC card interface channel 2 SD_2_CMD IO COMMAND RESPONSE SD SDIO MMC card interface channel 2 SD_2_CDn I CARD DETECT SD SDIO MMC card interface channel 2 SD_2_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 2 SD_3_CLK O CLOCK SD SDIO MMC card interface channel 3 SD_3_CMD IO COMMAND RESPONSE SD SD...

Page 2122: ... GPI I L XEINT_13 I HDMI_HPD I GPI I L XEINT_14 I GPI I L XEINT_15 I GPI I L XEINT_16 I KP_COL 0 IO GPI I L XEINT_17 I KP_COL 1 IO GPI I L XEINT_18 I KP_COL 2 IO GPI I L XEINT_19 I KP_COL 3 IO GPI I L XEINT_20 I KP_COL 4 IO GPI I L XEINT_21 I KP_COL 5 IO GPI I L XEINT_22 I KP_COL 6 IO GPI I L XEINT_23 I KP_COL 7 IO GPI I L XEINT_24 I KP_ROW 0 I GPI I L XEINT_25 I KP_ROW 1 I GPI I L XEINT_26 I KP_R...

Page 2123: ...10_UM 2 D TYPE SIZE BALL MAP 2 25 Signal I O Description XEINT 31 0 I External interrupts KP_COL 7 0 O KeyIF_Column_data 7 0 KP_ROW 7 0 I KeyIF_Row_data 7 0 HDMI_CEC IO HDMI CEC port HDMI_HPD I HDMI Hot plug ...

Page 2124: ...al I O Description I2S_0_SCLK IO IIS bus serial clock for channel 0 Lower Power Audio I2S_0_CDCLK IO IIS CODEC system clock for channel 0 Lower Power Audio I2S_0_LRCK IO IIS bus channel select clock for channel 0 Lower Power Audio I2S_0_SDI I IIS bus serial data input for channel 0 Lower Power Audio I2S_0_SDO 2 0 O IIS bus serial data output for channel 0 Lower Power Audio PCM_0_SCLK O PCM Serial ...

Page 2125: ...I L XMSMADDR_10 MSM_ADDR 10 I CAM_B_HREF I SROM_ADDR_16to22 2 O MHL_D3 O GPI I L XMSMADDR_11 MSM_ADDR 11 I CAM_B_FIELD I SROM_ADDR_16to22 3 O MHL_D4 O GPI I L XMSMADDR_12 MSM_ADDR 12 I CAM_B_CLKOUT O SROM_ADDR_16to22 4 O MHL_D5 O GPI I L XMSMADDR_13 MSM_ADDR 13 I KP_COL 0 I O SROM_ADDR_16to22 5 O MHL_D6 O GPI I L XMSMDATA_0 MSM_DATA 0 I O KP_COL 1 I O CF_DATA 0 I O MHL_D7 O GPI I L XMSMDATA_1 MSM_...

Page 2126: ...KP_ROW 13 I SROM_ADDR_16to22 6 O MHL_DE O GPI I L Signal I O Description MSM_ADDR 13 0 I MODEM MSM IF Address MSM_ADDR 13 should be 0 MSM_DATA 15 0 IO MODEM MSM IF Data MSM_CSn I MODEM MSM IF Chip Select MSM_WEn I MODEM MSM IF Write enable MSM_Rn I MODEM MSM IF Read enable MSM_IRQn O MODEM MSM IF Interrupt to MODEM MSM_ADVN I MODEM MSM IF Address Valid from MODEM Chip CAM_B_DATA 7 0 I Pixel Data d...

Page 2127: ... TS_CLK I TSI system clock 66MHz TS_SYNC I TSI synchronization control signal TS_VAL I TSI valid signal TS_DATA I TSI input data TS_ERROR I TSI error indicate signal MHL_D0 O MHL Data 0 MHL_D1 O MHL Data 1 MHL_D2 O MHL Data 2 MHL_D3 O MHL Data 3 MHL_D4 O MHL Data 4 MHL_D5 O MHL Data 5 MHL_D6 O MHL Data 6 MHL_D7 O MHL Data 7 MHL_D8 O MHL Data 8 MHL_D9 O MHL Data 9 MHL_D10 O MHL Data 10 MHL_D11 O MH...

Page 2128: ...110_UM 2 D TYPE SIZE BALL MAP 2 30 Signal I O Description MHL_D22 O MHL Data 22 MHL_D23 O MHL Data 23 MHL_HSYNC O MHL Hsync MHL_IDCK O MHL Interface Data Clock MHL_VSYNC O MHL Vsync MHL_DE O MHL Data Enable ...

Page 2129: ...LE O ONANDXL_ADDRVALID O Func3 O L XM0FALE NF_ALE O ONANDXL_SMCLK O Func3 O L XM0FWEN NF_FWEn O ONANDXL_RPn O Func3 O H XM0FREN NF_FREn O Func3 O H XM0FRNB_0 NF_RnB 0 I ONANDXL_INT 0 I Func3 I XM0FRNB_1 NF_RnB 1 I ONANDXL_INT 1 I Func3 I XM0FRNB_2 NF_RnB 2 I Func3 I XM0FRNB_3 NF_RnB 3 I Func3 I XM0ADDR_0 EBI_ADDR 0 O Func0 O L XM0ADDR_1 EBI_ADDR 1 O Func0 O L XM0ADDR_2 EBI_ADDR 2 O Func0 O L XM0AD...

Page 2130: ...5 EBI_DATA 15 IO Func0 O L Signal I O Description SROM_CSn 5 4 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 3 2 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 1 0 O Memory Port 0 SROM Chip select support up to 2 memory bank EBI_OEn O Memory Port 0 SROM OneNAND Output Enable EBI_WEn O Memory Port 0 SROM OneNAND Write Enable EBI_BEn 1 0 O Memory Port 0...

Page 2131: ...ect bank 1 NFCSn 2 O Memory Port 0 NAND Chip Select bank 2 NFCSn 3 O Memory Port 0 NAND Chip Select bank 3 ONANDXL_ADDRVALID O OneNANDXL Flash Address valid ONANDXL_SMCLK O OneNANDXL Flash clock ONANDXL_RPn O OneNANDXL Flash reset ONANDXL_INT 1 0 I OneNANDXL Flash Interrupt signal from OneNAND Device ...

Page 2132: ...3 IO Memory port 1DRAM Data Differential Strobe neg 4bit XM1DQM_0 XM1DQM_3 IO Memory port 1DRAM Data Mask 4bit XM1CKE_0 XM1CKE_1 IO Memory port 1DRAM Clock Enable 2bit XM1SCLK IO Memory port 1DRAM Clock XM1nSCLK IO Memory port 1DRAM Inverted Clock of Xm1SCLK XM1CSn_0 XM1CSn_1 IO Memory port 1DRAM Chip Select support up to 2 memory bank 2bit XM1RASn IO Memory port 1DRAM Row Address Strobe XM1CASn I...

Page 2133: ...3 IO Memory port 2DRAM Data Differential Strobe neg 4bit XM2DQM_0 XM2DQM_3 IO Memory port 2DRAM Data Mask 4bit XM2CKE_0 XM2CKE_1 IO Memory port 2DRAM Clock Enable 2bit XM2SCLK IO Memory port 2DRAM Clock XM2nSCLK IO Memory port 2DRAM Inverted Clock of Xm1SCLK XM2CSn_0 XM2CSn_1 IO Memory port 2DRAM Chip Select support up to 2 memory bank 2bit XM2RASn IO Memory port 2DRAM Row Address Strobe XM2CASn I...

Page 2134: ...gic Pull down resistor is connected XJTDI I XjTDI TAP Controller Data Input is the serial input for test instructions and data Pull up resistor is connected XJTDO O XjTDO TAP Controller Data Output is the serial output for test instructions and data XJDBGSEL I JTAG selection 0 CORTEXA8 Core JTAG 1 Peripherals JTAG RESET etc Dedicated Ball Name I O Description XOM_0 XOM_5 I Operating Mode control s...

Page 2135: ...nal capacitor connection XHDMITX0P O HDMI Phy TX0 P XHDMITX0N O HDMI Phy TX0 N XHDMITX1P O HDMI Phy TX1 P XHDMITX1N O HDMI Phy TX1 N XHDMITX2P O HDMI Phy TX2 P XHDMITX2N O HDMI Phy TX2 N XHDMITXCP O HDMI Phy TX Clock P XHDMITXCN O HDMI Phy TX Clock N XHDMIREXT I HDMI Phy Registance XHDMIXTI I HDMI crystal input XHDMIXTO O HDMI crystal output XMIPIMDP0 IO Master DATA LANE0 DP for MIPI DPHY XMIPIMDP...

Page 2136: ...K IO Slave CLK Lane DN for MIPI DPHY XMIPIVREG_0P4V IO Regulator capacitor for MIPI DPHY USB OTG USB HOST 1 1 Dedicated Ball Name I O Description XUOTGDRVVUBS O USB OTG charge pump enable XUHOSTPWREN O USB HOST charge pump enable XUHOSTOVERCUR I USB HOST over current flag XUOTGDP IO USB OTG Data pin DATA XUOTGREXT IO USB OTG External 44 2ohm 1 resistor connection XUOTGDM IO USB OTG Data pin DATA X...

Page 2137: ...ck Enable POP_CSB_A IO POP_A DRAM Chip Select POP_RASB_A IO POP_A DRAM Row Address Strobe POP_CASB_A IO POP_A DRAM Column Address Strobe POP_WEB_A IO POP_A DRAM Write Enable POP_BA0_A POP_BA1_A IO POP_A DRAM Bank Address POP_LDM_A IO POP_A DRAM Lower data input mask POP_LDQS_A IO POP_A DRAM Lower data strobe POP_UDM_A IO POP_A DRAM upper data input mask POP_UDQS_A IO POP_A DRAM upper data strobe P...

Page 2138: ...6 K16 XADCAIN_7 L15 XADCAIN_8 D16 XADCAIN_9 D14 VDD_ADC H17 P20 VSS_ADC H18 N20 DAC XDACCOMP K25 XDACIREF K22 XDACOUT K24 XDACVREF L22 VDD_DAC_A K20 VSS_DAC_A K21 VDD_DAC J22 VSS_DAC J21 MIPI DPHY XMIPIMDN0 G10 XMIPIMDN1 F11 XMIPIMDN2 G13 XMIPIMDN3 G14 XMIPIMDNCLK G12 XMIPIMDP0 F10 XMIPIMDP1 G11 XMIPIMDP2 F13 XMIPIMDP3 F14 XMIPIMDPCLK F12 XMIPISDN0 G15 XMIPISDN1 F16 XMIPISDN2 F18 XMIPISDN3 F19 XMI...

Page 2139: ... VSS_MIPI H13 H16 HDMI PHY XHDMIREXT P22 XHDMITX0N N26 XHDMITX0P N27 XHDMITX1N M26 XHDMITX1P M27 XHDMITX2N L26 XHDMITX2P L27 XHDMITXCN P26 XHDMITXCP P27 XHDMIXTI T22 XHDMIXTO R22 VDD_HDMI M22 VDD_HDMI_PLL N21 VDD_HDMI_OSC L20 VSS_HDMI M21 VSS_HDMI_PLL N22 VSS_HDMI_OSC L21 USB OTG XUOTGDM F6 XUOTGDP G6 XUOTGID D8 XUOTGREXT J6 XUOTGVBUS D9 VDD_UOTG_A F9 VDD_UOTG_D H10 VSS_UOTG_A H11 VSS_UOTG_AC G9 V...

Page 2140: ...ll No USB HOST XUHOSTDM G8 XUHOSTDP F8 XUHOSTREXT D10 VDD_UHOST_A D11 VDD_UHOST_D K12 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 APLL VDD_APLL N6 VSS_APLL P6 MPLL VDD_MPLL T6 VSS_MPLL T7 VPLL VDD_VPLL P8 VSS_VPLL P7 EPLL VDD_EPLL M7 VSS_EPLL N7 EPLL_FILTER T8 ...

Page 2141: ...DDR_11 AE26 XM0ADDR_12 AF23 XM0ADDR_13 AF22 XM0ADDR_14 AE23 XM0ADDR_15 AF26 XM0ADDR_2 V20 XM0ADDR_3 W21 XM0ADDR_4 W22 XM0ADDR_5 AD27 XM0ADDR_6 AD26 XM0ADDR_7 AF25 XM0ADDR_8 AF24 XM0ADDR_9 AE22 XM0BEN_0 AA24 XM0BEN_1 Y21 XM0CSN_0 U22 XM0CSN_1 W24 XM0CSN_2 AE24 XM0CSN_3 AA25 XM0CSN_4 Y25 XM0CSN_5 Y24 XM0DATA_0 V25 XM0DATA_1 U26 XM0DATA_10 R27 XM0DATA_11 R25 XM0DATA_12 P24 XM0DATA_13 M25 XM0DATA_14 J...

Page 2142: ...ATA_RDN AB26 XM0FALE W25 XM0FCLE Y26 XM0FREN W27 XM0FRNB_0 H26 XM0FRNB_1 AC26 XM0FRNB_2 V21 XM0FRNB_3 AC27 XM0FWEN AA27 XM0OEN G27 XM0WAITN V22 XM0WEN G26 VDD_M0 T20 U20 LCD XVHSYNC L14 XVSYS_OE G21 XVVCLK F22 XVVD_0 D20 XVVD_1 D21 XVVD_10 B25 XVVD_11 G24 XVVD_12 G22 XVVD_13 B26 XVVD_14 E26 XVVD_15 D27 XVVD_16 C25 XVVD_17 H22 XVVD_18 C26 XVVD_19 G25 XVVD_2 D22 XVVD_20 F20 ...

Page 2143: ...VD_9 F21 XVVDEN D19 XVVSYNC D18 XVVSYNC_LDI H24 VDD_LCD H19 CAMERA XCICLKENB H3 XCIDATA_0 J7 XCIDATA_1 M4 XCIDATA_2 G2 XCIDATA_3 H2 XCIDATA_4 H1 XCIDATA_5 G3 XCIDATA_6 J2 XCIDATA_7 J3 XCIFIELD F3 XCIHREF M6 XCIPCLK F1 XCIVSYNC K7 VDD_CAM H7 AUDIO XI2S0CDCLK M17 XI2S0LRCK U21 XI2S0SCLK N17 XI2S0SDI R24 XI2S0SDO_0 M24 XI2S0SDO_1 R20 XI2S0SDO_2 P18 XI2S1CDCLK T21 XI2S1LRCK R21 ...

Page 2144: ... AG19 XMSMADDR_1 AD18 XMSMADDR_10 AA20 XMSMADDR_11 AG23 XMSMADDR_12 AE18 XMSMADDR_13 AG17 XMSMADDR_2 AE20 XMSMADDR_3 AE17 XMSMADDR_4 AF21 XMSMADDR_5 AE21 XMSMADDR_6 AD20 XMSMADDR_7 AE19 XMSMADDR_8 AD19 XMSMADDR_9 AG22 XMSMADVN AF12 XMSMCSN AD14 XMSMDATA_0 AG11 XMSMDATA_1 AF14 XMSMDATA_10 AD15 XMSMDATA_11 AG13 XMSMDATA_12 AF15 XMSMDATA_13 AE16 XMSMDATA_14 AF16 XMSMDATA_15 AE15 XMSMDATA_2 AG14 XMSMD...

Page 2145: ...MSMRN AD13 XMSMWEN AE13 VDD_MODEM AA21 KEY XEINT_16 N3 XEINT_17 N2 XEINT_18 W4 XEINT_19 M3 XEINT_20 V2 XEINT_21 L3 XEINT_22 K1 XEINT_23 U3 XEINT_24 L2 XEINT_25 V4 XEINT_26 K3 XEINT_27 P4 XEINT_28 K2 XEINT_29 L4 XEINT_30 T2 XEINT_31 K4 VDD_KEY L10 System 0 XXTI AB2 XXTO AB3 XOM_0 Y4 XOM_1 Y3 XOM_2 Y2 XOM_3 AA6 XOM_4 Y1 XOM_5 AA2 XPWRRGTON AA7 XNRESET AB6 XNRSTOUT Y7 ...

Page 2146: ...VBUS F7 XUHOSTPWREN D6 XUHOSTOVERCUR H6 XDDR2SEL G7 XUSBXTI L6 XUSBXTO K6 XJTRSTN U18 XJTMS V18 XJTCK W20 XJTDI T18 XJTDO R18 XJDBGSEL AG24 VDD_SYS0 J8 M8 P21 System 1 XEINT_8 Y6 XEINT_9 V6 XEINT_10 U2 XEINT_11 AE2 XEINT_12 P2 XEINT_13 W3 XEINT_14 M2 XEINT_15 W1 VDD_SYS1 L7 External Peri 0 XMMC0CDN AG10 XMMC0CLK AF8 XMMC0CMD AD11 XMMC0DATA_0 AE11 XMMC0DATA_1 AF11 XMMC0DATA_2 AD12 ...

Page 2147: ...PICSN_0 AF4 XSPIMISO_0 AE3 XSPIMOSI_0 AE5 XURXD_0 AB14 XUTXD_0 AB11 XUCTSN_0 AE12 XURTSN_0 AB10 XURXD_1 AA14 XUTXD_1 AB13 XUCTSN_1 AB12 XURTSN_1 AB9 XI2C0SDA AB8 XI2C0SCL AD7 XPWMTOUT_0 Y16 XPWMTOUT_1 AB16 XPWMTOUT_2 AD9 XPWMTOUT_3 AA16 VDD_EXT0 Y18 External Peri 1 XMMC2CDN Y20 XMMC2CLK AA18 XMMC2CMD Y22 XMMC2DATA_0 AA19 XMMC2DATA_1 AA22 XMMC2DATA_2 AB22 XMMC2DATA_3 AB21 XI2C1SCL F2 XI2C1SDA H4 XI...

Page 2148: ...3 L12 VDD_EXT1 H8 L18 External Peri 2 XMMC3CDN Y15 XMMC3CLK AB20 XMMC3CMD Y19 XMMC3DATA_0 AB18 XMMC3DATA_1 Y17 XMMC3DATA_2 AB15 XMMC3DATA_3 AA17 XSPICLK_1 AF3 XSPICSN_1 AF5 XSPIMISO_1 AE4 XSPIMOSI_1 AG4 VDD_EXT2 AB17 RTC Clock Out XRTCCLKO AB7 VDD_CKO N10 RTC XRTCXTI AA3 XRTCXTO AA4 VDD_RTC N8 EFUSE Security XEFFSOURCE_0 U24 ...

Page 2149: ...R10 R11 R12 T10 T11 T12 U11 Alive VDD_ALIVE K8 L8 MCP Power Power Domain Ball Name Ball No MCP OneDRAM A IO Power POP_INTB_A C16 POP_A0_A C9 POP_A1_A C8 POP_A2_A B9 POP_A3_A C7 POP_A4_A B15 POP_A5_A A17 POP_A6_A C13 POP_A7_A A15 POP_A8_A C14 POP_A9_A C15 POP_A10_A B10 POP_A11_A B13 POP_A12_A C12 POP_BA0_A B11 POP_BA1_A A10 POP_CASB_A C11 POP_RASB_A A11 POP_WEB_A B14 POP_CKE_A D13 POP_CLK_A B12 POP...

Page 2150: ... C22 POP_DQ14_A B24 POP_DQ15_A C20 POP_LDM_A C4 POP_LDQS_A C3 POP_UDM_A A21 POP_UDQS_A B21 VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAM B IO Power POP_INTB_B AF19 VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM Core Power VDD_ODRAM A16 AC3 AG16 E3 F24 MDDR IO Power POP_TQ E1 POP_NC AC1 VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 MDDR Core Power VDD_MDDR AB4 AB25 F4 H25 N4 T26 OneNAND IO Power POP_CEB_O Y27...

Page 2151: ...21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 VSS_UOTG_A...

Page 2152: ...S5PC110_UM 2 D TYPE SIZE BALL MAP 2 1 6 PACKAGE DIMENSION Figure 2 2 S5PC110 Package Dimension 596 FCFBGA Top View 2 54 ...

Page 2153: ...S5PC110_UM 2 D TYPE SIZE BALL MAP Figure 2 3 S5PC110 Package Dimension 596 FCFBGA Side View 2 55 ...

Page 2154: ...S5PC110_UM 3 E TYPE SIZE BALL MAP 3 E TYPE SIZE BALL MAP 3 1 PIN ASSIGNMENT 3 1 1 PIN ASSIGNMENT DIAGRAM 596 BALL FCFBGA POP Figure 3 1 S5PC110 Pin Assignment 596 FCFBGA Bottom View 3 1 ...

Page 2155: ...MA_IO A27 VSS B20 POP_DQ21_A C13 POP_A6_A A8 NC5 B1 VSS B21 NC7 C14 POP_A8_A A9 POP_DQM1_A B2 POP_DQ4_A B22 POP_DQ24_A C15 POP_A9_A A10 POP_BA1_A B3 POP_DQ5_A B23 VSS C16 POP_INTB_A A11 POP_RASB_A B4 POP_DQ6_A B24 POP_DQ29_A C17 POP_DQM2_A A12 NC2 B5 POP_DQ10_A B25 XVVD_10 C18 POP_DQ18_A A13 NC1 B6 POP_DQ13_A B26 XVVD_13 C19 POP_DQ22_A A14 NC3 B7 POP_DQ14_A B27 VSS C20 POP_DQ31_A A15 POP_A7_A B8 V...

Page 2156: ... VDD_ODRAM F18 XMIPISDN2 G13 XMIPIMDN2 D9 XUOTGVBUS E25 XVVD_7 F19 XMIPISDN3 G14 XMIPIMDN3 D10 XUHOSTREXT E26 XVVD_14 F20 XVVD_20 G15 XMIPISDN0 D11 VDD_UHOST_A E27 XVVD_22 F21 XVVD_9 G16 XMIPISDP1 D12 VSS_UHOST_A F1 XCIPCLK F22 XVVCLK G17 XMIPISDPCLK D13 POP_CKE_A F2 XI2C1SCL F24 VDD_ODRAM G18 XMIPISDP2 D14 XADCAIN_9 F3 XCIFIELD F25 VSS G19 XMIPISDP3 D15 XADCAIN_1 F4 VDD_MDDR F26 VDD_ONAND G20 XVV...

Page 2157: ... XUSBXTI H9 VSS_UOTG_D J3 XCIDATA_7 K11 XUTXD_2 L7 VDD_SYS1 H10 VDD_UOTG_D J4 XI2C2SCL K12 VDD_UHOST_D L8 VDD_ALIVE H11 VSS_UOTG_A J6 XUOTGREXT K13 VDD_MIPI_PLL L10 VDD_KEY H12 VSS_UHOST_D J7 XCIDATA_0 K14 XMIPIVREG_0P4V L11 XURXD_3 H13 VSS_MIPI J8 VDD_SYS0 K15 VDD_MIPI_A L12 XUTXD_3 H14 VDD_MIPI_D J20 VDD_AUD K16 XADCAIN_6 L13 VSS_UHOST_AC H15 VDD_MIPI_D J21 VSS_DAC K17 XADCAIN_5 L14 XVHSYNC H16 ...

Page 2158: ...25 XM0DATA_3 P25 XM0DATA_4 M2 XEINT_14 M26 XHDMITX1N N26 XHDMITX0N P26 XHDMITXCN M3 XEINT_19 M27 XHDMITX1P N27 XHDMITX0P P27 XHDMITXCP M4 XCIDATA_1 N1 VDD_MDDR_IO P1 VSS R1 VDD_ARM M6 XCIHREF N2 XEINT_17 P2 XEINT_12 R2 VDD_ARM M7 VDD_EPLL N3 XEINT_16 P3 XEINT_7 R3 VDD_ARM M8 VDD_SYS0 N4 VDD_MDDR P4 XEINT_27 R4 VDD_ARM M10 XI2C2SDA N6 VDD_APLL P6 VSS_APLL R6 VDD_ARM M11 VDD_INT N7 VSS_EPLL P7 VSS_V...

Page 2159: ... XJTRSTN V15 VDD_INT R27 XM0DATA_10 T24 Xpcm2SOUT U20 VDD_M0 V16 VDD_INT T1 VSS T25 Xpcm2EXTCLK U21 XI2S0LRCK V17 VDD_INT T2 XEINT_30 T26 VDD_MDDR U22 XM0CSN_0 V18 XJTMS T3 XEINT_5 T27 VDD_ONAND_IO U24 XEFFSOURCE_0 V20 XM0ADDR_2 T4 VSS U1 VDD_MDDR_IO U25 VSS V21 XM0FRNB_2 T6 VDD_MPLL U2 XEINT_10 U26 XM0DATA_1 V22 XM0WAITN T7 VSS_MPLL U3 XEINT_23 U27 XM0DATA_9 V24 Xpcm2SCLK T8 EPLL_FILTER U4 VSS V1...

Page 2160: ...LKO W24 XM0CSN_1 Y18 VDD_EXT0 AA13 VSS AB8 XI2C0SDA W25 XM0FALE Y19 XMMC3CMD AA14 XURXD_1 AB9 XURTSN_1 W26 Xpcm2FSYNC Y20 XMMC2CDN AA15 VSS AB10 XURTSN_0 W27 XM0FREN Y21 XM0BEN_1 AA16 XPWMTOUT_3 AB11 XUTXD_0 Y1 XOM_4 Y22 XMMC2CMD AA17 XMMC3DATA_3 AB12 XUCTSN_1 Y2 XOM_2 Y24 XM0CSN_5 AA18 XMMC2CLK AB13 XUTXD_1 Y3 XOM_1 Y25 XM0CSN_4 AA19 XMMC2DATA_0 AB14 XURXD_0 Y4 XOM_0 Y26 XM0FCLE AA20 XMSMADDR_10 ...

Page 2161: ... XNWRESET AD18 XMSMADDR_1 AE13 XMSMWEN AF6 VDD_INT AC3 VDD_ODRAM AD19 XMSMADDR_8 AE14 XMSMDATA_3 AF7 VSS AC25 XM0ADDR_0 AD20 XMSMADDR_6 AE15 XMSMDATA_15 AF8 XMMC0CLK AC26 XM0FRNB_1 AD21 NC AE16 XMSMDATA_13 AF9 XMMC1DATA_2 AC27 XM0FRNB_3 AD22 NC AE17 XMSMADDR_3 AF10 XMMC0DATA_3 AD1 VSS AD25 VDD_ODRAMB_IO AE18 XMSMADDR_12 AF11 XMMC0DATA_1 AD2 XEINT_4 AD26 XM0ADDR_6 AE19 XMSMADDR_7 AF12 XMSMADVN AD3 ...

Page 2162: ...ADDR_4 AG14 XMSMDATA_2 AF22 XM0ADDR_13 AG15 VSS AF23 XM0ADDR_12 AG16 VDD_ODRAM AF24 XM0ADDR_8 AG17 XMSMADDR_13 AF25 XM0ADDR_7 AG18 XMSMDATA_6 AF26 XM0ADDR_15 AG19 XMSMADDR_0 AF27 VSS AG20 VDD_ODRAMB_IO AG1 VSS AG21 VSS AG2 VSS AG22 XMSMADDR_9 AG3 VDD_ODRAMB_IO AG23 XMSMADDR_11 AG4 XSPIMOSI_1 AG24 XJDBGSEL AG5 XSPICLK_0 AG25 VDD_ODRAMB_IO AG6 VDD_INT AG26 VSS AG7 VSS AG27 VSS AG8 VDD_ODRAMB_IO AG9 ...

Page 2163: ...DD_EXT1 H8 L18 EXT1 VDD_EXT2 AB17 EXT2 VDD_CKO N10 RTC CLKO VDD_RTC N8 RTC Internal Logic VDD_INT AD6 AE6 AF6 AG6 M11 M12 M13 M14 M15 M16 T17 U17 V14 V15 V16 V17 Internal logic VDD_ARM R1 R2 R3 R4 R6 R7 R8 R10 R11 R12 T10 T11 T12 U11 Cortex A8 core VDD_ALIVE K8 L8 Alive logic Analog High Speed VDD_ADC H17 P20 ADC VDD_DAC_A K20 DAC Analog VDD_DAC J22 DAC Digital VDD_MIPI_A K15 MIPI 1 8V VDD_MIPI_D ...

Page 2164: ... VDD_EPLL M7 EPLL MCP VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAM A VDDQ VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM B VDDQ VDD_ODRAM A16 AC3 AG16 E3 F24 OneDRAM CORE VDD VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 DDR VDDQ VDD_MDDR AB4 AB25 F4 H25 N4 T26 DDR CORE VDD VDD_ONAND_IO J26 T27 OneNAND VCCQ VDD_ONAND AA26 F26 OneNAND VCC ...

Page 2165: ...AG7 AG15 AG21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 M21 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D...

Page 2166: ...UART_2_RTSn O GPI I L Signal I O Description UART_0_RXD I UART 0 receives data input UART_0_TXD O UART 0 transmits data output UART_0_CTSn I UART 0 clear to send input signal UART_0_RTSn O UART 0 request to send output signal UART_1_RXD I UART 1 receives data input UART_1_TXD O UART 1 transmits data output UART_1_CTSn I UART 1 clear to send input signal UART_1_RTSn O UART 1 request to send output ...

Page 2167: ..._1_MISO IO GPI I L XSPIMOSI_1 SPI_1_MOSI IO GPI I L Signal I O Description SPI_0_CLK IO SPI clock for channel 0 SPI_0_nSS IO SPI chip select only for slave mode for channel 0 SPI_0_MISO IO SPI master input slave output line for channel 0 SPI_0_MOSI IO SPI master output slave input line for channel 0 SPI_1_CLK IO SPI clock for channel 1 SPI_1_nSS IO SPI chip select only for slave mode for channel 1...

Page 2168: ...el 1 I2S_1_LRCK IO IIS bus channel select clock for channel 1 I2S_1_SDI I IIS bus serial data input for channel 1 I2S_1_SDO O IIS bus serial data output for channel 1 PCM_2_SCLK O PCM Serial Shift Clock for channel 2 PCM_2_EXTCLK I PCM External Clock for channel 2 PCM_2_FSYNC O PCM Sync indicating start of word for channel 2 PCM_2_SIN I PCM Serial Data Input for channel 2 PCM_2_SOUT O PCM Serial D...

Page 2169: ... AC97SDO O AC link Serial Data output to AC97 Codec I2S_2_SCLK IO IIS bus serial clock for channel 2 I2S_2_CDCLK IO IIS CODEC system clock for channel 2 I2S_2_LRCK IO IIS bus channel select clock for channel 2 I2S_2_SDI I IIS bus serial data input for channel 2 I2S_2_SDO O IIS bus serial data output for channel 2 ...

Page 2170: ...XI2C1SDA I2C1_SDA IO GPI I L XI2C1SCL I2C1_SCL IO GPI I L XI2C2SDA I2C2_SDA IO IEM_SCLK IO GPI I L XI2C2SCL I2C2_SCL IO IEM_SPWI IO GPI I L Signal I O Description TOUT_0 1 2 3 O PWM Timer Output I2C0_SDA IO IIC bus clock for channel 0 I2C0_SCL IO IIC bus data for channel 0 I2C1_SDA IO IIC bus clock for channel 1 I2C1_SCL IO IIC bus data for channel 1 I2C2_SDA IO IIC bus clock for channel 0 I2C2_SC...

Page 2171: ...TA 5 I GPI I L XCIDATA_6 CAM_A_DATA 6 I GPI I L XCIDATA_7 CAM_A_DATA 7 I GPI I L XCICLKENB CAM_A_CLKOUT O GPI I L XCIFIELD CAM_A_FIELD I GPI I L Signal I O Description CAM_A_PCLK O Pixel Clock driven by the Camera processor A CAM_A_VSYNC IO Vertical Sync driven by the Camera processor A CAM_A_HREF IO Horizontal Sync driven by the Camera processor A CAM_A_DATA 7 0 IO Pixel Data for YCbCr in 8 bit m...

Page 2172: ... SYS_VD 7 IO VEN_DATA 7 O GPI I L XVVD_8 LCD_VD 8 O SYS_VD 8 IO V656_DATA 0 O GPI I L XVVD_9 LCD_VD 9 O SYS_VD 9 IO V656_DATA 1 O GPI I L XVVD_10 LCD_VD 10 O SYS_VD 10 IO V656_DATA 2 O GPI I L XVVD_11 LCD_VD 11 O SYS_VD 11 IO V656_DATA 3 O GPI I L XVVD_12 LCD_VD 12 O SYS_VD 12 IO V656_DATA 4 O GPI I L XVVD_13 LCD_VD 13 O SYS_VD 13 IO V656_DATA 5 O GPI I L XVVD_14 LCD_VD 14 O SYS_VD 14 IO V656_DATA...

Page 2173: ...rect i80 System interface SYS_RS O Register State Select Signal for LCD Indirect i80 System interface SYS_WE O Write Enable for LCD Indirect i80 System interface SYS_VD 23 0 IO Video data input output for LCD Indirect i80 System interface SYS_OE O Output Enable for LCD Indirect i80 System interface VEN_HSYNC O Horizontal Sync Signal for 601 interface VEN_VSYNC O Vertical Sync Signal for 601 interf...

Page 2174: ..._0_DATA 4 IO GPI I L XMMC1DATA_1 SD_1_DATA 1 IO SD_0_DATA 5 IO GPI I L XMMC1DATA_2 SD_1_DATA 2 IO SD_0_DATA 6 IO GPI I L XMMC1DATA_3 SD_1_DATA 3 IO SD_0_DATA 7 IO GPI I L XMMC2CLK SD_2_CLK O GPI I L XMMC2CMD SD_2_CMD IO GPI I L XMMC2CDN SD_2_CDn I GPI I L XMMC2DATA_0 SD_2_DATA 0 IO GPI I L XMMC2DATA_1 SD_2_DATA 1 IO GPI I L XMMC2DATA_2 SD_2_DATA 2 IO GPI I L XMMC2DATA_3 SD_2_DATA 3 IO GPI I L XMMC...

Page 2175: ...nel 1 SD_1_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 1 SD_2_CLK O CLOCK SD SDIO MMC card interface channel 2 SD_2_CMD IO COMMAND RESPONSE SD SDIO MMC card interface channel 2 SD_2_CDn I CARD DETECT SD SDIO MMC card interface channel 2 SD_2_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 2 SD_3_CLK O CLOCK SD SDIO MMC card interface channel 3 SD_3_CMD IO COMMAND RESPONSE SD SD...

Page 2176: ... GPI I L XEINT_13 I HDMI_HPD I GPI I L XEINT_14 I GPI I L XEINT_15 I GPI I L XEINT_16 I KP_COL 0 IO GPI I L XEINT_17 I KP_COL 1 IO GPI I L XEINT_18 I KP_COL 2 IO GPI I L XEINT_19 I KP_COL 3 IO GPI I L XEINT_20 I KP_COL 4 IO GPI I L XEINT_21 I KP_COL 5 IO GPI I L XEINT_22 I KP_COL 6 IO GPI I L XEINT_23 I KP_COL 7 IO GPI I L XEINT_24 I KP_ROW 0 I GPI I L XEINT_25 I KP_ROW 1 I GPI I L XEINT_26 I KP_R...

Page 2177: ...10_UM 3 E TYPE SIZE BALL MAP 3 24 Signal I O Description XEINT 31 0 I External interrupts KP_COL 7 0 O KeyIF_Column_data 7 0 KP_ROW 7 0 I KeyIF_Row_data 7 0 HDMI_CEC IO HDMI CEC port HDMI_HPD I HDMI Hot plug ...

Page 2178: ...al I O Description I2S_0_SCLK IO IIS bus serial clock for channel 0 Lower Power Audio I2S_0_CDCLK IO IIS CODEC system clock for channel 0 Lower Power Audio I2S_0_LRCK IO IIS bus channel select clock for channel 0 Lower Power Audio I2S_0_SDI I IIS bus serial data input for channel 0 Lower Power Audio I2S_0_SDO 2 0 O IIS bus serial data output for channel 0 Lower Power Audio PCM_0_SCLK O PCM Serial ...

Page 2179: ...I L XMSMADDR_10 MSM_ADDR 10 I CAM_B_HREF I SROM_ADDR_16to22 2 O MHL_D3 O GPI I L XMSMADDR_11 MSM_ADDR 11 I CAM_B_FIELD I SROM_ADDR_16to22 3 O MHL_D4 O GPI I L XMSMADDR_12 MSM_ADDR 12 I CAM_B_CLKOUT O SROM_ADDR_16to22 4 O MHL_D5 O GPI I L XMSMADDR_13 MSM_ADDR 13 I KP_COL 0 I O SROM_ADDR_16to22 5 O MHL_D6 O GPI I L XMSMDATA_0 MSM_DATA 0 I O KP_COL 1 I O CF_DATA 0 I O MHL_D7 O GPI I L XMSMDATA_1 MSM_...

Page 2180: ...KP_ROW 13 I SROM_ADDR_16to22 6 O MHL_DE O GPI I L Signal I O Description MSM_ADDR 13 0 I MODEM MSM IF Address MSM_ADDR 13 should be 0 MSM_DATA 15 0 IO MODEM MSM IF Data MSM_CSn I MODEM MSM IF Chip Select MSM_WEn I MODEM MSM IF Write enable MSM_Rn I MODEM MSM IF Read enable MSM_IRQn O MODEM MSM IF Interrupt to MODEM MSM_ADVN I MODEM MSM IF Address Valid from MODEM Chip CAM_B_DATA 7 0 I Pixel Data d...

Page 2181: ... TS_CLK I TSI system clock 66MHz TS_SYNC I TSI synchronization control signal TS_VAL I TSI valid signal TS_DATA I TSI input data TS_ERROR I TSI error indicate signal MHL_D0 O MHL Data 0 MHL_D1 O MHL Data 1 MHL_D2 O MHL Data 2 MHL_D3 O MHL Data 3 MHL_D4 O MHL Data 4 MHL_D5 O MHL Data 5 MHL_D6 O MHL Data 6 MHL_D7 O MHL Data 7 MHL_D8 O MHL Data 8 MHL_D9 O MHL Data 9 MHL_D10 O MHL Data 10 MHL_D11 O MH...

Page 2182: ...110_UM 3 E TYPE SIZE BALL MAP 3 29 Signal I O Description MHL_D22 O MHL Data 22 MHL_D23 O MHL Data 23 MHL_HSYNC O MHL Hsync MHL_IDCK O MHL Interface Data Clock MHL_VSYNC O MHL Vsync MHL_DE O MHL Data Enable ...

Page 2183: ...LE O ONANDXL_ADDRVALID O Func3 O L XM0FALE NF_ALE O ONANDXL_SMCLK O Func3 O L XM0FWEN NF_FWEn O ONANDXL_RPn O Func3 O H XM0FREN NF_FREn O Func3 O H XM0FRNB_0 NF_RnB 0 I ONANDXL_INT 0 I Func3 I XM0FRNB_1 NF_RnB 1 I ONANDXL_INT 1 I Func3 I XM0FRNB_2 NF_RnB 2 I Func3 I XM0FRNB_3 NF_RnB 3 I Func3 I XM0ADDR_0 EBI_ADDR 0 O Func0 O L XM0ADDR_1 EBI_ADDR 1 O Func0 O L XM0ADDR_2 EBI_ADDR 2 O Func0 O L XM0AD...

Page 2184: ...5 EBI_DATA 15 IO Func0 O L Signal I O Description SROM_CSn 5 4 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 3 2 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 1 0 O Memory Port 0 SROM Chip select support up to 2 memory bank EBI_OEn O Memory Port 0 SROM OneNAND Output Enable EBI_WEn O Memory Port 0 SROM OneNAND Write Enable EBI_BEn 1 0 O Memory Port 0...

Page 2185: ...ect bank 1 NFCSn 2 O Memory Port 0 NAND Chip Select bank 2 NFCSn 3 O Memory Port 0 NAND Chip Select bank 3 ONANDXL_ADDRVALID O OneNANDXL Flash Address valid ONANDXL_SMCLK O OneNANDXL Flash clock ONANDXL_RPn O OneNANDXL Flash reset ONANDXL_INT 1 0 I OneNANDXL Flash Interrupt signal from OneNAND Device ...

Page 2186: ...ory port 1DRAM Data Differential Strobe neg only LPDDR2 4bit XM1CKE_0 XM1CKE_1 IO Memory port 1DRAM Clock Enable 2bit XM1SCLK IO Memory port 1DRAM Clock XM1nSCLK IO Memory port 1DRAM Inverted Clock of Xm1SCLK XM1CSn_0 XM1CSn_1 IO Memory port 1DRAM Chip Select support up to 2 memory bank 2bit XM1RASn IO Memory port 1DRAM Row Address Strobe XM1CASn IO Memory port 1DRAM Column Address Strobe XM1WEn I...

Page 2187: ...ory port 2DRAM Data Differential Strobe neg only LPDDR2 4bit XM2CKE_0 XM2CKE_1 IO Memory port 2DRAM Clock Enable 2bit XM2SCLK IO Memory port 2DRAM Clock XM2nSCLK IO Memory port 2DRAM Inverted Clock of Xm1SCLK XM2CSn_0 XM2CSn_1 IO Memory port 2DRAM Chip Select support up to 2 memory bank 2bit XM2RASn IO Memory port 2DRAM Row Address Strobe XM2CASn IO Memory port 2DRAM Column Address Strobe XM2WEn I...

Page 2188: ... logic Pull down resistor is connected XJTDI I XjTDI TAP Controller Data Input is the serial input for test instructions and data Pull up resistor is connected XJTDO O XjTDO TAP Controller Data Output is the serial output for test instructions and data XJDBGSEL I JTAG selection 0 CORTEXA8 Core JTAG 1 Peripherals JTAG RESET etc Dedicated Ball Name I O Description XOM_0 XOM_5 I Operating Mode contro...

Page 2189: ...nal capacitor connection XHDMITX0P O HDMI Phy TX0 P XHDMITX0N O HDMI Phy TX0 N XHDMITX1P O HDMI Phy TX1 P XHDMITX1N O HDMI Phy TX1 N XHDMITX2P O HDMI Phy TX2 P XHDMITX2N O HDMI Phy TX2 N XHDMITXCP O HDMI Phy TX Clock P XHDMITXCN O HDMI Phy TX Clock N XHDMIREXT I HDMI Phy Registance XHDMIXTI I HDMI crystal input XHDMIXTO O HDMI crystal output XMIPIMDP0 IO Master DATA LANE0 DP for MIPI DPHY XMIPIMDP...

Page 2190: ...PI DPHY XMIPISDPCLK IO Slave CLK Lane DP for MIPI DPHY XMIPISDNCLK IO Slave CLK Lane DN for MIPI DPHY XMIPIVREG_0P4V IO Regulator capacitor for MIPI DPHY USB OTG USB HOST 1 1 Dedicated Ball Name I O Description XUOTGDRVVUBS O USB OTG charge pump enable XUHOSTPWREN O USB HOST charge pump enable XUHOSTOVERCUR I USB HOST over current flag XUOTGDP IO USB OTG Data pin DATA XUOTGREXT IO USB OTG External...

Page 2191: ... IO POP_A DRAM Address bus POP_CLK_A IO POP_A DRAM CLK POP_CKE_A IO POP_A DRAM Clock Enable POP_CSB_A IO POP_A DRAM Chip Select POP_RASB_A IO POP_A DRAM Row Address Strobe POP_CASB_A IO POP_A DRAM Column Address Strobe POP_WEB_A IO POP_A DRAM Write Enable POP_BA0_A POP_BA1_A IO POP_A DRAM Bank Address POP_DQM0_A POP_DQM3_A IO POP_A DRAM Data Differential Strobe neg POP_INTB_A IO OneDRAM Port A int...

Page 2192: ...6 K16 XADCAIN_7 L15 XADCAIN_8 D16 XADCAIN_9 D14 VDD_ADC H17 P20 VSS_ADC H18 N20 DAC XDACCOMP K25 XDACIREF K22 XDACOUT K24 XDACVREF L22 VDD_DAC_A K20 VSS_DAC_A K21 VDD_DAC J22 VSS_DAC J21 MIPI DPHY XMIPIMDN0 G10 XMIPIMDN1 F11 XMIPIMDN2 G13 XMIPIMDN3 G14 XMIPIMDNCLK G12 XMIPIMDP0 F10 XMIPIMDP1 G11 XMIPIMDP2 F13 XMIPIMDP3 F14 XMIPIMDPCLK F12 XMIPISDN0 G15 XMIPISDN1 F16 XMIPISDN2 F18 XMIPISDN3 F19 XMI...

Page 2193: ... VSS_MIPI H13 H16 HDMI PHY XHDMIREXT P22 XHDMITX0N N26 XHDMITX0P N27 XHDMITX1N M26 XHDMITX1P M27 XHDMITX2N L26 XHDMITX2P L27 XHDMITXCN P26 XHDMITXCP P27 XHDMIXTI T22 XHDMIXTO R22 VDD_HDMI M22 VDD_HDMI_PLL N21 VDD_HDMI_OSC L20 VSS_HDMI M21 VSS_HDMI_PLL N22 VSS_HDMI_OSC L21 USB OTG XUOTGDM F6 XUOTGDP G6 XUOTGID D8 XUOTGREXT J6 XUOTGVBUS D9 VDD_UOTG_A F9 VDD_UOTG_D H10 VSS_UOTG_A H11 VSS_UOTG_AC G9 V...

Page 2194: ...ll No USB HOST XUHOSTDM G8 XUHOSTDP F8 XUHOSTREXT D10 VDD_UHOST_A D11 VDD_UHOST_D K12 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 APLL VDD_APLL N6 VSS_APLL P6 MPLL VDD_MPLL T6 VSS_MPLL T7 VPLL VDD_VPLL P8 VSS_VPLL P7 EPLL VDD_EPLL M7 VSS_EPLL N7 EPLL_FILTER T8 ...

Page 2195: ...DDR_11 AE26 XM0ADDR_12 AF23 XM0ADDR_13 AF22 XM0ADDR_14 AE23 XM0ADDR_15 AF26 XM0ADDR_2 V20 XM0ADDR_3 W21 XM0ADDR_4 W22 XM0ADDR_5 AD27 XM0ADDR_6 AD26 XM0ADDR_7 AF25 XM0ADDR_8 AF24 XM0ADDR_9 AE22 XM0BEN_0 AA24 XM0BEN_1 Y21 XM0CSN_0 U22 XM0CSN_1 W24 XM0CSN_2 AE24 XM0CSN_3 AA25 XM0CSN_4 Y25 XM0CSN_5 Y24 XM0DATA_0 V25 XM0DATA_1 U26 XM0DATA_10 R27 XM0DATA_11 R25 XM0DATA_12 P24 XM0DATA_13 M25 XM0DATA_14 J...

Page 2196: ...ATA_RDN AB26 XM0FALE W25 XM0FCLE Y26 XM0FREN W27 XM0FRNB_0 H26 XM0FRNB_1 AC26 XM0FRNB_2 V21 XM0FRNB_3 AC27 XM0FWEN AA27 XM0OEN G27 XM0WAITN V22 XM0WEN G26 VDD_M0 T20 U20 LCD XVHSYNC L14 XVSYS_OE G21 XVVCLK F22 XVVD_0 D20 XVVD_1 D21 XVVD_10 B25 XVVD_11 G24 XVVD_12 G22 XVVD_13 B26 XVVD_14 E26 XVVD_15 D27 XVVD_16 C25 XVVD_17 H22 XVVD_18 C26 XVVD_19 G25 XVVD_2 D22 XVVD_20 F20 ...

Page 2197: ...VD_9 F21 XVVDEN D19 XVVSYNC D18 XVVSYNC_LDI H24 VDD_LCD H19 CAMERA XCICLKENB H3 XCIDATA_0 J7 XCIDATA_1 M4 XCIDATA_2 G2 XCIDATA_3 H2 XCIDATA_4 H1 XCIDATA_5 G3 XCIDATA_6 J2 XCIDATA_7 J3 XCIFIELD F3 XCIHREF M6 XCIPCLK F1 XCIVSYNC K7 VDD_CAM H7 AUDIO XI2S0CDCLK M17 XI2S0LRCK U21 XI2S0SCLK N17 XI2S0SDI R24 XI2S0SDO_0 M24 XI2S0SDO_1 R20 XI2S0SDO_2 P18 XI2S1CDCLK T21 XI2S1LRCK R21 ...

Page 2198: ... AG19 XMSMADDR_1 AD18 XMSMADDR_10 AA20 XMSMADDR_11 AG23 XMSMADDR_12 AE18 XMSMADDR_13 AG17 XMSMADDR_2 AE20 XMSMADDR_3 AE17 XMSMADDR_4 AF21 XMSMADDR_5 AE21 XMSMADDR_6 AD20 XMSMADDR_7 AE19 XMSMADDR_8 AD19 XMSMADDR_9 AG22 XMSMADVN AF12 XMSMCSN AD14 XMSMDATA_0 AG11 XMSMDATA_1 AF14 XMSMDATA_10 AD15 XMSMDATA_11 AG13 XMSMDATA_12 AF15 XMSMDATA_13 AE16 XMSMDATA_14 AF16 XMSMDATA_15 AE15 XMSMDATA_2 AG14 XMSMD...

Page 2199: ...MSMRN AD13 XMSMWEN AE13 VDD_MODEM AA21 KEY XEINT_16 N3 XEINT_17 N2 XEINT_18 W4 XEINT_19 M3 XEINT_20 V2 XEINT_21 L3 XEINT_22 K1 XEINT_23 U3 XEINT_24 L2 XEINT_25 V4 XEINT_26 K3 XEINT_27 P4 XEINT_28 K2 XEINT_29 L4 XEINT_30 T2 XEINT_31 K4 VDD_KEY L10 System 0 XXTI AB2 XXTO AB3 XOM_0 Y4 XOM_1 Y3 XOM_2 Y2 XOM_3 AA6 XOM_4 Y1 XOM_5 AA2 XPWRRGTON AA7 XNRESET AB6 XNRSTOUT Y7 ...

Page 2200: ...VBUS F7 XUHOSTPWREN D6 XUHOSTOVERCUR H6 XDDR2SEL G7 XUSBXTI L6 XUSBXTO K6 XJTRSTN U18 XJTMS V18 XJTCK W20 XJTDI T18 XJTDO R18 XJDBGSEL AG24 VDD_SYS0 J8 M8 P21 System 1 XEINT_8 Y6 XEINT_9 V6 XEINT_10 U2 XEINT_11 AE2 XEINT_12 P2 XEINT_13 W3 XEINT_14 M2 XEINT_15 W1 VDD_SYS1 L7 External Peri 0 XMMC0CDN AG10 XMMC0CLK AF8 XMMC0CMD AD11 XMMC0DATA_0 AE11 XMMC0DATA_1 AF11 XMMC0DATA_2 AD12 ...

Page 2201: ...PICSN_0 AF4 XSPIMISO_0 AE3 XSPIMOSI_0 AE5 XURXD_0 AB14 XUTXD_0 AB11 XUCTSN_0 AE12 XURTSN_0 AB10 XURXD_1 AA14 XUTXD_1 AB13 XUCTSN_1 AB12 XURTSN_1 AB9 XI2C0SDA AB8 XI2C0SCL AD7 XPWMTOUT_0 Y16 XPWMTOUT_1 AB16 XPWMTOUT_2 AD9 XPWMTOUT_3 AA16 VDD_EXT0 Y18 External Peri 1 XMMC2CDN Y20 XMMC2CLK AA18 XMMC2CMD Y22 XMMC2DATA_0 AA19 XMMC2DATA_1 AA22 XMMC2DATA_2 AB22 XMMC2DATA_3 AB21 XI2C1SCL F2 XI2C1SDA H4 XI...

Page 2202: ...3 L12 VDD_EXT1 H8 L18 External Peri 2 XMMC3CDN Y15 XMMC3CLK AB20 XMMC3CMD Y19 XMMC3DATA_0 AB18 XMMC3DATA_1 Y17 XMMC3DATA_2 AB15 XMMC3DATA_3 AA17 XSPICLK_1 AF3 XSPICSN_1 AF5 XSPIMISO_1 AE4 XSPIMOSI_1 AG4 VDD_EXT2 AB17 RTC Clock Out XRTCCLKO AB7 VDD_CKO N10 RTC XRTCXTI AA3 XRTCXTO AA4 VDD_RTC N8 EFUSE Security XEFFSOURCE_0 U24 ...

Page 2203: ... R10 R11 R12 T10 T11 T12 U11 Alive VDD_ALIVE K8 L8 MCP Power Power Domain Ball Name Ball No MCP OneDRAM A IO Power POP_INTB_A C16 POP_A0_A C9 POP_A1_A C8 POP_A2_A B9 POP_A3_A C7 POP_A4_A B15 POP_A5_A A17 POP_A6_A C13 POP_A7_A A15 POP_A8_A C14 POP_A9_A C15 POP_A10_A B10 POP_A11_A B13 POP_A12_A C12 POP_BA0_A B11 POP_BA1_A A10 POP_CASB_A C11 POP_RASB_A A11 POP_WEB_A B14 POP_CKE_A D13 POP_CLK_A B12 PO...

Page 2204: ...A A5 POP_DQ12_A A6 POP_DQ13_A B6 POP_DQ14_A B7 POP_DQ15_A C6 POP_DQ16_A B18 POP_DQ17_A A18 POP_DQ18_A C18 POP_DQ19_A B19 POP_DQ20_A A19 POP_DQ21_A B20 POP_DQ22_A C19 POP_DQ23_A A20 POP_DQ24_A B22 POP_DQ25_A A23 POP_DQ26_A C21 POP_DQ27_A C22 POP_DQ28_A A24 POP_DQ29_A B24 POP_DQ30_A C23 POP_DQ31_A C20 POP_DQM0_A C4 POP_DQM1_A A9 POP_DQM2_A C17 POP_DQM3_A A21 VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAM B POP...

Page 2205: ...O AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM Core Power VDD_ODRAM A16 AC3 AG16 E3 F24 MDDR IO Power POP_TQ E1 POP_NC AC1 VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 MDDR Core Power VDD_MDDR AB4 AB25 F4 H25 N4 T26 OneNAND IO Power POP_CEB_O Y27 VDD_ONAND_IO J26 T27 OneNAND Core Power VDD_ONAND AA26 F26 ...

Page 2206: ... AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 M21 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 VSS_UOTG...

Page 2207: ...S5PC110_UM 3 E TYPE SIZE BALL MAP 3 1 6 PACKAGE DIMENSION Figure 3 2 S5PC110 Package Dimension 596 FCFBGA Top View 3 54 ...

Page 2208: ...S5PC110_UM 3 E TYPE SIZE BALL MAP Figure 3 3 S5PC110 Package Dimension 596 FCFBGA Side View 3 55 ...

Page 2209: ...S5PC110_UM 4 F TYPE SIZE BALL MAP 4 F TYPE SIZE BALL MAP 4 1 PIN ASSIGNMENT 4 1 1 PIN ASSIGNMENT DIAGRAM 596 BALL FCFBGA POP Figure 4 1 S5PC110 Pin Assignment 596 FCFBGA Bottom View 4 1 ...

Page 2210: ...A7 VDD_ODRAMA_IO A27 VSS B20 NC11 C13 POP_A6_A A8 NC21 B1 VSS B21 POP_UDQS_A C14 POP_A8_A A9 NC19 B2 POP_DQ2_A B22 NC13 C15 POP_A9_A A10 POP_BA1_A B3 NC3 B23 VSS C16 POP_INTB_A A11 POP_RASB_A B4 POP_DQ3_A B24 POP_DQ14_A C17 NC20 A12 POP_CLKB_A B5 NC6 B25 XVVD_10 C18 POP_DQ9_A A13 NC17 B6 POP_DQ6_A B26 XVVD_13 C19 POP_DQ11_A A14 NC18 B7 NC8 B27 VSS C20 POP_DQ15_A A15 POP_A7_A B8 VSS C1 NC2 C21 NC14...

Page 2211: ...D_ODRAM F18 XMIPISDN2 G13 XMIPIMDN2 D9 XUOTGVBUS E25 XVVD_7 F19 XMIPISDN3 G14 XMIPIMDN3 D10 XUHOSTREXT E26 XVVD_14 F20 XVVD_20 G15 XMIPISDN0 D11 VDD_UHOST_A E27 XVVD_22 F21 XVVD_9 G16 XMIPISDP1 D12 VSS_UHOST_A F1 XCIPCLK F22 XVVCLK G17 XMIPISDPCLK D13 POP_CKE_A F2 XI2C1SCL F24 VDD_ODRAM G18 XMIPISDP2 D14 XADCAIN_9 F3 XCIFIELD F25 VSS G19 XMIPISDP3 D15 XADCAIN_1 F4 VDD_MDDR F26 VDD_ONAND G20 XVVD_3...

Page 2212: ... XUSBXTI H9 VSS_UOTG_D J3 XCIDATA_7 K11 XUTXD_2 L7 VDD_SYS1 H10 VDD_UOTG_D J4 XI2C2SCL K12 VDD_UHOST_D L8 VDD_ALIVE H11 VSS_UOTG_A J6 XUOTGREXT K13 VDD_MIPI_PLL L10 VDD_KEY H12 VSS_UHOST_D J7 XCIDATA_0 K14 XMIPIVREG_0P4V L11 XURXD_3 H13 VSS_MIPI J8 VDD_SYS0 K15 VDD_MIPI_A L12 XUTXD_3 H14 VDD_MIPI_D J20 VDD_AUD K16 XADCAIN_6 L13 VSS_UHOST_AC H15 VDD_MIPI_D J21 VSS_DAC K17 XADCAIN_5 L14 XVHSYNC H16 ...

Page 2213: ...25 XM0DATA_3 P25 XM0DATA_4 M2 XEINT_14 M26 XHDMITX1N N26 XHDMITX0N P26 XHDMITXCN M3 XEINT_19 M27 XHDMITX1P N27 XHDMITX0P P27 XHDMITXCP M4 XCIDATA_1 N1 VDD_MDDR_IO P1 VSS R1 VDD_ARM M6 XCIHREF N2 XEINT_17 P2 XEINT_12 R2 VDD_ARM M7 VDD_EPLL N3 XEINT_16 P3 XEINT_7 R3 VDD_ARM M8 VDD_SYS0 N4 VDD_MDDR P4 XEINT_27 R4 VDD_ARM M10 XI2C2SDA N6 VDD_APLL P6 VSS_APLL R6 VDD_ARM M11 VDD_INT N7 VSS_EPLL P7 VSS_V...

Page 2214: ... XJTRSTN V15 VDD_INT R27 XM0DATA_10 T24 Xpcm2SOUT U20 VDD_M0 V16 VDD_INT T1 VSS T25 Xpcm2EXTCLK U21 XI2S0LRCK V17 VDD_INT T2 XEINT_30 T26 VDD_MDDR U22 XM0CSN_0 V18 XJTMS T3 XEINT_5 T27 VDD_ONAND_IO U24 XEFFSOURCE_0 V20 XM0ADDR_2 T4 VSS U1 VDD_MDDR_IO U25 VSS V21 XM0FRNB_2 T6 VDD_MPLL U2 XEINT_10 U26 XM0DATA_1 V22 XM0WAITN T7 VSS_MPLL U3 XEINT_23 U27 XM0DATA_9 V24 Xpcm2SCLK T8 EPLL_FILTER U4 VSS V1...

Page 2215: ...LKO W24 XM0CSN_1 Y18 VDD_EXT0 AA13 VSS AB8 XI2C0SDA W25 XM0FALE Y19 XMMC3CMD AA14 XURXD_1 AB9 XURTSN_1 W26 Xpcm2FSYNC Y20 XMMC2CDN AA15 VSS AB10 XURTSN_0 W27 XM0FREN Y21 XM0BEN_1 AA16 XPWMTOUT_3 AB11 XUTXD_0 Y1 XOM_4 Y22 XMMC2CMD AA17 XMMC3DATA_3 AB12 XUCTSN_1 Y2 XOM_2 Y24 XM0CSN_5 AA18 XMMC2CLK AB13 XUTXD_1 Y3 XOM_1 Y25 XM0CSN_4 AA19 XMMC2DATA_0 AB14 XURXD_0 Y4 XOM_0 Y26 XM0FCLE AA20 XMSMADDR_10 ...

Page 2216: ...NWRESET AD18 XMSMADDR_1 AE13 XMSMWEN AF6 VDD_INT AC3 VDD_ODRAM AD19 XMSMADDR_8 AE14 XMSMDATA_3 AF7 VSS AC25 XM0ADDR_0 AD20 XMSMADDR_6 AE15 XMSMDATA_15 AF8 XMMC0CLK AC26 XM0FRNB_1 AD21 NC AE16 XMSMDATA_13 AF9 XMMC1DATA_2 AC27 XM0FRNB_3 AD22 NC AE17 XMSMADDR_3 AF10 XMMC0DATA_3 AD1 VSS AD25 VDD_ODRAMB_IO AE18 XMSMADDR_12 AF11 XMMC0DATA_1 AD2 XEINT_4 AD26 XM0ADDR_6 AE19 XMSMADDR_7 AF12 XMSMADVN AD3 XE...

Page 2217: ...ADDR_4 AG14 XMSMDATA_2 AF22 XM0ADDR_13 AG15 VSS AF23 XM0ADDR_12 AG16 VDD_ODRAM AF24 XM0ADDR_8 AG17 XMSMADDR_13 AF25 XM0ADDR_7 AG18 XMSMDATA_6 AF26 XM0ADDR_15 AG19 XMSMADDR_0 AF27 VSS AG20 VDD_ODRAMB_IO AG1 VSS AG21 VSS AG2 VSS AG22 XMSMADDR_9 AG3 VDD_ODRAMB_IO AG23 XMSMADDR_11 AG4 XSPIMOSI_1 AG24 XJDBGSEL AG5 XSPICLK_0 AG25 VDD_ODRAMB_IO AG6 VDD_INT AG26 VSS AG7 VSS AG27 VSS AG8 VDD_ODRAMB_IO AG9 ...

Page 2218: ...DD_EXT1 H8 L18 EXT1 VDD_EXT2 AB17 EXT2 VDD_CKO N10 RTC CLKO VDD_RTC N8 RTC Internal Logic VDD_INT AD6 AE6 AF6 AG6 M11 M12 M13 M14 M15 M16 T17 U17 V14 V15 V16 V17 Internal logic VDD_ARM R1 R2 R3 R4 R6 R7 R8 R10 R11 R12 T10 T11 T12 U11 Cortex A8 core VDD_ALIVE K8 L8 Alive logic Analog High Speed VDD_ADC H17 P20 ADC VDD_DAC_A K20 DAC Analog VDD_DAC J22 DAC Digital VDD_MIPI_A K15 MIPI 1 8V VDD_MIPI_D ...

Page 2219: ... VDD_EPLL M7 EPLL MCP VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAMA VDDQ VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAMB VDDQ VDD_ODRAM A16 AC3 AG16 E3 F24 OneDRAM CORE VDD VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 MDDR VDDQ VDD_MDDR AB4 AB25 F4 H25 N4 T26 MDDR CORE VDD VDD_ONAND_IO J26 T27 OneNAND VCCQ VDD_ONAND AA26 F26 OneNAND VCC ...

Page 2220: ...2 AG7 AG15 AG21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H...

Page 2221: ...UART_2_RTSn O GPI I L Signal I O Description UART_0_RXD I UART 0 receives data input UART_0_TXD O UART 0 transmits data output UART_0_CTSn I UART 0 clear to send input signal UART_0_RTSn O UART 0 request to send output signal UART_1_RXD I UART 1 receives data input UART_1_TXD O UART 1 transmits data output UART_1_CTSn I UART 1 clear to send input signal UART_1_RTSn O UART 1 request to send output ...

Page 2222: ..._1_MISO IO GPI I L XSPIMOSI_1 SPI_1_MOSI IO GPI I L Signal I O Description SPI_0_CLK IO SPI clock for channel 0 SPI_0_nSS IO SPI chip select only for slave mode for channel 0 SPI_0_MISO IO SPI master input slave output line for channel 0 SPI_0_MOSI IO SPI master output slave input line for channel 0 SPI_1_CLK IO SPI clock for channel 1 SPI_1_nSS IO SPI chip select only for slave mode for channel 1...

Page 2223: ...el 1 I2S_1_LRCK IO IIS bus channel select clock for channel 1 I2S_1_SDI I IIS bus serial data input for channel 1 I2S_1_SDO O IIS bus serial data output for channel 1 PCM_2_SCLK O PCM Serial Shift Clock for channel 2 PCM_2_EXTCLK I PCM External Clock for channel 2 PCM_2_FSYNC O PCM Sync indicating start of word for channel 2 PCM_2_SIN I PCM Serial Data Input for channel 2 PCM_2_SOUT O PCM Serial D...

Page 2224: ... AC97SDO O AC link Serial Data output to AC97 Codec I2S_2_SCLK IO IIS bus serial clock for channel 2 I2S_2_CDCLK IO IIS CODEC system clock for channel 2 I2S_2_LRCK IO IIS bus channel select clock for channel 2 I2S_2_SDI I IIS bus serial data input for channel 2 I2S_2_SDO O IIS bus serial data output for channel 2 ...

Page 2225: ...XI2C1SDA I2C1_SDA IO GPI I L XI2C1SCL I2C1_SCL IO GPI I L XI2C2SDA I2C2_SDA IO IEM_SCLK IO GPI I L XI2C2SCL I2C2_SCL IO IEM_SPWI IO GPI I L Signal I O Description TOUT_0 1 2 3 O PWM Timer Output I2C0_SDA IO IIC bus clock for channel 0 I2C0_SCL IO IIC bus data for channel 0 I2C1_SDA IO IIC bus clock for channel 1 I2C1_SCL IO IIC bus data for channel 1 I2C2_SDA IO IIC bus clock for channel 0 I2C2_SC...

Page 2226: ...TA 5 I GPI I L XCIDATA_6 CAM_A_DATA 6 I GPI I L XCIDATA_7 CAM_A_DATA 7 I GPI I L XCICLKENB CAM_A_CLKOUT O GPI I L XCIFIELD CAM_A_FIELD I GPI I L Signal I O Description CAM_A_PCLK O Pixel Clock driven by the Camera processor A CAM_A_VSYNC IO Vertical Sync driven by the Camera processor A CAM_A_HREF IO Horizontal Sync driven by the Camera processor A CAM_A_DATA 7 0 IO Pixel Data for YCbCr in 8 bit m...

Page 2227: ... SYS_VD 7 IO VEN_DATA 7 O GPI I L XVVD_8 LCD_VD 8 O SYS_VD 8 IO V656_DATA 0 O GPI I L XVVD_9 LCD_VD 9 O SYS_VD 9 IO V656_DATA 1 O GPI I L XVVD_10 LCD_VD 10 O SYS_VD 10 IO V656_DATA 2 O GPI I L XVVD_11 LCD_VD 11 O SYS_VD 11 IO V656_DATA 3 O GPI I L XVVD_12 LCD_VD 12 O SYS_VD 12 IO V656_DATA 4 O GPI I L XVVD_13 LCD_VD 13 O SYS_VD 13 IO V656_DATA 5 O GPI I L XVVD_14 LCD_VD 14 O SYS_VD 14 IO V656_DATA...

Page 2228: ...rect i80 System interface SYS_RS O Register State Select Signal for LCD Indirect i80 System interface SYS_WE O Write Enable for LCD Indirect i80 System interface SYS_VD 23 0 IO Video data input output for LCD Indirect i80 System interface SYS_OE O Output Enable for LCD Indirect i80 System interface VEN_HSYNC O Horizontal Sync Signal for 601 interface VEN_VSYNC O Vertical Sync Signal for 601 interf...

Page 2229: ..._0_DATA 4 IO GPI I L XMMC1DATA_1 SD_1_DATA 1 IO SD_0_DATA 5 IO GPI I L XMMC1DATA_2 SD_1_DATA 2 IO SD_0_DATA 6 IO GPI I L XMMC1DATA_3 SD_1_DATA 3 IO SD_0_DATA 7 IO GPI I L XMMC2CLK SD_2_CLK O GPI I L XMMC2CMD SD_2_CMD IO GPI I L XMMC2CDN SD_2_CDn I GPI I L XMMC2DATA_0 SD_2_DATA 0 IO GPI I L XMMC2DATA_1 SD_2_DATA 1 IO GPI I L XMMC2DATA_2 SD_2_DATA 2 IO GPI I L XMMC2DATA_3 SD_2_DATA 3 IO GPI I L XMMC...

Page 2230: ...nel 1 SD_1_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 1 SD_2_CLK O CLOCK SD SDIO MMC card interface channel 2 SD_2_CMD IO COMMAND RESPONSE SD SDIO MMC card interface channel 2 SD_2_CDn I CARD DETECT SD SDIO MMC card interface channel 2 SD_2_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 2 SD_3_CLK O CLOCK SD SDIO MMC card interface channel 3 SD_3_CMD IO COMMAND RESPONSE SD SD...

Page 2231: ... GPI I L XEINT_13 I HDMI_HPD I GPI I L XEINT_14 I GPI I L XEINT_15 I GPI I L XEINT_16 I KP_COL 0 IO GPI I L XEINT_17 I KP_COL 1 IO GPI I L XEINT_18 I KP_COL 2 IO GPI I L XEINT_19 I KP_COL 3 IO GPI I L XEINT_20 I KP_COL 4 IO GPI I L XEINT_21 I KP_COL 5 IO GPI I L XEINT_22 I KP_COL 6 IO GPI I L XEINT_23 I KP_COL 7 IO GPI I L XEINT_24 I KP_ROW 0 I GPI I L XEINT_25 I KP_ROW 1 I GPI I L XEINT_26 I KP_R...

Page 2232: ...10_UM 4 F TYPE SIZE BALL MAP 4 24 Signal I O Description XEINT 31 0 I External interrupts KP_COL 7 0 O KeyIF_Column_data 7 0 KP_ROW 7 0 I KeyIF_Row_data 7 0 HDMI_CEC IO HDMI CEC port HDMI_HPD I HDMI Hot plug ...

Page 2233: ...al I O Description I2S_0_SCLK IO IIS bus serial clock for channel 0 Lower Power Audio I2S_0_CDCLK IO IIS CODEC system clock for channel 0 Lower Power Audio I2S_0_LRCK IO IIS bus channel select clock for channel 0 Lower Power Audio I2S_0_SDI I IIS bus serial data input for channel 0 Lower Power Audio I2S_0_SDO 2 0 O IIS bus serial data output for channel 0 Lower Power Audio PCM_0_SCLK O PCM Serial ...

Page 2234: ...I L XMSMADDR_10 MSM_ADDR 10 I CAM_B_HREF I SROM_ADDR_16to22 2 O MHL_D3 O GPI I L XMSMADDR_11 MSM_ADDR 11 I CAM_B_FIELD I SROM_ADDR_16to22 3 O MHL_D4 O GPI I L XMSMADDR_12 MSM_ADDR 12 I CAM_B_CLKOUT O SROM_ADDR_16to22 4 O MHL_D5 O GPI I L XMSMADDR_13 MSM_ADDR 13 I KP_COL 0 I O SROM_ADDR_16to22 5 O MHL_D6 O GPI I L XMSMDATA_0 MSM_DATA 0 I O KP_COL 1 I O CF_DATA 0 I O MHL_D7 O GPI I L XMSMDATA_1 MSM_...

Page 2235: ...KP_ROW 13 I SROM_ADDR_16to22 6 O MHL_DE O GPI I L Signal I O Description MSM_ADDR 13 0 I MODEM MSM IF Address MSM_ADDR 13 should be 0 MSM_DATA 15 0 IO MODEM MSM IF Data MSM_CSn I MODEM MSM IF Chip Select MSM_WEn I MODEM MSM IF Write enable MSM_Rn I MODEM MSM IF Read enable MSM_IRQn O MODEM MSM IF Interrupt to MODEM MSM_ADVN I MODEM MSM IF Address Valid from MODEM Chip CAM_B_DATA 7 0 I Pixel Data d...

Page 2236: ... TS_CLK I TSI system clock 66MHz TS_SYNC I TSI synchronization control signal TS_VAL I TSI valid signal TS_DATA I TSI input data TS_ERROR I TSI error indicate signal MHL_D0 O MHL Data 0 MHL_D1 O MHL Data 1 MHL_D2 O MHL Data 2 MHL_D3 O MHL Data 3 MHL_D4 O MHL Data 4 MHL_D5 O MHL Data 5 MHL_D6 O MHL Data 6 MHL_D7 O MHL Data 7 MHL_D8 O MHL Data 8 MHL_D9 O MHL Data 9 MHL_D10 O MHL Data 10 MHL_D11 O MH...

Page 2237: ...110_UM 4 F TYPE SIZE BALL MAP 4 29 Signal I O Description MHL_D22 O MHL Data 22 MHL_D23 O MHL Data 23 MHL_HSYNC O MHL Hsync MHL_IDCK O MHL Interface Data Clock MHL_VSYNC O MHL Vsync MHL_DE O MHL Data Enable ...

Page 2238: ...LE O ONANDXL_ADDRVALID O Func3 O L XM0FALE NF_ALE O ONANDXL_SMCLK O Func3 O L XM0FWEN NF_FWEn O ONANDXL_RPn O Func3 O H XM0FREN NF_FREn O Func3 O H XM0FRNB_0 NF_RnB 0 I ONANDXL_INT 0 I Func3 I XM0FRNB_1 NF_RnB 1 I ONANDXL_INT 1 I Func3 I XM0FRNB_2 NF_RnB 2 I Func3 I XM0FRNB_3 NF_RnB 3 I Func3 I XM0ADDR_0 EBI_ADDR 0 O Func0 O L XM0ADDR_1 EBI_ADDR 1 O Func0 O L XM0ADDR_2 EBI_ADDR 2 O Func0 O L XM0AD...

Page 2239: ...5 EBI_DATA 15 IO Func0 O L Signal I O Description SROM_CSn 5 4 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 3 2 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 1 0 O Memory Port 0 SROM Chip select support up to 2 memory bank EBI_OEn O Memory Port 0 SROM OneNAND Output Enable EBI_WEn O Memory Port 0 SROM OneNAND Write Enable EBI_BEn 1 0 O Memory Port 0...

Page 2240: ...ect bank 1 NFCSn 2 O Memory Port 0 NAND Chip Select bank 2 NFCSn 3 O Memory Port 0 NAND Chip Select bank 3 ONANDXL_ADDRVALID O OneNANDXL Flash Address valid ONANDXL_SMCLK O OneNANDXL Flash clock ONANDXL_RPn O OneNANDXL Flash reset ONANDXL_INT 1 0 I OneNANDXL Flash Interrupt signal from OneNAND Device ...

Page 2241: ...ory port 1DRAM Data Differential Strobe neg only LPDDR2 4bit XM1CKE_0 XM1CKE_1 IO Memory port 1DRAM Clock Enable 2bit XM1SCLK IO Memory port 1DRAM Clock XM1nSCLK IO Memory port 1DRAM Inverted Clock of Xm1SCLK XM1CSn_0 XM1CSn_1 IO Memory port 1DRAM Chip Select support up to 2 memory bank 2bit XM1RASn IO Memory port 1DRAM Row Address Strobe XM1CASn IO Memory port 1DRAM Column Address Strobe XM1WEn I...

Page 2242: ...ory port 2DRAM Data Differential Strobe neg only LPDDR2 4bit XM2CKE_0 XM2CKE_1 IO Memory port 2DRAM Clock Enable 2bit XM2SCLK IO Memory port 2DRAM Clock XM2nSCLK IO Memory port 2DRAM Inverted Clock of Xm1SCLK XM2CSn_0 XM2CSn_1 IO Memory port 2DRAM Chip Select support up to 2 memory bank 2bit XM2RASn IO Memory port 2DRAM Row Address Strobe XM2CASn IO Memory port 2DRAM Column Address Strobe XM2WEn I...

Page 2243: ... logic Pull down resistor is connected XJTDI I XjTDI TAP Controller Data Input is the serial input for test instructions and data Pull up resistor is connected XJTDO O XjTDO TAP Controller Data Output is the serial output for test instructions and data XJDBGSEL I JTAG selection 0 CORTEXA8 Core JTAG 1 Peripherals JTAG RESET etc Dedicated Ball Name I O Description XOM_0 XOM_5 I Operating Mode contro...

Page 2244: ...nal capacitor connection XHDMITX0P O HDMI Phy TX0 P XHDMITX0N O HDMI Phy TX0 N XHDMITX1P O HDMI Phy TX1 P XHDMITX1N O HDMI Phy TX1 N XHDMITX2P O HDMI Phy TX2 P XHDMITX2N O HDMI Phy TX2 N XHDMITXCP O HDMI Phy TX Clock P XHDMITXCN O HDMI Phy TX Clock N XHDMIREXT I HDMI Phy Registance XHDMIXTI I HDMI crystal input XHDMIXTO O HDMI crystal output XMIPIMDP0 IO Master DATA LANE0 DP for MIPI DPHY XMIPIMDP...

Page 2245: ...K IO Slave CLK Lane DN for MIPI DPHY XMIPIVREG_0P4V IO Regulator capacitor for MIPI DPHY USB OTG USB HOST 1 1 Dedicated Ball Name I O Description XUOTGDRVVUBS O USB OTG charge pump enable XUHOSTPWREN O USB HOST charge pump enable XUHOSTOVERCUR I USB HOST over current flag XUOTGDP IO USB OTG Data pin DATA XUOTGREXT IO USB OTG External 44 2ohm 1 resistor connection XUOTGDM IO USB OTG Data pin DATA X...

Page 2246: ...ck Enable POP_CSB_A IO POP_A DRAM Chip Select POP_RASB_A IO POP_A DRAM Row Address Strobe POP_CASB_A IO POP_A DRAM Column Address Strobe POP_WEB_A IO POP_A DRAM Write Enable POP_BA0_A POP_BA1_A IO POP_A DRAM Bank Address POP_LDM_A IO POP_A DRAM Lower data input mask POP_LDQS_A IO POP_A DRAM Lower data strobe POP_UDM_A IO POP_A DRAM upper data input mask POP_UDQS_A IO POP_A DRAM upper data strobe P...

Page 2247: ...6 K16 XADCAIN_7 L15 XADCAIN_8 D16 XADCAIN_9 D14 VDD_ADC H17 P20 VSS_ADC H18 N20 DAC XDACCOMP K25 XDACIREF K22 XDACOUT K24 XDACVREF L22 VDD_DAC_A K20 VSS_DAC_A K21 VDD_DAC J22 VSS_DAC J21 MIPI DPHY XMIPIMDN0 G10 XMIPIMDN1 F11 XMIPIMDN2 G13 XMIPIMDN3 G14 XMIPIMDNCLK G12 XMIPIMDP0 F10 XMIPIMDP1 G11 XMIPIMDP2 F13 XMIPIMDP3 F14 XMIPIMDPCLK F12 XMIPISDN0 G15 XMIPISDN1 F16 XMIPISDN2 F18 XMIPISDN3 F19 XMI...

Page 2248: ... VSS_MIPI H13 H16 HDMI PHY XHDMIREXT P22 XHDMITX0N N26 XHDMITX0P N27 XHDMITX1N M26 XHDMITX1P M27 XHDMITX2N L26 XHDMITX2P L27 XHDMITXCN P26 XHDMITXCP P27 XHDMIXTI T22 XHDMIXTO R22 VDD_HDMI M22 VDD_HDMI_PLL N21 VDD_HDMI_OSC L20 VSS_HDMI M21 VSS_HDMI_PLL N22 VSS_HDMI_OSC L21 USB OTG XUOTGDM F6 XUOTGDP G6 XUOTGID D8 XUOTGREXT J6 XUOTGVBUS D9 VDD_UOTG_A F9 VDD_UOTG_D H10 VSS_UOTG_A H11 VSS_UOTG_AC G9 V...

Page 2249: ...ll No USB HOST XUHOSTDM G8 XUHOSTDP F8 XUHOSTREXT D10 VDD_UHOST_A D11 VDD_UHOST_D K12 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 APLL VDD_APLL N6 VSS_APLL P6 MPLL VDD_MPLL T6 VSS_MPLL T7 VPLL VDD_VPLL P8 VSS_VPLL P7 EPLL VDD_EPLL M7 VSS_EPLL N7 EPLL_FILTER T8 ...

Page 2250: ...DDR_11 AE26 XM0ADDR_12 AF23 XM0ADDR_13 AF22 XM0ADDR_14 AE23 XM0ADDR_15 AF26 XM0ADDR_2 V20 XM0ADDR_3 W21 XM0ADDR_4 W22 XM0ADDR_5 AD27 XM0ADDR_6 AD26 XM0ADDR_7 AF25 XM0ADDR_8 AF24 XM0ADDR_9 AE22 XM0BEN_0 AA24 XM0BEN_1 Y21 XM0CSN_0 U22 XM0CSN_1 W24 XM0CSN_2 AE24 XM0CSN_3 AA25 XM0CSN_4 Y25 XM0CSN_5 Y24 XM0DATA_0 V25 XM0DATA_1 U26 XM0DATA_10 R27 XM0DATA_11 R25 XM0DATA_12 P24 XM0DATA_13 M25 XM0DATA_14 J...

Page 2251: ...ATA_RDN AB26 XM0FALE W25 XM0FCLE Y26 XM0FREN W27 XM0FRNB_0 H26 XM0FRNB_1 AC26 XM0FRNB_2 V21 XM0FRNB_3 AC27 XM0FWEN AA27 XM0OEN G27 XM0WAITN V22 XM0WEN G26 VDD_M0 T20 U20 LCD XVHSYNC L14 XVSYS_OE G21 XVVCLK F22 XVVD_0 D20 XVVD_1 D21 XVVD_10 B25 XVVD_11 G24 XVVD_12 G22 XVVD_13 B26 XVVD_14 E26 XVVD_15 D27 XVVD_16 C25 XVVD_17 H22 XVVD_18 C26 XVVD_19 G25 XVVD_2 D22 XVVD_20 F20 ...

Page 2252: ...VD_9 F21 XVVDEN D19 XVVSYNC D18 XVVSYNC_LDI H24 VDD_LCD H19 CAMERA XCICLKENB H3 XCIDATA_0 J7 XCIDATA_1 M4 XCIDATA_2 G2 XCIDATA_3 H2 XCIDATA_4 H1 XCIDATA_5 G3 XCIDATA_6 J2 XCIDATA_7 J3 XCIFIELD F3 XCIHREF M6 XCIPCLK F1 XCIVSYNC K7 VDD_CAM H7 AUDIO XI2S0CDCLK M17 XI2S0LRCK U21 XI2S0SCLK N17 XI2S0SDI R24 XI2S0SDO_0 M24 XI2S0SDO_1 R20 XI2S0SDO_2 P18 XI2S1CDCLK T21 XI2S1LRCK R21 ...

Page 2253: ... AG19 XMSMADDR_1 AD18 XMSMADDR_10 AA20 XMSMADDR_11 AG23 XMSMADDR_12 AE18 XMSMADDR_13 AG17 XMSMADDR_2 AE20 XMSMADDR_3 AE17 XMSMADDR_4 AF21 XMSMADDR_5 AE21 XMSMADDR_6 AD20 XMSMADDR_7 AE19 XMSMADDR_8 AD19 XMSMADDR_9 AG22 XMSMADVN AF12 XMSMCSN AD14 XMSMDATA_0 AG11 XMSMDATA_1 AF14 XMSMDATA_10 AD15 XMSMDATA_11 AG13 XMSMDATA_12 AF15 XMSMDATA_13 AE16 XMSMDATA_14 AF16 XMSMDATA_15 AE15 XMSMDATA_2 AG14 XMSMD...

Page 2254: ...MSMRN AD13 XMSMWEN AE13 VDD_MODEM AA21 KEY XEINT_16 N3 XEINT_17 N2 XEINT_18 W4 XEINT_19 M3 XEINT_20 V2 XEINT_21 L3 XEINT_22 K1 XEINT_23 U3 XEINT_24 L2 XEINT_25 V4 XEINT_26 K3 XEINT_27 P4 XEINT_28 K2 XEINT_29 L4 XEINT_30 T2 XEINT_31 K4 VDD_KEY L10 System 0 XXTI AB2 XXTO AB3 XOM_0 Y4 XOM_1 Y3 XOM_2 Y2 XOM_3 AA6 XOM_4 Y1 XOM_5 AA2 XPWRRGTON AA7 XNRESET AB6 XNRSTOUT Y7 ...

Page 2255: ...VBUS F7 XUHOSTPWREN D6 XUHOSTOVERCUR H6 XDDR2SEL G7 XUSBXTI L6 XUSBXTO K6 XJTRSTN U18 XJTMS V18 XJTCK W20 XJTDI T18 XJTDO R18 XJDBGSEL AG24 VDD_SYS0 J8 M8 P21 System 1 XEINT_8 Y6 XEINT_9 V6 XEINT_10 U2 XEINT_11 AE2 XEINT_12 P2 XEINT_13 W3 XEINT_14 M2 XEINT_15 W1 VDD_SYS1 L7 External Peri 0 XMMC0CDN AG10 XMMC0CLK AF8 XMMC0CMD AD11 XMMC0DATA_0 AE11 XMMC0DATA_1 AF11 XMMC0DATA_2 AD12 ...

Page 2256: ...PICSN_0 AF4 XSPIMISO_0 AE3 XSPIMOSI_0 AE5 XURXD_0 AB14 XUTXD_0 AB11 XUCTSN_0 AE12 XURTSN_0 AB10 XURXD_1 AA14 XUTXD_1 AB13 XUCTSN_1 AB12 XURTSN_1 AB9 XI2C0SDA AB8 XI2C0SCL AD7 XPWMTOUT_0 Y16 XPWMTOUT_1 AB16 XPWMTOUT_2 AD9 XPWMTOUT_3 AA16 VDD_EXT0 Y18 External Peri 1 XMMC2CDN Y20 XMMC2CLK AA18 XMMC2CMD Y22 XMMC2DATA_0 AA19 XMMC2DATA_1 AA22 XMMC2DATA_2 AB22 XMMC2DATA_3 AB21 XI2C1SCL F2 XI2C1SDA H4 XI...

Page 2257: ...3 L12 VDD_EXT1 H8 L18 External Peri 2 XMMC3CDN Y15 XMMC3CLK AB20 XMMC3CMD Y19 XMMC3DATA_0 AB18 XMMC3DATA_1 Y17 XMMC3DATA_2 AB15 XMMC3DATA_3 AA17 XSPICLK_1 AF3 XSPICSN_1 AF5 XSPIMISO_1 AE4 XSPIMOSI_1 AG4 VDD_EXT2 AB17 RTC Clock Out XRTCCLKO AB7 VDD_CKO N10 RTC XRTCXTI AA3 XRTCXTO AA4 VDD_RTC N8 EFUSE Security XEFFSOURCE_0 U24 ...

Page 2258: ...R10 R11 R12 T10 T11 T12 U11 Alive VDD_ALIVE K8 L8 MCP Power Power Domain Ball Name Ball No MCP OneDRAM A IO Power POP_INTB_A C16 POP_A0_A C9 POP_A1_A C8 POP_A2_A B9 POP_A3_A C7 POP_A4_A B15 POP_A5_A A17 POP_A6_A C13 POP_A7_A A15 POP_A8_A C14 POP_A9_A C15 POP_A10_A B10 POP_A11_A B13 POP_A12_A C12 POP_BA0_A B11 POP_BA1_A A10 POP_CASB_A C11 POP_RASB_A A11 POP_WEB_A B14 POP_CKE_A D13 POP_CLK_A B12 POP...

Page 2259: ...Q13_A C22 POP_DQ14_A B24 POP_DQ15_A C20 POP_LDM_A C4 POP_LDQS_A C3 POP_UDM_A A21 POP_UDQS_A B21 VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAM B IO Power POP_INTB_B AF19 VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM Core Power VDD_ODRAM A16 AC3 AG16 E3 F24 MDDR IO Power POP_TQ E1 VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 MDDR Core Power VDD_MDDR AB4 AB25 F4 H25 N4 T26 OneNAND IO Power POP_CEB_O Y27 VDD_O...

Page 2260: ...21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 VSS_UOTG_A...

Page 2261: ...S5PC110_UM 4 F TYPE SIZE BALL MAP 4 1 6 PACKAGE DIMENSION Figure 4 2 S5PC110 Package Dimension 596 FCFBGA Top View 4 53 ...

Page 2262: ...S5PC110_UM 4 F TYPE SIZE BALL MAP Figure 4 3 S5PC110 Package Dimension 596 FCFBGA Side View 4 54 ...

Page 2263: ...S5PC110_UM 5 G TYPE SIZE BALL MAP 5 G TYPE SIZE BALL MAP 5 1 PIN ASSIGNMENT 5 1 1 PIN ASSIGNMENT DIAGRAM 596 BALL FCFBGA POP Figure 5 1 S5PC110 Pin Assignment 596 FCFBGA Bottom View 5 1 ...

Page 2264: ...0 POP_DQ21_A C13 POP_A6_A A8 POP_DQS1_A B1 VSS B21 POP_DQS3_A C14 POP_A8_A A9 POP_DQM1_A B2 POP_DQ4_A B22 POP_DQ24_A C15 POP_A9_A A10 POP_BA1_A B3 POP_DQ5_A B23 VSS C16 POP_INTB_A A11 POP_RASB_A B4 POP_DQ6_A B24 POP_DQ29_A C17 POP_DQM2_A A12 POP_CLKB_A B5 POP_DQ10_A B25 XVVD_10 C18 POP_DQ18_A A13 POP_A13_A B6 POP_DQ13_A B26 XVVD_13 C19 POP_DQ22_A A14 POP_BA2_A B7 POP_DQ14_A B27 VSS C20 POP_DQ31_A ...

Page 2265: ... VDD_ODRAM F18 XMIPISDN2 G13 XMIPIMDN2 D9 XUOTGVBUS E25 XVVD_7 F19 XMIPISDN3 G14 XMIPIMDN3 D10 XUHOSTREXT E26 XVVD_14 F20 XVVD_20 G15 XMIPISDN0 D11 VDD_UHOST_A E27 XVVD_22 F21 XVVD_9 G16 XMIPISDP1 D12 VSS_UHOST_A F1 XCIPCLK F22 XVVCLK G17 XMIPISDPCLK D13 POP_CKE_A F2 XI2C1SCL F24 VDD_ODRAM G18 XMIPISDP2 D14 XADCAIN_9 F3 XCIFIELD F25 VSS G19 XMIPISDP3 D15 XADCAIN_1 F4 VDD_MDDR F26 VDD_ONAND G20 XVV...

Page 2266: ...DD_ALIVE H9 VSS_UOTG_D J3 XCIDATA_7 K13 VDD_MIPI_PLL L10 VDD_KEY H10 VDD_UOTG_D J4 XI2C2SCL K14 XMIPIVREG_0P4V L11 XURXD_3 H11 VSS_UOTG_A J6 XUOTGREXT K15 VDD_MIPI_A L12 XUTXD_3 H12 VSS_UHOST_D J7 XCIDATA_0 K16 XADCAIN_6 L13 VSS_UHOST_AC H13 VSS_MIPI J8 VDD_SYS0 K17 XADCAIN_5 L14 XVHSYNC H14 VDD_MIPI_D J20 VDD_AUD K18 XADCAIN_0 L15 XADCAIN_7 H15 VDD_MIPI_D J21 VSS_DAC K20 VDD_DAC_A L16 XADCAIN_4 H...

Page 2267: ...DMITX1P N27 XHDMITX0P P27 XHDMITXCP M4 XCIDATA_1 N1 VDD_MDDR_IO P1 VSS R1 VDD_ARM M6 XCIHREF N2 XEINT_17 P2 XEINT_12 R2 VDD_ARM M7 VDD_EPLL N3 XEINT_16 P3 XEINT_7 R3 VDD_ARM M8 VDD_SYS0 N4 VDD_MDDR P4 XEINT_27 R4 VDD_ARM M10 XI2C2SDA N6 VDD_APLL P6 VSS_APLL R6 VDD_ARM M11 VDD_INT N7 VSS_EPLL P7 VSS_VPLL R7 VDD_ARM M12 VDD_INT N8 VDD_RTC P8 VDD_VPLL R8 VDD_ARM M13 VDD_INT N10 VDD_CKO P10 VSS R10 VD...

Page 2268: ...1 VSS T25 XPCM0EXTCLK U21 XI2S0LRCK V17 VDD_INT T2 XEINT_30 T26 VDD_MDDR U22 XM0CSN_0 V18 XJTMS T3 XEINT_5 T27 VDD_ONAND_IO U24 XEFFSOURCE_0 V20 XM0ADDR_2 T4 VSS U1 VDD_MDDR_IO U25 VSS V21 XM0FRNB_2 T6 VDD_MPLL U2 XEINT_10 U26 XM0DATA_1 V22 XM0WAITN T7 VSS_MPLL U3 XEINT_23 U27 XM0DATA_9 V24 XPCM0SCLK T8 EPLL_FILTER U4 VSS V1 VDD_MDDR_IO V25 XM0DATA_0 T10 VDD_ARM U6 XEINT_2 V2 XEINT_20 V26 XPCM0SIN...

Page 2269: ...6 XPCM0FSYNC Y20 XMMC2CDN AA15 VSS AB10 XURTSN_0 W27 XM0FREN Y21 XM0BEN_1 AA16 XPWMTOUT_3 AB11 XUTXD_0 Y1 XOM_4 Y22 XMMC2CMD AA17 XMMC3DATA_3 AB12 XUCTSN_1 Y2 XOM_2 Y24 XM0CSN_5 AA18 XMMC2CLK AB13 XUTXD_1 Y3 XOM_1 Y25 XM0CSN_4 AA19 XMMC2DATA_0 AB14 XURXD_0 Y4 XOM_0 Y26 XM0FCLE AA20 XMSMADDR_10 AB15 XMMC3DATA_2 Y6 XEINT_8 Y27 POP_CEB_O AA21 VDD_MODEM AB16 XPWMTOUT_1 Y7 XNRSTOUT AA1 VDD_MDDR_IO AA22...

Page 2270: ...XM0ADDR_0 AD20 XMSMADDR_6 AE17 XMSMADDR_3 AF10 XMMC0DATA_3 AC26 XM0FRNB_1 AD25 VDD_ODRAMB_IO AE18 XMSMADDR_12 AF11 XMMC0DATA_1 AC27 XM0FRNB_3 AD26 XM0ADDR_6 AE19 XMSMADDR_7 AF12 XMSMADVN AD1 VSS AD27 XM0ADDR_5 AE20 XMSMADDR_2 AF13 XMSMIRQN AD2 XEINT_4 AE1 VDD_ODRAMB_IO AE21 XMSMADDR_5 AF14 XMSMDATA_1 AD3 XEINT_6 AE2 XEINT_11 AE22 XM0ADDR_9 AF15 XMSMDATA_12 AD6 VDD_INT AE3 XSPIMISO_0 AE23 XM0ADDR_1...

Page 2271: ...8 AG17 XMSMADDR_13 AF25 XM0ADDR_7 AG18 XMSMDATA_6 AF26 XM0ADDR_15 AG19 XMSMADDR_0 AF27 VSS AG20 VDD_ODRAMB_IO AG1 VSS AG21 VSS AG2 VSS AG22 XMSMADDR_9 AG3 VDD_ODRAMB_IO AG23 XMSMADDR_11 AG4 XSPIMOSI_1 AG24 XJDBGSEL AG5 XSPICLK_0 AG25 VDD_ODRAMB_IO AG6 VDD_INT AG26 VSS AG7 VSS AG27 VSS AG8 VDD_ODRAMB_IO AG9 XMMC1CDN AG10 XMMC0CDN AG11 XMSMDATA_0 AG12 XMSMDATA_5 AG13 XMSMDATA_11 AG14 XMSMDATA_2 AG15...

Page 2272: ...DD_EXT1 H8 L18 EXT1 VDD_EXT2 AB17 EXT2 VDD_CKO N10 RTC CLKO VDD_RTC N8 RTC Internal Logic VDD_INT AD6 AE6 AF6 AG6 M11 M12 M13 M14 M15 M16 T17 U17 V14 V15 V16 V17 Internal logic VDD_ARM R1 R2 R3 R4 R6 R7 R8 R10 R11 R12 T10 T11 T12 U11 Cortex A8 core VDD_ALIVE K8 L8 Alive logic Analog High Speed VDD_ADC H17 P20 ADC VDD_DAC_A K20 DAC Analog VDD_DAC J22 DAC Digital VDD_MIPI_A K15 MIPI 1 8V VDD_MIPI_D ...

Page 2273: ... VDD_EPLL M7 EPLL MCP VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAM A VDDQ VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM B VDDQ VDD_ODRAM A16 AC3 AG16 E3 F24 OneDRAM CORE VDD VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 DDR VDDQ VDD_MDDR AB4 AB25 F4 H25 N4 T26 DDR CORE VDD VDD_ONAND_IO J26 T27 OneNAND VCCQ VDD_ONAND AA26 F26 OneNAND VCC ...

Page 2274: ... AG7 AG15 AG21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T8 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D...

Page 2275: ...UART_2_RTSn O GPI I L Signal I O Description UART_0_RXD I UART 0 receives data input UART_0_TXD O UART 0 transmits data output UART_0_CTSn I UART 0 clear to send input signal UART_0_RTSn O UART 0 request to send output signal UART_1_RXD I UART 1 receives data input UART_1_TXD O UART 1 transmits data output UART_1_CTSn I UART 1 clear to send input signal UART_1_RTSn O UART 1 request to send output ...

Page 2276: ..._1_MISO IO GPI I L XSPIMOSI_1 SPI_1_MOSI IO GPI I L Signal I O Description SPI_0_CLK IO SPI clock for channel 0 SPI_0_nSS IO SPI chip select only for slave mode for channel 0 SPI_0_MISO IO SPI master input slave output line for channel 0 SPI_0_MOSI IO SPI master output slave input line for channel 0 SPI_1_CLK IO SPI clock for channel 1 SPI_1_nSS IO SPI chip select only for slave mode for channel 1...

Page 2277: ...el 1 I2S_1_LRCK IO IIS bus channel select clock for channel 1 I2S_1_SDI I IIS bus serial data input for channel 1 I2S_1_SDO O IIS bus serial data output for channel 1 PCM_2_SCLK O PCM Serial Shift Clock for channel 2 PCM_2_EXTCLK I PCM External Clock for channel 2 PCM_2_FSYNC O PCM Sync indicating start of word for channel 2 PCM_2_SIN I PCM Serial Data Input for channel 2 PCM_2_SOUT O PCM Serial D...

Page 2278: ... AC97SDO O AC link Serial Data output to AC97 Codec I2S_2_SCLK IO IIS bus serial clock for channel 2 I2S_2_CDCLK IO IIS CODEC system clock for channel 2 I2S_2_LRCK IO IIS bus channel select clock for channel 2 I2S_2_SDI I IIS bus serial data input for channel 2 I2S_2_SDO O IIS bus serial data output for channel 2 ...

Page 2279: ...XI2C1SDA I2C1_SDA IO GPI I L XI2C1SCL I2C1_SCL IO GPI I L XI2C2SDA I2C2_SDA IO IEM_SCLK IO GPI I L XI2C2SCL I2C2_SCL IO IEM_SPWI IO GPI I L Signal I O Description TOUT_0 1 2 3 O PWM Timer Output I2C0_SDA IO IIC bus clock for channel 0 I2C0_SCL IO IIC bus data for channel 0 I2C1_SDA IO IIC bus clock for channel 1 I2C1_SCL IO IIC bus data for channel 1 I2C2_SDA IO IIC bus clock for channel 0 I2C2_SC...

Page 2280: ...TA 5 I GPI I L XCIDATA_6 CAM_A_DATA 6 I GPI I L XCIDATA_7 CAM_A_DATA 7 I GPI I L XCICLKENB CAM_A_CLKOUT O GPI I L XCIFIELD CAM_A_FIELD I GPI I L Signal I O Description CAM_A_PCLK O Pixel Clock driven by the Camera processor A CAM_A_VSYNC IO Vertical Sync driven by the Camera processor A CAM_A_HREF IO Horizontal Sync driven by the Camera processor A CAM_A_DATA 7 0 IO Pixel Data for YCbCr in 8 bit m...

Page 2281: ... SYS_VD 7 IO VEN_DATA 7 O GPI I L XVVD_8 LCD_VD 8 O SYS_VD 8 IO V656_DATA 0 O GPI I L XVVD_9 LCD_VD 9 O SYS_VD 9 IO V656_DATA 1 O GPI I L XVVD_10 LCD_VD 10 O SYS_VD 10 IO V656_DATA 2 O GPI I L XVVD_11 LCD_VD 11 O SYS_VD 11 IO V656_DATA 3 O GPI I L XVVD_12 LCD_VD 12 O SYS_VD 12 IO V656_DATA 4 O GPI I L XVVD_13 LCD_VD 13 O SYS_VD 13 IO V656_DATA 5 O GPI I L XVVD_14 LCD_VD 14 O SYS_VD 14 IO V656_DATA...

Page 2282: ...ect i80 System interface SYS_RS O Register State Select Signal for LCD Indirect i80 System interface SYS_WE O Write Enable for LCD Indirect i80 System interface SYS_VD 23 0 IO Video data input output for LCD Indirect i80 System interface SYS_OE O Output Enable for LCD Indirect i80 System interface VEN_HSYNC O Horizontal Sync Signal for 601 interface VEN_VSYNC O Vertical Sync Signal for 601 interfa...

Page 2283: ...ATA_1 SD_1_DATA 1 IO SD_0_DATA 5 IO GPI I L XMMC1DATA_2 SD_1_DATA 2 IO SD_0_DATA 6 IO GPI I L XMMC1DATA_3 SD_1_DATA 3 IO SD_0_DATA 7 IO GPI I L XMMC2CLK SD_2_CLK O SPI_2_CLK IO GPI I L XMMC2CMD SD_2_CMD IO SPI_2_nSS IO GPI I L XMMC2CDN SD_2_CDn I SPI_2_MISO IO GPI I L XMMC2DATA_0 SD_2_DATA 0 IO SPI_2_MOSI IO GPI I L XMMC2DATA_1 SD_2_DATA 1 IO GPI I L XMMC2DATA_2 SD_2_DATA 2 IO GPI I L XMMC2DATA_3 ...

Page 2284: ...channel 2 SD_2_CMD IO COMMAND RESPONSE SD SDIO MMC card interface channel 2 SD_2_CDn I CARD DETECT SD SDIO MMC card interface channel 2 SD_2_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 2 SD_3_CLK O CLOCK SD SDIO MMC card interface channel 3 SD_3_CMD IO COMMAND RESPONSE SD SDIO MMC card interface channel 3 SD_3_CDn I CARD DETECT SD SDIO MMC card interface channel 3 SD_3_DATA 3 0 IO DATA...

Page 2285: ... GPI I L XEINT_13 I HDMI_HPD I GPI I L XEINT_14 I GPI I L XEINT_15 I GPI I L XEINT_16 I KP_COL 0 IO GPI I L XEINT_17 I KP_COL 1 IO GPI I L XEINT_18 I KP_COL 2 IO GPI I L XEINT_19 I KP_COL 3 IO GPI I L XEINT_20 I KP_COL 4 IO GPI I L XEINT_21 I KP_COL 5 IO GPI I L XEINT_22 I KP_COL 6 IO GPI I L XEINT_23 I KP_COL 7 IO GPI I L XEINT_24 I KP_ROW 0 I GPI I L XEINT_25 I KP_ROW 1 I GPI I L XEINT_26 I KP_R...

Page 2286: ...10_UM 5 G TYPE SIZE BALL MAP 5 24 Signal I O Description XEINT 31 0 I External interrupts KP_COL 7 0 O KeyIF_Column_data 7 0 KP_ROW 7 0 I KeyIF_Row_data 7 0 HDMI_CEC IO HDMI CEC port HDMI_HPD I HDMI Hot plug ...

Page 2287: ...al I O Description I2S_0_SCLK IO IIS bus serial clock for channel 0 Lower Power Audio I2S_0_CDCLK IO IIS CODEC system clock for channel 0 Lower Power Audio I2S_0_LRCK IO IIS bus channel select clock for channel 0 Lower Power Audio I2S_0_SDI I IIS bus serial data input for channel 0 Lower Power Audio I2S_0_SDO 2 0 O IIS bus serial data output for channel 0 Lower Power Audio PCM_0_SCLK O PCM Serial ...

Page 2288: ...I L XMSMADDR_10 MSM_ADDR 10 I CAM_B_HREF I SROM_ADDR_16to22 2 O MHL_D3 O GPI I L XMSMADDR_11 MSM_ADDR 11 I CAM_B_FIELD I SROM_ADDR_16to22 3 O MHL_D4 O GPI I L XMSMADDR_12 MSM_ADDR 12 I CAM_B_CLKOUT O SROM_ADDR_16to22 4 O MHL_D5 O GPI I L XMSMADDR_13 MSM_ADDR 13 I KP_COL 0 I O SROM_ADDR_16to22 5 O MHL_D6 O GPI I L XMSMDATA_0 MSM_DATA 0 I O KP_COL 1 I O CF_DATA 0 I O MHL_D7 O GPI I L XMSMDATA_1 MSM_...

Page 2289: ...KP_ROW 13 I SROM_ADDR_16to22 6 O MHL_DE O GPI I L Signal I O Description MSM_ADDR 13 0 I MODEM MSM IF Address MSM_ADDR 13 should be 0 MSM_DATA 15 0 IO MODEM MSM IF Data MSM_CSn I MODEM MSM IF Chip Select MSM_WEn I MODEM MSM IF Write enable MSM_Rn I MODEM MSM IF Read enable MSM_IRQn O MODEM MSM IF Interrupt to MODEM MSM_ADVN I MODEM MSM IF Address Valid from MODEM Chip CAM_B_DATA 7 0 I Pixel Data d...

Page 2290: ... TS_CLK I TSI system clock 66MHz TS_SYNC I TSI synchronization control signal TS_VAL I TSI valid signal TS_DATA I TSI input data TS_ERROR I TSI error indicate signal MHL_D0 O MHL Data 0 MHL_D1 O MHL Data 1 MHL_D2 O MHL Data 2 MHL_D3 O MHL Data 3 MHL_D4 O MHL Data 4 MHL_D5 O MHL Data 5 MHL_D6 O MHL Data 6 MHL_D7 O MHL Data 7 MHL_D8 O MHL Data 8 MHL_D9 O MHL Data 9 MHL_D10 O MHL Data 10 MHL_D11 O MH...

Page 2291: ...110_UM 5 G TYPE SIZE BALL MAP 5 29 Signal I O Description MHL_D22 O MHL Data 22 MHL_D23 O MHL Data 23 MHL_HSYNC O MHL Hsync MHL_IDCK O MHL Interface Data Clock MHL_VSYNC O MHL Vsync MHL_DE O MHL Data Enable ...

Page 2292: ...LE O ONANDXL_ADDRVALID O Func3 O L XM0FALE NF_ALE O ONANDXL_SMCLK O Func3 O L XM0FWEN NF_FWEn O ONANDXL_RPn O Func3 O H XM0FREN NF_FREn O Func3 O H XM0FRNB_0 NF_RnB 0 I ONANDXL_INT 0 I Func3 I XM0FRNB_1 NF_RnB 1 I ONANDXL_INT 1 I Func3 I XM0FRNB_2 NF_RnB 2 I Func3 I XM0FRNB_3 NF_RnB 3 I Func3 I XM0ADDR_0 EBI_ADDR 0 O Func0 O L XM0ADDR_1 EBI_ADDR 1 O Func0 O L XM0ADDR_2 EBI_ADDR 2 O Func0 O L XM0AD...

Page 2293: ...5 EBI_DATA 15 IO Func0 O L Signal I O Description SROM_CSn 5 4 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 3 2 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 1 0 O Memory Port 0 SROM Chip select support up to 2 memory bank EBI_OEn O Memory Port 0 SROM OneNAND Output Enable EBI_WEn O Memory Port 0 SROM OneNAND Write Enable EBI_BEn 1 0 O Memory Port 0...

Page 2294: ...ect bank 1 NFCSn 2 O Memory Port 0 NAND Chip Select bank 2 NFCSn 3 O Memory Port 0 NAND Chip Select bank 3 ONANDXL_ADDRVALID O OneNANDXL Flash Address valid ONANDXL_SMCLK O OneNANDXL Flash clock ONANDXL_RPn O OneNANDXL Flash reset ONANDXL_INT 1 0 I OneNANDXL Flash Interrupt signal from OneNAND Device ...

Page 2295: ...ory port 1DRAM Data Differential Strobe neg only LPDDR2 4bit XM1CKE_0 XM1CKE_1 IO Memory port 1DRAM Clock Enable 2bit XM1SCLK IO Memory port 1DRAM Clock XM1nSCLK IO Memory port 1DRAM Inverted Clock of Xm1SCLK XM1CSn_0 XM1CSn_1 IO Memory port 1DRAM Chip Select support up to 2 memory bank 2bit XM1RASn IO Memory port 1DRAM Row Address Strobe XM1CASn IO Memory port 1DRAM Column Address Strobe XM1WEn I...

Page 2296: ...ory port 2DRAM Data Differential Strobe neg only LPDDR2 4bit XM2CKE_0 XM2CKE_1 IO Memory port 2DRAM Clock Enable 2bit XM2SCLK IO Memory port 2DRAM Clock XM2nSCLK IO Memory port 2DRAM Inverted Clock of Xm1SCLK XM2CSn_0 XM2CSn_1 IO Memory port 2DRAM Chip Select support up to 2 memory bank 2bit XM2RASn IO Memory port 2DRAM Row Address Strobe XM2CASn IO Memory port 2DRAM Column Address Strobe XM2WEn I...

Page 2297: ... logic Pull down resistor is connected XJTDI I XjTDI TAP Controller Data Input is the serial input for test instructions and data Pull up resistor is connected XJTDO O XjTDO TAP Controller Data Output is the serial output for test instructions and data XJDBGSEL I JTAG selection 0 CORTEXA8 Core JTAG 1 Peripherals JTAG RESET etc Dedicated Ball Name I O Description XOM_0 XOM_5 I Operating Mode contro...

Page 2298: ...nal capacitor connection XHDMITX0P O HDMI Phy TX0 P XHDMITX0N O HDMI Phy TX0 N XHDMITX1P O HDMI Phy TX1 P XHDMITX1N O HDMI Phy TX1 N XHDMITX2P O HDMI Phy TX2 P XHDMITX2N O HDMI Phy TX2 N XHDMITXCP O HDMI Phy TX Clock P XHDMITXCN O HDMI Phy TX Clock N XHDMIREXT I HDMI Phy Registance XHDMIXTI I HDMI crystal input XHDMIXTO O HDMI crystal output XMIPIMDP0 IO Master DATA LANE0 DP for MIPI DPHY XMIPIMDP...

Page 2299: ...PI DPHY XMIPISDPCLK IO Slave CLK Lane DP for MIPI DPHY XMIPISDNCLK IO Slave CLK Lane DN for MIPI DPHY XMIPIVREG_0P4V IO Regulator capacitor for MIPI DPHY USB OTG USB HOST 1 1 Dedicated Ball Name I O Description XUOTGDRVVUBS O USB OTG charge pump enable XUHOSTPWREN O USB HOST charge pump enable XUHOSTOVERCUR I USB HOST over current flag XUOTGDP IO USB OTG Data pin DATA XUOTGREXT IO USB OTG External...

Page 2300: ...m clock POP_CLKB_A IO POP_A DRAM CLK differential system clock POP_CKE_A IO POP_A DRAM Clock Enable POP_CSB_A IO POP_A DRAM Chip Select POP_RASB_A IO POP_A DRAM Row Address Strobe POP_CASB_A IO POP_A DRAM Column Address Strobe POP_WEB_A IO POP_A DRAM Write Enable POP_BA0_A POP_BA2_A IO POP_A DRAM Bank Address POP_DQM0_A POP_DQM3_A IO POP_A DRAM Data Differential Strobe neg POP_DQS0_A POP_DQS3_A IO...

Page 2301: ...6 K16 XADCAIN_7 L15 XADCAIN_8 D16 XADCAIN_9 D14 VDD_ADC H17 P20 VSS_ADC H18 N20 DAC XDACCOMP K25 XDACIREF K22 XDACOUT K24 XDACVREF L22 VDD_DAC_A K20 VSS_DAC_A K21 VDD_DAC J22 VSS_DAC J21 MIPI DPHY XMIPIMDN0 G10 XMIPIMDN1 F11 XMIPIMDN2 G13 XMIPIMDN3 G14 XMIPIMDNCLK G12 XMIPIMDP0 F10 XMIPIMDP1 G11 XMIPIMDP2 F13 XMIPIMDP3 F14 XMIPIMDPCLK F12 XMIPISDN0 G15 XMIPISDN1 F16 XMIPISDN2 F18 XMIPISDN3 F19 XMI...

Page 2302: ... VSS_MIPI H13 H16 HDMI PHY XHDMIREXT P22 XHDMITX0N N26 XHDMITX0P N27 XHDMITX1N M26 XHDMITX1P M27 XHDMITX2N L26 XHDMITX2P L27 XHDMITXCN P26 XHDMITXCP P27 XHDMIXTI T22 XHDMIXTO R22 VDD_HDMI M22 VDD_HDMI_PLL N21 VDD_HDMI_OSC L20 VSS_HDMI M21 VSS_HDMI_PLL N22 VSS_HDMI_OSC L21 USB OTG XUOTGDM F6 XUOTGDP G6 XUOTGID D8 XUOTGREXT J6 XUOTGVBUS D9 VDD_UOTG_A F9 VDD_UOTG_D H10 VSS_UOTG_A H11 VSS_UOTG_AC G9 V...

Page 2303: ...ll No USB HOST XUHOSTDM G8 XUHOSTDP F8 XUHOSTREXT D10 VDD_UHOST_A D11 VDD_UHOST_D K12 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 APLL VDD_APLL N6 VSS_APLL P6 MPLL VDD_MPLL T6 VSS_MPLL T7 VPLL VDD_VPLL P8 VSS_VPLL P7 EPLL VDD_EPLL M7 VSS_EPLL N7 EPLL_FILTER T8 ...

Page 2304: ...DDR_11 AE26 XM0ADDR_12 AF23 XM0ADDR_13 AF22 XM0ADDR_14 AE23 XM0ADDR_15 AF26 XM0ADDR_2 V20 XM0ADDR_3 W21 XM0ADDR_4 W22 XM0ADDR_5 AD27 XM0ADDR_6 AD26 XM0ADDR_7 AF25 XM0ADDR_8 AF24 XM0ADDR_9 AE22 XM0BEN_0 AA24 XM0BEN_1 Y21 XM0CSN_0 U22 XM0CSN_1 W24 XM0CSN_2 AE24 XM0CSN_3 AA25 XM0CSN_4 Y25 XM0CSN_5 Y24 XM0DATA_0 V25 XM0DATA_1 U26 XM0DATA_10 R27 XM0DATA_11 R25 XM0DATA_12 P24 XM0DATA_13 M25 XM0DATA_14 J...

Page 2305: ...ATA_RDN AB26 XM0FALE W25 XM0FCLE Y26 XM0FREN W27 XM0FRNB_0 H26 XM0FRNB_1 AC26 XM0FRNB_2 V21 XM0FRNB_3 AC27 XM0FWEN AA27 XM0OEN G27 XM0WAITN V22 XM0WEN G26 VDD_M0 T20 U20 LCD XVHSYNC L14 XVSYS_OE G21 XVVCLK F22 XVVD_0 D20 XVVD_1 D21 XVVD_10 B25 XVVD_11 G24 XVVD_12 G22 XVVD_13 B26 XVVD_14 E26 XVVD_15 D27 XVVD_16 C25 XVVD_17 H22 XVVD_18 C26 XVVD_19 G25 XVVD_2 D22 XVVD_20 F20 ...

Page 2306: ...VD_9 F21 XVVDEN D19 XVVSYNC D18 XVVSYNC_LDI H24 VDD_LCD H19 CAMERA XCICLKENB H3 XCIDATA_0 J7 XCIDATA_1 M4 XCIDATA_2 G2 XCIDATA_3 H2 XCIDATA_4 H1 XCIDATA_5 G3 XCIDATA_6 J2 XCIDATA_7 J3 XCIFIELD F3 XCIHREF M6 XCIPCLK F1 XCIVSYNC K7 VDD_CAM H7 AUDIO XI2S0CDCLK M17 XI2S0LRCK U21 XI2S0SCLK N17 XI2S0SDI R24 XI2S0SDO_0 M24 XI2S0SDO_1 R20 XI2S0SDO_2 P18 XI2S1CDCLK T21 XI2S1LRCK R21 ...

Page 2307: ... AG19 XMSMADDR_1 AD18 XMSMADDR_10 AA20 XMSMADDR_11 AG23 XMSMADDR_12 AE18 XMSMADDR_13 AG17 XMSMADDR_2 AE20 XMSMADDR_3 AE17 XMSMADDR_4 AF21 XMSMADDR_5 AE21 XMSMADDR_6 AD20 XMSMADDR_7 AE19 XMSMADDR_8 AD19 XMSMADDR_9 AG22 XMSMADVN AF12 XMSMCSN AD14 XMSMDATA_0 AG11 XMSMDATA_1 AF14 XMSMDATA_10 AD15 XMSMDATA_11 AG13 XMSMDATA_12 AF15 XMSMDATA_13 AE16 XMSMDATA_14 AF16 XMSMDATA_15 AE15 XMSMDATA_2 AG14 XMSMD...

Page 2308: ...MSMRN AD13 XMSMWEN AE13 VDD_MODEM AA21 KEY XEINT_16 N3 XEINT_17 N2 XEINT_18 W4 XEINT_19 M3 XEINT_20 V2 XEINT_21 L3 XEINT_22 K1 XEINT_23 U3 XEINT_24 L2 XEINT_25 V4 XEINT_26 K3 XEINT_27 P4 XEINT_28 K2 XEINT_29 L4 XEINT_30 T2 XEINT_31 K4 VDD_KEY L10 System 0 XXTI AB2 XXTO AB3 XOM_0 Y4 XOM_1 Y3 XOM_2 Y2 XOM_3 AA6 XOM_4 Y1 XOM_5 AA2 XPWRRGTON AA7 XNRESET AB6 XNRSTOUT Y7 ...

Page 2309: ...VBUS F7 XUHOSTPWREN D6 XUHOSTOVERCUR H6 XDDR2SEL G7 XUSBXTI L6 XUSBXTO K6 XJTRSTN U18 XJTMS V18 XJTCK W20 XJTDI T18 XJTDO R18 XJDBGSEL AG24 VDD_SYS0 J8 M8 P21 System 1 XEINT_8 Y6 XEINT_9 V6 XEINT_10 U2 XEINT_11 AE2 XEINT_12 P2 XEINT_13 W3 XEINT_14 M2 XEINT_15 W1 VDD_SYS1 L7 External Peri 0 XMMC0CDN AG10 XMMC0CLK AF8 XMMC0CMD AD11 XMMC0DATA_0 AE11 XMMC0DATA_1 AF11 XMMC0DATA_2 AD12 ...

Page 2310: ...PICSN_0 AF4 XSPIMISO_0 AE3 XSPIMOSI_0 AE5 XURXD_0 AB14 XUTXD_0 AB11 XUCTSN_0 AE12 XURTSN_0 AB10 XURXD_1 AA14 XUTXD_1 AB13 XUCTSN_1 AB12 XURTSN_1 AB9 XI2C0SDA AB8 XI2C0SCL AD7 XPWMTOUT_0 Y16 XPWMTOUT_1 AB16 XPWMTOUT_2 AD9 XPWMTOUT_3 AA16 VDD_EXT0 Y18 External Peri 1 XMMC2CDN Y20 XMMC2CLK AA18 XMMC2CMD Y22 XMMC2DATA_0 AA19 XMMC2DATA_1 AA22 XMMC2DATA_2 AB22 XMMC2DATA_3 AB21 XI2C1SCL F2 XI2C1SDA H4 XI...

Page 2311: ...3 L12 VDD_EXT1 H8 L18 External Peri 2 XMMC3CDN Y15 XMMC3CLK AB20 XMMC3CMD Y19 XMMC3DATA_0 AB18 XMMC3DATA_1 Y17 XMMC3DATA_2 AB15 XMMC3DATA_3 AA17 XSPICLK_1 AF3 XSPICSN_1 AF5 XSPIMISO_1 AE4 XSPIMOSI_1 AG4 VDD_EXT2 AB17 RTC Clock Out XRTCCLKO AB7 VDD_CKO N10 RTC XRTCXTI AA3 XRTCXTO AA4 VDD_RTC N8 EFUSE Security XEFFSOURCE_0 U24 ...

Page 2312: ...50 Internal Power Power Domain Ball Name Ball No Internal Internal Logic VDD_INT AD6 AE6 AF6 AG6 M11 M12 M13 M14 M15 M16 T17 U17 V14 V15 V16 V17 ARM Cortex A8 VDD_ARM R1 R2 R3 R4 R6 R7 R8 R10 R11 R12 T10 T11 T12 U11 Alive VDD_ALIVE K8 L8 ...

Page 2313: ...POP_A6_A C13 POP_A7_A A15 POP_A8_A C14 POP_A9_A C15 POP_A10_A B10 POP_A11_A B13 POP_A12_A C12 POP_A13_A A13 POP_BA0_A B11 POP_BA1_A A10 POP_BA2_A A14 POP_CASB_A C11 POP_RASB_A A11 POP_WEB_A B14 POP_CKE_A D13 POP_CLK_A B12 POP_CLKB_A A12 POP_CSB_A C10 POP_DQ0_A D2 POP_DQ1_A D3 POP_DQ2_A C2 POP_DQ3_A C1 POP_DQ4_A B2 POP_DQ5_A B3 POP_DQ6_A B4 POP_DQ7_A A3 POP_DQ8_A A4 POP_DQ9_A C5 POP_DQ10_A B5 ...

Page 2314: ...POP_DQ23_A A20 POP_DQ24_A B22 POP_DQ25_A A23 POP_DQ26_A C21 POP_DQ27_A C22 POP_DQ28_A A24 POP_DQ29_A B24 POP_DQ30_A C23 POP_DQ31_A C20 POP_DQM0_A C4 POP_DQM1_A A9 POP_DQM2_A C17 POP_DQM3_A A21 POP_DQS0_A C3 POP_DQS1_A A8 POP_DQS2_A B17 POP_DQS3_A B21 VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAM B IO Power POP_INTB_B AF19 VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM Core Power VDD_ODRAM A16 AC3...

Page 2315: ...SIZE BALL MAP 5 53 Power Domain Ball Name Ball No VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 MDDR Core Power VDD_MDDR AB4 AB25 F4 H25 N4 T26 OneNAND IO Power POP_CEB_O Y27 VDD_ONAND_IO J26 T27 OneNAND Core Power VDD_ONAND AA26 F26 ...

Page 2316: ...1 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T8 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 VSS_UOTG...

Page 2317: ...S5PC110_UM 5 G TYPE SIZE BALL MAP 5 1 6 PACKAGE DIMENSION Figure 5 2 S5PC110 Package Dimension 596 FCFBGA Top View 5 55 ...

Page 2318: ...S5PC110_UM 5 G TYPE SIZE BALL MAP Figure 5 3 S5PC110 Package Dimension 596 FCFBGA Side View 5 56 ...

Page 2319: ...S5PC110_UM 6 H TYPE SIZE BALL MAP 6 H TYPE SIZE BALL MAP 6 1 PIN ASSIGNMENT 6 1 1 PIN ASSIGNMENT DIAGRAM 596 BALL FCFBGA POP Figure 6 1 S5PC110 Pin Assignment 596 FCFBGA Bottom View 6 1 ...

Page 2320: ...C16 C11 NC51 A6 NC12 A26 VSS B19 NC19 C12 NC44 A7 NC65 A27 VSS B20 NC21 C13 NC38 A8 NC61 B1 VSS B21 NC63 C14 NC40 A9 NC57 B2 NC4 B22 NC24 C15 NC41 A10 NC54 B3 NC5 B23 VSS C16 NC64 A11 NC50 B4 NC6 B24 NC29 C17 NC58 A12 NC47 B5 NC10 B25 XVVD_10 C18 NC18 A13 NC45 B6 NC13 B26 XVVD_13 C19 NC22 A14 NC55 B7 NC14 B27 VSS C20 NC31 A15 NC39 B8 VSS C1 NC3 C21 NC26 A16 VDD_MDDR0 B9 NC34 C2 NC2 C22 NC27 A17 NC...

Page 2321: ...8 XMIPISDN2 G13 XMIPIMDN2 D9 XUOTGVBUS E25 XVVD_7 F19 XMIPISDN3 G14 XMIPIMDN3 D10 XUHOSTREXT E26 XVVD_14 F20 XVVD_20 G15 XMIPISDN0 D11 VDD_UHOST_A E27 XVVD_22 F21 XVVD_9 G16 XMIPISDP1 D12 VSS_UHOST_A F1 XCIPCLK F22 XVVCLK G17 XMIPISDPCLK D13 NC48 F2 XI2C1SCL F24 VDD_MDDR0 G18 XMIPISDP2 D14 XADCAIN_9 F3 XCIFIELD F25 VSS G19 XMIPISDP3 D15 XADCAIN_1 F4 VDD_MDDR1 F26 VDD_ONAND G20 XVVD_3 D16 XADCAIN_8...

Page 2322: ...6 XUSBXTI H9 VSS_UOTG_D J3 XCIDATA_7 K11 XUTXD_2 L7 VDD_SYS1 H10 VDD_UOTG_D J4 XI2C2SCL K12 VDD_UHOST_D L8 VDD_ALIVE H11 VSS_UOTG_A J6 XUOTGREXT K13 VDD_MIPI_PLL L10 VDD_KEY H12 VSS_UHOST_D J7 XCIDATA_0 K14 XMIPIVREG_0P4V L11 XURXD_3 H13 VSS_MIPI J8 VDD_SYS0 K15 VDD_MIPI_A L12 XUTXD_3 H14 VDD_MIPI_D J20 VDD_AUD K16 XADCAIN_6 L13 VSS_UHOST_AC H15 VDD_MIPI_D J21 VSS_DAC K17 XADCAIN_5 L14 XVHSYNC H16...

Page 2323: ...5 XM0DATA_3 P25 XM0DATA_4 M2 XEINT_14 M26 XHDMITX1N N26 XHDMITX0N P26 XHDMITXCN M3 XEINT_19 M27 XHDMITX1P N27 XHDMITX0P P27 XHDMITXCP M4 XCIDATA_1 N1 VDD_MDDR1_IO P1 VSS R1 VDD_ARM M6 XCIHREF N2 XEINT_17 P2 XEINT_12 R2 VDD_ARM M7 VDD_EPLL N3 XEINT_16 P3 XEINT_7 R3 VDD_ARM M8 VDD_SYS0 N4 VDD_MDDR1 P4 XEINT_27 R4 VDD_ARM M10 XI2C2SDA N6 VDD_APLL P6 VSS_APLL R6 VDD_ARM M11 VDD_INT N7 VSS_EPLL P7 VSS_...

Page 2324: ...JTRSTN V15 VDD_INT R27 XM0DATA_10 T24 Xpcm2SOUT U20 VDD_M0 V16 VDD_INT T1 VSS T25 Xpcm2EXTCLK U21 XI2S0LRCK V17 VDD_INT T2 XEINT_30 T26 VDD_MDDR1 U22 XM0CSN_0 V18 XJTMS T3 XEINT_5 T27 VDD_ONAND_IO U24 XEFFSOURCE_0 V20 XM0ADDR_2 T4 VSS U1 VDD_MDDR1_IO U25 VSS V21 XM0FRNB_2 T6 VDD_MPLL U2 XEINT_10 U26 XM0DATA_1 V22 XM0WAITN T7 VSS_MPLL U3 XEINT_23 U27 XM0DATA_9 V24 Xpcm2SCLK T8 EPLL_FILTER U4 VSS V1...

Page 2325: ...LKO W24 XM0CSN_1 Y18 VDD_EXT0 AA13 VSS AB8 XI2C0SDA W25 XM0FALE Y19 XMMC3CMD AA14 XURXD_1 AB9 XURTSN_1 W26 Xpcm2FSYNC Y20 XMMC2CDN AA15 VSS AB10 XURTSN_0 W27 XM0FREN Y21 XM0BEN_1 AA16 XPWMTOUT_3 AB11 XUTXD_0 Y1 XOM_4 Y22 XMMC2CMD AA17 XMMC3DATA_3 AB12 XUCTSN_1 Y2 XOM_2 Y24 XM0CSN_5 AA18 XMMC2CLK AB13 XUTXD_1 Y3 XOM_1 Y25 XM0CSN_4 AA19 XMMC2DATA_0 AB14 XURXD_0 Y4 XOM_0 Y26 XM0FCLE AA20 XMSMADDR_10 ...

Page 2326: ...2 XNWRESET AD18 XMSMADDR_1 AE13 XMSMWEN AF6 VDD_INT AC3 VDD_MDDR0 AD19 XMSMADDR_8 AE14 XMSMDATA_3 AF7 VSS AC25 XM0ADDR_0 AD20 XMSMADDR_6 AE15 XMSMDATA_15 AF8 XMMC0CLK AC26 XM0FRNB_1 AD21 NC AE16 XMSMDATA_13 AF9 XMMC1DATA_2 AC27 XM0FRNB_3 AD22 NC AE17 XMSMADDR_3 AF10 XMMC0DATA_3 AD1 VSS AD25 VDD_MDDR0_IO AE18 XMSMADDR_12 AF11 XMMC0DATA_1 AD2 XEINT_4 AD26 XM0ADDR_6 AE19 XMSMADDR_7 AF12 XMSMADVN AD3 ...

Page 2327: ...DR_4 AG14 XMSMDATA_2 AF22 XM0ADDR_13 AG15 VSS AF23 XM0ADDR_12 AG16 VDD_MDDR0 AF24 XM0ADDR_8 AG17 XMSMADDR_13 AF25 XM0ADDR_7 AG18 XMSMDATA_6 AF26 XM0ADDR_15 AG19 XMSMADDR_0 AF27 VSS AG20 VDD_MDDR0_IO AG1 VSS AG21 VSS AG2 VSS AG22 XMSMADDR_9 AG3 VDD_MDDR0_IO AG23 XMSMADDR_11 AG4 XSPIMOSI_1 AG24 XJDBGSEL AG5 XSPICLK_0 AG25 VDD_MDDR0_IO AG6 VDD_INT AG26 VSS AG7 VSS AG27 VSS AG8 VDD_MDDR0_IO AG9 XMMC1C...

Page 2328: ...DD_EXT1 H8 L18 EXT1 VDD_EXT2 AB17 EXT2 VDD_CKO N10 RTC CLKO VDD_RTC N8 RTC Internal Logic VDD_INT AD6 AE6 AF6 AG6 M11 M12 M13 M14 M15 M16 T17 U17 V14 V15 V16 V17 Internal logic VDD_ARM R1 R2 R3 R4 R6 R7 R8 R10 R11 R12 T10 T11 T12 U11 Cortex A8 core VDD_ALIVE K8 L8 Alive logic Analog High Speed VDD_ADC H17 P20 ADC VDD_DAC_A K20 DAC Analog VDD_DAC J22 DAC Digital VDD_MIPI_A K15 MIPI 1 8V VDD_MIPI_D ...

Page 2329: ... MPLL VDD_VPLL P8 VPLL VDD_EPLL M7 EPLL MCP VDD_MDDR0_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 MDDR0 VDDQ VDD_MDDR0 A16 AC3 AG16 E3 F24 MDDR0 CORE VDD VDD_MDDR1_IO AA1 G1 L1 M1 N1 U1 V1 MDDR1 VDDQ VDD_MDDR1 AB4 AB25 F4 H25 N4 T26 MDDR1 CORE VDD VDD_ONAND_IO J26 T27 OneNAND VCCQ VDD_ONAND AA26 F26 OneNAND VCC ...

Page 2330: ...2 AG7 AG15 AG21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H...

Page 2331: ...UART_2_RTSn O GPI I L Signal I O Description UART_0_RXD I UART 0 receives data input UART_0_TXD O UART 0 transmits data output UART_0_CTSn I UART 0 clear to send input signal UART_0_RTSn O UART 0 request to send output signal UART_1_RXD I UART 1 receives data input UART_1_TXD O UART 1 transmits data output UART_1_CTSn I UART 1 clear to send input signal UART_1_RTSn O UART 1 request to send output ...

Page 2332: ..._1_MISO IO GPI I L XSPIMOSI_1 SPI_1_MOSI IO GPI I L Signal I O Description SPI_0_CLK IO SPI clock for channel 0 SPI_0_nSS IO SPI chip select only for slave mode for channel 0 SPI_0_MISO IO SPI master input slave output line for channel 0 SPI_0_MOSI IO SPI master output slave input line for channel 0 SPI_1_CLK IO SPI clock for channel 1 SPI_1_nSS IO SPI chip select only for slave mode for channel 1...

Page 2333: ...el 1 I2S_1_LRCK IO IIS bus channel select clock for channel 1 I2S_1_SDI I IIS bus serial data input for channel 1 I2S_1_SDO O IIS bus serial data output for channel 1 PCM_2_SCLK O PCM Serial Shift Clock for channel 2 PCM_2_EXTCLK I PCM External Clock for channel 2 PCM_2_FSYNC O PCM Sync indicating start of word for channel 2 PCM_2_SIN I PCM Serial Data Input for channel 2 PCM_2_SOUT O PCM Serial D...

Page 2334: ... AC97SDO O AC link Serial Data output to AC97 Codec I2S_2_SCLK IO IIS bus serial clock for channel 2 I2S_2_CDCLK IO IIS CODEC system clock for channel 2 I2S_2_LRCK IO IIS bus channel select clock for channel 2 I2S_2_SDI I IIS bus serial data input for channel 2 I2S_2_SDO O IIS bus serial data output for channel 2 ...

Page 2335: ...XI2C1SDA I2C1_SDA IO GPI I L XI2C1SCL I2C1_SCL IO GPI I L XI2C2SDA I2C2_SDA IO IEM_SCLK IO GPI I L XI2C2SCL I2C2_SCL IO IEM_SPWI IO GPI I L Signal I O Description TOUT_0 1 2 3 O PWM Timer Output I2C0_SDA IO IIC bus clock for channel 0 I2C0_SCL IO IIC bus data for channel 0 I2C1_SDA IO IIC bus clock for channel 1 I2C1_SCL IO IIC bus data for channel 1 I2C2_SDA IO IIC bus clock for channel 0 I2C2_SC...

Page 2336: ...TA 5 I GPI I L XCIDATA_6 CAM_A_DATA 6 I GPI I L XCIDATA_7 CAM_A_DATA 7 I GPI I L XCICLKENB CAM_A_CLKOUT O GPI I L XCIFIELD CAM_A_FIELD I GPI I L Signal I O Description CAM_A_PCLK O Pixel Clock driven by the Camera processor A CAM_A_VSYNC IO Vertical Sync driven by the Camera processor A CAM_A_HREF IO Horizontal Sync driven by the Camera processor A CAM_A_DATA 7 0 IO Pixel Data for YCbCr in 8 bit m...

Page 2337: ... SYS_VD 7 IO VEN_DATA 7 O GPI I L XVVD_8 LCD_VD 8 O SYS_VD 8 IO V656_DATA 0 O GPI I L XVVD_9 LCD_VD 9 O SYS_VD 9 IO V656_DATA 1 O GPI I L XVVD_10 LCD_VD 10 O SYS_VD 10 IO V656_DATA 2 O GPI I L XVVD_11 LCD_VD 11 O SYS_VD 11 IO V656_DATA 3 O GPI I L XVVD_12 LCD_VD 12 O SYS_VD 12 IO V656_DATA 4 O GPI I L XVVD_13 LCD_VD 13 O SYS_VD 13 IO V656_DATA 5 O GPI I L XVVD_14 LCD_VD 14 O SYS_VD 14 IO V656_DATA...

Page 2338: ...rect i80 System interface SYS_RS O Register State Select Signal for LCD Indirect i80 System interface SYS_WE O Write Enable for LCD Indirect i80 System interface SYS_VD 23 0 IO Video data input output for LCD Indirect i80 System interface SYS_OE O Output Enable for LCD Indirect i80 System interface VEN_HSYNC O Horizontal Sync Signal for 601 interface VEN_VSYNC O Vertical Sync Signal for 601 interf...

Page 2339: ..._0_DATA 4 IO GPI I L XMMC1DATA_1 SD_1_DATA 1 IO SD_0_DATA 5 IO GPI I L XMMC1DATA_2 SD_1_DATA 2 IO SD_0_DATA 6 IO GPI I L XMMC1DATA_3 SD_1_DATA 3 IO SD_0_DATA 7 IO GPI I L XMMC2CLK SD_2_CLK O GPI I L XMMC2CMD SD_2_CMD IO GPI I L XMMC2CDN SD_2_CDn I GPI I L XMMC2DATA_0 SD_2_DATA 0 IO GPI I L XMMC2DATA_1 SD_2_DATA 1 IO GPI I L XMMC2DATA_2 SD_2_DATA 2 IO GPI I L XMMC2DATA_3 SD_2_DATA 3 IO GPI I L XMMC...

Page 2340: ...nel 1 SD_1_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 1 SD_2_CLK O CLOCK SD SDIO MMC card interface channel 2 SD_2_CMD IO COMMAND RESPONSE SD SDIO MMC card interface channel 2 SD_2_CDn I CARD DETECT SD SDIO MMC card interface channel 2 SD_2_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 2 SD_3_CLK O CLOCK SD SDIO MMC card interface channel 3 SD_3_CMD IO COMMAND RESPONSE SD SD...

Page 2341: ... GPI I L XEINT_13 I HDMI_HPD I GPI I L XEINT_14 I GPI I L XEINT_15 I GPI I L XEINT_16 I KP_COL 0 IO GPI I L XEINT_17 I KP_COL 1 IO GPI I L XEINT_18 I KP_COL 2 IO GPI I L XEINT_19 I KP_COL 3 IO GPI I L XEINT_20 I KP_COL 4 IO GPI I L XEINT_21 I KP_COL 5 IO GPI I L XEINT_22 I KP_COL 6 IO GPI I L XEINT_23 I KP_COL 7 IO GPI I L XEINT_24 I KP_ROW 0 I GPI I L XEINT_25 I KP_ROW 1 I GPI I L XEINT_26 I KP_R...

Page 2342: ...10_UM 6 H TYPE SIZE BALL MAP 6 24 Signal I O Description XEINT 31 0 I External interrupts KP_COL 7 0 O KeyIF_Column_data 7 0 KP_ROW 7 0 I KeyIF_Row_data 7 0 HDMI_CEC IO HDMI CEC port HDMI_HPD I HDMI Hot plug ...

Page 2343: ...al I O Description I2S_0_SCLK IO IIS bus serial clock for channel 0 Lower Power Audio I2S_0_CDCLK IO IIS CODEC system clock for channel 0 Lower Power Audio I2S_0_LRCK IO IIS bus channel select clock for channel 0 Lower Power Audio I2S_0_SDI I IIS bus serial data input for channel 0 Lower Power Audio I2S_0_SDO 2 0 O IIS bus serial data output for channel 0 Lower Power Audio PCM_0_SCLK O PCM Serial ...

Page 2344: ...I L XMSMADDR_10 MSM_ADDR 10 I CAM_B_HREF I SROM_ADDR_16to22 2 O MHL_D3 O GPI I L XMSMADDR_11 MSM_ADDR 11 I CAM_B_FIELD I SROM_ADDR_16to22 3 O MHL_D4 O GPI I L XMSMADDR_12 MSM_ADDR 12 I CAM_B_CLKOUT O SROM_ADDR_16to22 4 O MHL_D5 O GPI I L XMSMADDR_13 MSM_ADDR 13 I KP_COL 0 I O SROM_ADDR_16to22 5 O MHL_D6 O GPI I L XMSMDATA_0 MSM_DATA 0 I O KP_COL 1 I O CF_DATA 0 I O MHL_D7 O GPI I L XMSMDATA_1 MSM_...

Page 2345: ...KP_ROW 13 I SROM_ADDR_16to22 6 O MHL_DE O GPI I L Signal I O Description MSM_ADDR 13 0 I MODEM MSM IF Address MSM_ADDR 13 should be 0 MSM_DATA 15 0 IO MODEM MSM IF Data MSM_CSn I MODEM MSM IF Chip Select MSM_WEn I MODEM MSM IF Write enable MSM_Rn I MODEM MSM IF Read enable MSM_IRQn O MODEM MSM IF Interrupt to MODEM MSM_ADVN I MODEM MSM IF Address Valid from MODEM Chip CAM_B_DATA 7 0 I Pixel Data d...

Page 2346: ... TS_CLK I TSI system clock 66MHz TS_SYNC I TSI synchronization control signal TS_VAL I TSI valid signal TS_DATA I TSI input data TS_ERROR I TSI error indicate signal MHL_D0 O MHL Data 0 MHL_D1 O MHL Data 1 MHL_D2 O MHL Data 2 MHL_D3 O MHL Data 3 MHL_D4 O MHL Data 4 MHL_D5 O MHL Data 5 MHL_D6 O MHL Data 6 MHL_D7 O MHL Data 7 MHL_D8 O MHL Data 8 MHL_D9 O MHL Data 9 MHL_D10 O MHL Data 10 MHL_D11 O MH...

Page 2347: ...110_UM 6 H TYPE SIZE BALL MAP 6 29 Signal I O Description MHL_D22 O MHL Data 22 MHL_D23 O MHL Data 23 MHL_HSYNC O MHL Hsync MHL_IDCK O MHL Interface Data Clock MHL_VSYNC O MHL Vsync MHL_DE O MHL Data Enable ...

Page 2348: ...LE O ONANDXL_ADDRVALID O Func3 O L XM0FALE NF_ALE O ONANDXL_SMCLK O Func3 O L XM0FWEN NF_FWEn O ONANDXL_RPn O Func3 O H XM0FREN NF_FREn O Func3 O H XM0FRNB_0 NF_RnB 0 I ONANDXL_INT 0 I Func3 I XM0FRNB_1 NF_RnB 1 I ONANDXL_INT 1 I Func3 I XM0FRNB_2 NF_RnB 2 I Func3 I XM0FRNB_3 NF_RnB 3 I Func3 I XM0ADDR_0 EBI_ADDR 0 O Func0 O L XM0ADDR_1 EBI_ADDR 1 O Func0 O L XM0ADDR_2 EBI_ADDR 2 O Func0 O L XM0AD...

Page 2349: ...5 EBI_DATA 15 IO Func0 O L Signal I O Description SROM_CSn 5 4 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 3 2 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 1 0 O Memory Port 0 SROM Chip select support up to 2 memory bank EBI_OEn O Memory Port 0 SROM OneNAND Output Enable EBI_WEn O Memory Port 0 SROM OneNAND Write Enable EBI_BEn 1 0 O Memory Port 0...

Page 2350: ...ect bank 1 NFCSn 2 O Memory Port 0 NAND Chip Select bank 2 NFCSn 3 O Memory Port 0 NAND Chip Select bank 3 ONANDXL_ADDRVALID O OneNANDXL Flash Address valid ONANDXL_SMCLK O OneNANDXL Flash clock ONANDXL_RPn O OneNANDXL Flash reset ONANDXL_INT 1 0 I OneNANDXL Flash Interrupt signal from OneNAND Device ...

Page 2351: ...ory port 1DRAM Data Differential Strobe neg only LPDDR2 4bit XM1CKE_0 XM1CKE_1 IO Memory port 1DRAM Clock Enable 2bit XM1SCLK IO Memory port 1DRAM Clock XM1nSCLK IO Memory port 1DRAM Inverted Clock of Xm1SCLK XM1CSn_0 XM1CSn_1 IO Memory port 1DRAM Chip Select support up to 2 memory bank 2bit XM1RASn IO Memory port 1DRAM Row Address Strobe XM1CASn IO Memory port 1DRAM Column Address Strobe XM1WEn I...

Page 2352: ...ory port 2DRAM Data Differential Strobe neg only LPDDR2 4bit XM2CKE_0 XM2CKE_1 IO Memory port 2DRAM Clock Enable 2bit XM2SCLK IO Memory port 2DRAM Clock XM2nSCLK IO Memory port 2DRAM Inverted Clock of Xm1SCLK XM2CSn_0 XM2CSn_1 IO Memory port 2DRAM Chip Select support up to 2 memory bank 2bit XM2RASn IO Memory port 2DRAM Row Address Strobe XM2CASn IO Memory port 2DRAM Column Address Strobe XM2WEn I...

Page 2353: ... logic Pull down resistor is connected XJTDI I XjTDI TAP Controller Data Input is the serial input for test instructions and data Pull up resistor is connected XJTDO O XjTDO TAP Controller Data Output is the serial output for test instructions and data XJDBGSEL I JTAG selection 0 CORTEXA8 Core JTAG 1 Peripherals JTAG RESET etc Dedicated Ball Name I O Description XOM_0 XOM_5 I Operating Mode contro...

Page 2354: ...nal capacitor connection XHDMITX0P O HDMI Phy TX0 P XHDMITX0N O HDMI Phy TX0 N XHDMITX1P O HDMI Phy TX1 P XHDMITX1N O HDMI Phy TX1 N XHDMITX2P O HDMI Phy TX2 P XHDMITX2N O HDMI Phy TX2 N XHDMITXCP O HDMI Phy TX Clock P XHDMITXCN O HDMI Phy TX Clock N XHDMIREXT I HDMI Phy Registance XHDMIXTI I HDMI crystal input XHDMIXTO O HDMI crystal output XMIPIMDP0 IO Master DATA LANE0 DP for MIPI DPHY XMIPIMDP...

Page 2355: ...K IO Slave CLK Lane DN for MIPI DPHY XMIPIVREG_0P4V IO Regulator capacitor for MIPI DPHY USB OTG USB HOST 1 1 Dedicated Ball Name I O Description XUOTGDRVVUBS O USB OTG charge pump enable XUHOSTPWREN O USB HOST charge pump enable XUHOSTOVERCUR I USB HOST over current flag XUOTGDP IO USB OTG Data pin DATA XUOTGREXT IO USB OTG External 44 2ohm 1 resistor connection XUOTGDM IO USB OTG Data pin DATA X...

Page 2356: ...S5PC110_UM 6 H TYPE SIZE BALL MAP 6 38 POP_A OneDRAM A Port Ball Name I O Description POP_CEB_O IO POP_A DRAM Chip Enable ...

Page 2357: ...6 K16 XADCAIN_7 L15 XADCAIN_8 D16 XADCAIN_9 D14 VDD_ADC H17 P20 VSS_ADC H18 N20 DAC XDACCOMP K25 XDACIREF K22 XDACOUT K24 XDACVREF L22 VDD_DAC_A K20 VSS_DAC_A K21 VDD_DAC J22 VSS_DAC J21 MIPI DPHY XMIPIMDN0 G10 XMIPIMDN1 F11 XMIPIMDN2 G13 XMIPIMDN3 G14 XMIPIMDNCLK G12 XMIPIMDP0 F10 XMIPIMDP1 G11 XMIPIMDP2 F13 XMIPIMDP3 F14 XMIPIMDPCLK F12 XMIPISDN0 G15 XMIPISDN1 F16 XMIPISDN2 F18 XMIPISDN3 F19 XMI...

Page 2358: ... VSS_MIPI H13 H16 HDMI PHY XHDMIREXT P22 XHDMITX0N N26 XHDMITX0P N27 XHDMITX1N M26 XHDMITX1P M27 XHDMITX2N L26 XHDMITX2P L27 XHDMITXCN P26 XHDMITXCP P27 XHDMIXTI T22 XHDMIXTO R22 VDD_HDMI M22 VDD_HDMI_PLL N21 VDD_HDMI_OSC L20 VSS_HDMI M21 VSS_HDMI_PLL N22 VSS_HDMI_OSC L21 USB OTG XUOTGDM F6 XUOTGDP G6 XUOTGID D8 XUOTGREXT J6 XUOTGVBUS D9 VDD_UOTG_A F9 VDD_UOTG_D H10 VSS_UOTG_A H11 VSS_UOTG_AC G9 V...

Page 2359: ...ll No USB HOST XUHOSTDM G8 XUHOSTDP F8 XUHOSTREXT D10 VDD_UHOST_A D11 VDD_UHOST_D K12 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 APLL VDD_APLL N6 VSS_APLL P6 MPLL VDD_MPLL T6 VSS_MPLL T7 VPLL VDD_VPLL P8 VSS_VPLL P7 EPLL VDD_EPLL M7 VSS_EPLL N7 EPLL_FILTER T8 ...

Page 2360: ...DDR_11 AE26 XM0ADDR_12 AF23 XM0ADDR_13 AF22 XM0ADDR_14 AE23 XM0ADDR_15 AF26 XM0ADDR_2 V20 XM0ADDR_3 W21 XM0ADDR_4 W22 XM0ADDR_5 AD27 XM0ADDR_6 AD26 XM0ADDR_7 AF25 XM0ADDR_8 AF24 XM0ADDR_9 AE22 XM0BEN_0 AA24 XM0BEN_1 Y21 XM0CSN_0 U22 XM0CSN_1 W24 XM0CSN_2 AE24 XM0CSN_3 AA25 XM0CSN_4 Y25 XM0CSN_5 Y24 XM0DATA_0 V25 XM0DATA_1 U26 XM0DATA_10 R27 XM0DATA_11 R25 XM0DATA_12 P24 XM0DATA_13 M25 XM0DATA_14 J...

Page 2361: ...ATA_RDN AB26 XM0FALE W25 XM0FCLE Y26 XM0FREN W27 XM0FRNB_0 H26 XM0FRNB_1 AC26 XM0FRNB_2 V21 XM0FRNB_3 AC27 XM0FWEN AA27 XM0OEN G27 XM0WAITN V22 XM0WEN G26 VDD_M0 T20 U20 LCD XVHSYNC L14 XVSYS_OE G21 XVVCLK F22 XVVD_0 D20 XVVD_1 D21 XVVD_10 B25 XVVD_11 G24 XVVD_12 G22 XVVD_13 B26 XVVD_14 E26 XVVD_15 D27 XVVD_16 C25 XVVD_17 H22 XVVD_18 C26 XVVD_19 G25 XVVD_2 D22 XVVD_20 F20 ...

Page 2362: ...VD_9 F21 XVVDEN D19 XVVSYNC D18 XVVSYNC_LDI H24 VDD_LCD H19 CAMERA XCICLKENB H3 XCIDATA_0 J7 XCIDATA_1 M4 XCIDATA_2 G2 XCIDATA_3 H2 XCIDATA_4 H1 XCIDATA_5 G3 XCIDATA_6 J2 XCIDATA_7 J3 XCIFIELD F3 XCIHREF M6 XCIPCLK F1 XCIVSYNC K7 VDD_CAM H7 AUDIO XI2S0CDCLK M17 XI2S0LRCK U21 XI2S0SCLK N17 XI2S0SDI R24 XI2S0SDO_0 M24 XI2S0SDO_1 R20 XI2S0SDO_2 P18 XI2S1CDCLK T21 XI2S1LRCK R21 ...

Page 2363: ... AG19 XMSMADDR_1 AD18 XMSMADDR_10 AA20 XMSMADDR_11 AG23 XMSMADDR_12 AE18 XMSMADDR_13 AG17 XMSMADDR_2 AE20 XMSMADDR_3 AE17 XMSMADDR_4 AF21 XMSMADDR_5 AE21 XMSMADDR_6 AD20 XMSMADDR_7 AE19 XMSMADDR_8 AD19 XMSMADDR_9 AG22 XMSMADVN AF12 XMSMCSN AD14 XMSMDATA_0 AG11 XMSMDATA_1 AF14 XMSMDATA_10 AD15 XMSMDATA_11 AG13 XMSMDATA_12 AF15 XMSMDATA_13 AE16 XMSMDATA_14 AF16 XMSMDATA_15 AE15 XMSMDATA_2 AG14 XMSMD...

Page 2364: ...MSMRN AD13 XMSMWEN AE13 VDD_MODEM AA21 KEY XEINT_16 N3 XEINT_17 N2 XEINT_18 W4 XEINT_19 M3 XEINT_20 V2 XEINT_21 L3 XEINT_22 K1 XEINT_23 U3 XEINT_24 L2 XEINT_25 V4 XEINT_26 K3 XEINT_27 P4 XEINT_28 K2 XEINT_29 L4 XEINT_30 T2 XEINT_31 K4 VDD_KEY L10 System 0 XXTI AB2 XXTO AB3 XOM_0 Y4 XOM_1 Y3 XOM_2 Y2 XOM_3 AA6 XOM_4 Y1 XOM_5 AA2 XPWRRGTON AA7 XNRESET AB6 XNRSTOUT Y7 ...

Page 2365: ...VBUS F7 XUHOSTPWREN D6 XUHOSTOVERCUR H6 XDDR2SEL G7 XUSBXTI L6 XUSBXTO K6 XJTRSTN U18 XJTMS V18 XJTCK W20 XJTDI T18 XJTDO R18 XJDBGSEL AG24 VDD_SYS0 J8 M8 P21 System 1 XEINT_8 Y6 XEINT_9 V6 XEINT_10 U2 XEINT_11 AE2 XEINT_12 P2 XEINT_13 W3 XEINT_14 M2 XEINT_15 W1 VDD_SYS1 L7 External Peri 0 XMMC0CDN AG10 XMMC0CLK AF8 XMMC0CMD AD11 XMMC0DATA_0 AE11 XMMC0DATA_1 AF11 XMMC0DATA_2 AD12 ...

Page 2366: ...PICSN_0 AF4 XSPIMISO_0 AE3 XSPIMOSI_0 AE5 XURXD_0 AB14 XUTXD_0 AB11 XUCTSN_0 AE12 XURTSN_0 AB10 XURXD_1 AA14 XUTXD_1 AB13 XUCTSN_1 AB12 XURTSN_1 AB9 XI2C0SDA AB8 XI2C0SCL AD7 XPWMTOUT_0 Y16 XPWMTOUT_1 AB16 XPWMTOUT_2 AD9 XPWMTOUT_3 AA16 VDD_EXT0 Y18 External Peri 1 XMMC2CDN Y20 XMMC2CLK AA18 XMMC2CMD Y22 XMMC2DATA_0 AA19 XMMC2DATA_1 AA22 XMMC2DATA_2 AB22 XMMC2DATA_3 AB21 XI2C1SCL F2 XI2C1SDA H4 XI...

Page 2367: ...3 L12 VDD_EXT1 H8 L18 External Peri 2 XMMC3CDN Y15 XMMC3CLK AB20 XMMC3CMD Y19 XMMC3DATA_0 AB18 XMMC3DATA_1 Y17 XMMC3DATA_2 AB15 XMMC3DATA_3 AA17 XSPICLK_1 AF3 XSPICSN_1 AF5 XSPIMISO_1 AE4 XSPIMOSI_1 AG4 VDD_EXT2 AB17 RTC Clock Out XRTCCLKO AB7 VDD_CKO N10 RTC XRTCXTI AA3 XRTCXTO AA4 VDD_RTC N8 EFUSE Security XEFFSOURCE_0 U24 ...

Page 2368: ...R8 R10 R11 R12 T10 T11 T12 U11 Alive VDD_ALIVE K8 L8 MCP Power Power Domain Ball Name Ball No MCP OneDRAM B IO Power VDD_MDDR0_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM Core Power VDD_MDDR0 A16 AC3 AG16 E3 F24 MDDR IO Power POP_TQ E1 POP_NC AC1 VDD_MDDR1_IO AA1 G1 L1 M1 N1 U1 V1 MDDR Core Power VDD_MDDR1 AB4 AB25 F4 H25 N4 T26 OneNAND IO Power POP_CEB_O Y27 VDD_ONAND_IO J26 T27 OneNAND Core P...

Page 2369: ...21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 VSS_UOTG_A...

Page 2370: ...S5PC110_UM 6 H TYPE SIZE BALL MAP 6 1 6 PACKAGE DIMENSION Figure 6 2 S5PC110 Package Dimension 596 FCFBGA Top View 6 52 ...

Page 2371: ...S5PC110_UM 6 H TYPE SIZE BALL MAP Figure 6 3 S5PC110 Package Dimension 596 FCFBGA Side View 6 53 ...

Page 2372: ...S5PC110_UM 7 I TYPE SIZE BALL MAP 7 I TYPE SIZE BALL MAP 7 1 PIN ASSIGNMENT 7 1 1 PIN ASSIGNMENT DIAGRAM 596 BALL FCFBGA POP Figure 7 1 S5PC110 Pin Assignment 596 FCFBGA Bottom View 7 1 ...

Page 2373: ...0 POP_DQ21_A C13 POP_A6_A A8 POP_DQS1_A B1 VSS B21 POP_DQS3_A C14 POP_A8_A A9 POP_DQM1_A B2 POP_DQ4_A B22 POP_DQ24_A C15 POP_A9_A A10 POP_BA1_A B3 POP_DQ5_A B23 VSS C16 POP_INTB_A A11 POP_RASB_A B4 POP_DQ6_A B24 POP_DQ29_A C17 POP_DQM2_A A12 POP_CLKB_A B5 POP_DQ10_A B25 XVVD_10 C18 POP_DQ18_A A13 POP_A13_A B6 POP_DQ13_A B26 XVVD_13 C19 POP_DQ22_A A14 POP_BA2_A B7 POP_DQ14_A B27 VSS C20 POP_DQ31_A ...

Page 2374: ... VDD_ODRAM F18 XMIPISDN2 G13 XMIPIMDN2 D9 XUOTGVBUS E25 XVVD_7 F19 XMIPISDN3 G14 XMIPIMDN3 D10 XUHOSTREXT E26 XVVD_14 F20 XVVD_20 G15 XMIPISDN0 D11 VDD_UHOST_A E27 XVVD_22 F21 XVVD_9 G16 XMIPISDP1 D12 VSS_UHOST_A F1 XCIPCLK F22 XVVCLK G17 XMIPISDPCLK D13 POP_CKE_A F2 XI2C1SCL F24 VDD_ODRAM G18 XMIPISDP2 D14 XADCAIN_0 F3 XCIFIELD F25 VSS G19 XMIPISDP3 D15 XADCAIN_8 F4 VDD_MDDR F26 VDD_ONAND G20 XVV...

Page 2375: ... XUSBXTI H9 VSS_UOTG_D J3 XCIDATA_7 K11 XUTXD_2 L7 VDD_SYS1 H10 VDD_UOTG_D J4 XI2C2SCL K12 VDD_UHOST_D L8 VDD_ALIVE H11 VSS_UOTG_A J6 XUOTGREXT K13 VDD_MIPI_PLL L10 VDD_KEY H12 VSS_UHOST_D J7 XCIDATA_0 K14 XMIPIVREG_0P4V L11 XURXD_3 H13 VSS_MIPI J8 VDD_SYS0 K15 VDD_MIPI_A L12 XUTXD_3 H14 VDD_MIPI_D J20 VDD_AUD K16 XADCAIN_3 L13 VSS_UHOST_AC H15 VDD_MIPI_D J21 VSS_DAC K17 XADCAIN_4 L14 XVHSYNC H16 ...

Page 2376: ...25 XM0DATA_3 P25 XM0DATA_4 M2 XEINT_14 M26 XHDMITX1N N26 XHDMITX0N P26 XHDMITXCN M3 XEINT_19 M27 XHDMITX1P N27 XHDMITX0P P27 XHDMITXCP M4 XCIDATA_1 N1 VDD_MDDR_IO P1 VSS R1 VDD_ARM M6 XCIHREF N2 XEINT_17 P2 XEINT_12 R2 VDD_ARM M7 VDD_EPLL N3 XEINT_16 P3 XEINT_7 R3 VDD_ARM M8 VDD_SYS0 N4 VDD_MDDR P4 XEINT_27 R4 VDD_ARM M10 XI2C2SDA N6 VDD_APLL P6 VSS_APLL R6 VDD_ARM M11 VDD_INT N7 VSS_EPLL P7 VSS_V...

Page 2377: ... XJTRSTN V15 VDD_INT R27 XM0DATA_10 T24 XPCM0SOUT U20 VDD_M0 V16 VDD_INT T1 VSS T25 XPCM0EXTCLK U21 XI2S0LRCK V17 VDD_INT T2 XEINT_30 T26 VDD_MDDR U22 XM0CSN_0 V18 XJTMS T3 XEINT_5 T27 VDD_ONAND_IO U24 XEFFSOURCE_0 V20 XM0ADDR_2 T4 VSS U1 VDD_MDDR_IO U25 VSS V21 XM0FRNB_2 T6 VDD_MPLL U2 XEINT_10 U26 XM0DATA_1 V22 XM0WAITN T7 VSS_MPLL U3 XEINT_23 U27 XM0DATA_9 V24 XPCM0SCLK T8 EPLL_FILTER U4 VSS V1...

Page 2378: ...LKO W24 XM0CSN_1 Y18 VDD_EXT0 AA13 VSS AB8 XI2C0SDA W25 XM0FALE Y19 XMMC3CMD AA14 XURXD_1 AB9 XURTSN_1 W26 XPCM0FSYNC Y20 XMMC2CDN AA15 VSS AB10 XURTSN_0 W27 XM0FREN Y21 XM0BEN_1 AA16 XPWMTOUT_3 AB11 XUTXD_0 Y1 XOM_4 Y22 XMMC2CMD AA17 XMMC3DATA_3 AB12 XUCTSN_1 Y2 XOM_2 Y24 XM0CSN_5 AA18 XMMC2CLK AB13 XUTXD_1 Y3 XOM_1 Y25 XM0CSN_4 AA19 XMMC2DATA_0 AB14 XURXD_0 Y4 XOM_0 Y26 XM0FCLE AA20 XMSMADDR_10 ...

Page 2379: ...NWRESET AD18 XMSMADDR_1 AE13 XMSMWEN AF6 VDD_INT AC3 VDD_ODRAM AD19 XMSMADDR_8 AE14 XMSMDATA_3 AF7 VSS AC25 XM0ADDR_0 AD20 XMSMADDR_6 AE15 XMSMDATA_15 AF8 XMMC0CLK AC26 XM0FRNB_1 AD21 NC AE16 XMSMDATA_13 AF9 XMMC1DATA_2 AC27 XM0FRNB_3 AD22 NC AE17 XMSMADDR_3 AF10 XMMC0DATA_3 AD1 VSS AD25 VDD_ODRAMB_IO AE18 XMSMADDR_12 AF11 XMMC0DATA_1 AD2 XEINT_4 AD26 XM0ADDR_6 AE19 XMSMADDR_7 AF12 XMSMADVN AD3 XE...

Page 2380: ...ADDR_4 AG14 XMSMDATA_2 AF22 XM0ADDR_13 AG15 VSS AF23 XM0ADDR_12 AG16 VDD_ODRAM AF24 XM0ADDR_8 AG17 XMSMADDR_13 AF25 XM0ADDR_7 AG18 XMSMDATA_6 AF26 XM0ADDR_15 AG19 XMSMADDR_0 AF27 VSS AG20 VDD_ODRAMB_IO AG1 VSS AG21 VSS AG2 VSS AG22 XMSMADDR_9 AG3 VDD_ODRAMB_IO AG23 XMSMADDR_11 AG4 XSPIMOSI_1 AG24 XJDBGSEL AG5 XSPICLK_0 AG25 VDD_ODRAMB_IO AG6 VDD_INT AG26 VSS AG7 VSS AG27 VSS AG8 VDD_ODRAMB_IO AG9 ...

Page 2381: ...DD_EXT1 H8 L18 EXT1 VDD_EXT2 AB17 EXT2 VDD_CKO N10 RTC CLKO VDD_RTC N8 RTC Internal Logic VDD_INT AD6 AE6 AF6 AG6 M11 M12 M13 M14 M15 M16 T17 U17 V14 V15 V16 V17 Internal logic VDD_ARM R1 R2 R3 R4 R6 R7 R8 R10 R11 R12 T10 T11 T12 U11 Cortex A8 core VDD_ALIVE K8 L8 Alive logic Analog High Speed VDD_ADC H17 P20 ADC VDD_DAC_A K20 DAC Analog VDD_DAC J22 DAC Digital VDD_MIPI_A K15 MIPI 1 8V VDD_MIPI_D ...

Page 2382: ... VDD_EPLL M7 EPLL MCP VDD_ODRAMA_IO A7 A22 C27 D1 OneDRAMA VDDQ VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAMB VDDQ VDD_ODRAM A16 AC3 AG16 E3 F24 OneDRAM CORE VDD VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 MDDR VDDQ VDD_MDDR AB4 AB25 F4 H25 N4 T26 MDDR CORE VDD VDD_ONAND_IO J26 T27 OneNAND VCCQ VDD_ONAND AA26 F26 OneNAND VCC ...

Page 2383: ...2 AG7 AG15 AG21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H...

Page 2384: ...UART_2_RTSn O GPI I L Signal I O Description UART_0_RXD I UART 0 receives data input UART_0_TXD O UART 0 transmits data output UART_0_CTSn I UART 0 clear to send input signal UART_0_RTSn O UART 0 request to send output signal UART_1_RXD I UART 1 receives data input UART_1_TXD O UART 1 transmits data output UART_1_CTSn I UART 1 clear to send input signal UART_1_RTSn O UART 1 request to send output ...

Page 2385: ..._1_MISO IO GPI I L XSPIMOSI_1 SPI_1_MOSI IO GPI I L Signal I O Description SPI_0_CLK IO SPI clock for channel 0 SPI_0_nSS IO SPI chip select only for slave mode for channel 0 SPI_0_MISO IO SPI master input slave output line for channel 0 SPI_0_MOSI IO SPI master output slave input line for channel 0 SPI_1_CLK IO SPI clock for channel 1 SPI_1_nSS IO SPI chip select only for slave mode for channel 1...

Page 2386: ...el 1 I2S_1_LRCK IO IIS bus channel select clock for channel 1 I2S_1_SDI I IIS bus serial data input for channel 1 I2S_1_SDO O IIS bus serial data output for channel 1 PCM_2_SCLK O PCM Serial Shift Clock for channel 2 PCM_2_EXTCLK I PCM External Clock for channel 2 PCM_2_FSYNC O PCM Sync indicating start of word for channel 2 PCM_2_SIN I PCM Serial Data Input for channel 2 PCM_2_SOUT O PCM Serial D...

Page 2387: ... AC97SDO O AC link Serial Data output to AC97 Codec I2S_2_SCLK IO IIS bus serial clock for channel 2 I2S_2_CDCLK IO IIS CODEC system clock for channel 2 I2S_2_LRCK IO IIS bus channel select clock for channel 2 I2S_2_SDI I IIS bus serial data input for channel 2 I2S_2_SDO O IIS bus serial data output for channel 2 ...

Page 2388: ...XI2C1SDA I2C1_SDA IO GPI I L XI2C1SCL I2C1_SCL IO GPI I L XI2C2SDA I2C2_SDA IO IEM_SCLK IO GPI I L XI2C2SCL I2C2_SCL IO IEM_SPWI IO GPI I L Signal I O Description TOUT_0 1 2 3 O PWM Timer Output I2C0_SDA IO IIC bus clock for channel 0 I2C0_SCL IO IIC bus data for channel 0 I2C1_SDA IO IIC bus clock for channel 1 I2C1_SCL IO IIC bus data for channel 1 I2C2_SDA IO IIC bus clock for channel 0 I2C2_SC...

Page 2389: ...A 5 I GPI I L XCIDATA_6 CAM_A_DATA 6 I GPI I L XCIDATA_7 CAM_A_DATA 7 I GPI I L XCICLKENB CAM_A_CLKOUT O GPI I L XCIFIELD CAM_A_FIELD I GPI I L Signal I O Description CAM_A_PCLK O Pixel Clock driven by the Camera processor A CAM_A_VSYNC IO Vertical Sync driven by the Camera processor A CAM_A_HREF IO Horizontal Sync driven by the Camera processor A CAM_A_DATA 7 0 IO Pixel Data for YCbCr in 8 bit mo...

Page 2390: ... SYS_VD 7 IO VEN_DATA 7 O GPI I L XVVD_8 LCD_VD 8 O SYS_VD 8 IO V656_DATA 0 O GPI I L XVVD_9 LCD_VD 9 O SYS_VD 9 IO V656_DATA 1 O GPI I L XVVD_10 LCD_VD 10 O SYS_VD 10 IO V656_DATA 2 O GPI I L XVVD_11 LCD_VD 11 O SYS_VD 11 IO V656_DATA 3 O GPI I L XVVD_12 LCD_VD 12 O SYS_VD 12 IO V656_DATA 4 O GPI I L XVVD_13 LCD_VD 13 O SYS_VD 13 IO V656_DATA 5 O GPI I L XVVD_14 LCD_VD 14 O SYS_VD 14 IO V656_DATA...

Page 2391: ...rect i80 System interface SYS_RS O Register State Select Signal for LCD Indirect i80 System interface SYS_WE O Write Enable for LCD Indirect i80 System interface SYS_VD 23 0 IO Video data input output for LCD Indirect i80 System interface SYS_OE O Output Enable for LCD Indirect i80 System interface VEN_HSYNC O Horizontal Sync Signal for 601 interface VEN_VSYNC O Vertical Sync Signal for 601 interf...

Page 2392: ..._0_DATA 4 IO GPI I L XMMC1DATA_1 SD_1_DATA 1 IO SD_0_DATA 5 IO GPI I L XMMC1DATA_2 SD_1_DATA 2 IO SD_0_DATA 6 IO GPI I L XMMC1DATA_3 SD_1_DATA 3 IO SD_0_DATA 7 IO GPI I L XMMC2CLK SD_2_CLK O GPI I L XMMC2CMD SD_2_CMD IO GPI I L XMMC2CDN SD_2_CDn I GPI I L XMMC2DATA_0 SD_2_DATA 0 IO GPI I L XMMC2DATA_1 SD_2_DATA 1 IO GPI I L XMMC2DATA_2 SD_2_DATA 2 IO GPI I L XMMC2DATA_3 SD_2_DATA 3 IO GPI I L XMMC...

Page 2393: ...nel 1 SD_1_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 1 SD_2_CLK O CLOCK SD SDIO MMC card interface channel 2 SD_2_CMD IO COMMAND RESPONSE SD SDIO MMC card interface channel 2 SD_2_CDn I CARD DETECT SD SDIO MMC card interface channel 2 SD_2_DATA 3 0 IO DATA 3 0 SD SDIO MMC card interface channel 2 SD_3_CLK O CLOCK SD SDIO MMC card interface channel 3 SD_3_CMD IO COMMAND RESPONSE SD SD...

Page 2394: ... GPI I L XEINT_13 I HDMI_HPD I GPI I L XEINT_14 I GPI I L XEINT_15 I GPI I L XEINT_16 I KP_COL 0 IO GPI I L XEINT_17 I KP_COL 1 IO GPI I L XEINT_18 I KP_COL 2 IO GPI I L XEINT_19 I KP_COL 3 IO GPI I L XEINT_20 I KP_COL 4 IO GPI I L XEINT_21 I KP_COL 5 IO GPI I L XEINT_22 I KP_COL 6 IO GPI I L XEINT_23 I KP_COL 7 IO GPI I L XEINT_24 I KP_ROW 0 I GPI I L XEINT_25 I KP_ROW 1 I GPI I L XEINT_26 I KP_R...

Page 2395: ...10_UM 7 I TYPE SIZE BALL MAP 7 24 Signal I O Description XEINT 31 0 I External interrupts KP_COL 7 0 O KeyIF_Column_data 7 0 KP_ROW 7 0 I KeyIF_Row_data 7 0 HDMI_CEC IO HDMI CEC port HDMI_HPD I HDMI Hot plug ...

Page 2396: ...al I O Description I2S_0_SCLK IO IIS bus serial clock for channel 0 Lower Power Audio I2S_0_CDCLK IO IIS CODEC system clock for channel 0 Lower Power Audio I2S_0_LRCK IO IIS bus channel select clock for channel 0 Lower Power Audio I2S_0_SDI I IIS bus serial data input for channel 0 Lower Power Audio I2S_0_SDO 2 0 O IIS bus serial data output for channel 0 Lower Power Audio PCM_0_SCLK O PCM Serial ...

Page 2397: ...I L XMSMADDR_10 MSM_ADDR 10 I CAM_B_HREF I SROM_ADDR_16to22 2 O MHL_D3 O GPI I L XMSMADDR_11 MSM_ADDR 11 I CAM_B_FIELD I SROM_ADDR_16to22 3 O MHL_D4 O GPI I L XMSMADDR_12 MSM_ADDR 12 I CAM_B_CLKOUT O SROM_ADDR_16to22 4 O MHL_D5 O GPI I L XMSMADDR_13 MSM_ADDR 13 I KP_COL 0 I O SROM_ADDR_16to22 5 O MHL_D6 O GPI I L XMSMDATA_0 MSM_DATA 0 I O KP_COL 1 I O CF_DATA 0 I O MHL_D7 O GPI I L XMSMDATA_1 MSM_...

Page 2398: ...KP_ROW 13 I SROM_ADDR_16to22 6 O MHL_DE O GPI I L Signal I O Description MSM_ADDR 13 0 I MODEM MSM IF Address MSM_ADDR 13 should be 0 MSM_DATA 15 0 IO MODEM MSM IF Data MSM_CSn I MODEM MSM IF Chip Select MSM_WEn I MODEM MSM IF Write enable MSM_Rn I MODEM MSM IF Read enable MSM_IRQn O MODEM MSM IF Interrupt to MODEM MSM_ADVN I MODEM MSM IF Address Valid from MODEM Chip CAM_B_DATA 7 0 I Pixel Data d...

Page 2399: ... TS_CLK I TSI system clock 66MHz TS_SYNC I TSI synchronization control signal TS_VAL I TSI valid signal TS_DATA I TSI input data TS_ERROR I TSI error indicate signal MHL_D0 O MHL Data 0 MHL_D1 O MHL Data 1 MHL_D2 O MHL Data 2 MHL_D3 O MHL Data 3 MHL_D4 O MHL Data 4 MHL_D5 O MHL Data 5 MHL_D6 O MHL Data 6 MHL_D7 O MHL Data 7 MHL_D8 O MHL Data 8 MHL_D9 O MHL Data 9 MHL_D10 O MHL Data 10 MHL_D11 O MH...

Page 2400: ...110_UM 7 I TYPE SIZE BALL MAP 7 29 Signal I O Description MHL_D22 O MHL Data 22 MHL_D23 O MHL Data 23 MHL_HSYNC O MHL Hsync MHL_IDCK O MHL Interface Data Clock MHL_VSYNC O MHL Vsync MHL_DE O MHL Data Enable ...

Page 2401: ...LE O ONANDXL_ADDRVALID O Func3 O L XM0FALE NF_ALE O ONANDXL_SMCLK O Func3 O L XM0FWEN NF_FWEn O ONANDXL_RPn O Func3 O H XM0FREN NF_FREn O Func3 O H XM0FRNB_0 NF_RnB 0 I ONANDXL_INT 0 I Func3 I XM0FRNB_1 NF_RnB 1 I ONANDXL_INT 1 I Func3 I XM0FRNB_2 NF_RnB 2 I Func3 I XM0FRNB_3 NF_RnB 3 I Func3 I XM0ADDR_0 EBI_ADDR 0 O Func0 O L XM0ADDR_1 EBI_ADDR 1 O Func0 O L XM0ADDR_2 EBI_ADDR 2 O Func0 O L XM0AD...

Page 2402: ...5 EBI_DATA 15 IO Func0 O L Signal I O Description SROM_CSn 5 4 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 3 2 O Memory Port 0 SROM Chip select support up to 2 memory bank SROM_CSn 1 0 O Memory Port 0 SROM Chip select support up to 2 memory bank EBI_OEn O Memory Port 0 SROM OneNAND Output Enable EBI_WEn O Memory Port 0 SROM OneNAND Write Enable EBI_BEn 1 0 O Memory Port 0...

Page 2403: ...ect bank 1 NFCSn 2 O Memory Port 0 NAND Chip Select bank 2 NFCSn 3 O Memory Port 0 NAND Chip Select bank 3 ONANDXL_ADDRVALID O OneNANDXL Flash Address valid ONANDXL_SMCLK O OneNANDXL Flash clock ONANDXL_RPn O OneNANDXL Flash reset ONANDXL_INT 1 0 I OneNANDXL Flash Interrupt signal from OneNAND Device ...

Page 2404: ...3 IO Memory port 1DRAM Data Differential Strobe neg 4bit XM1DQM_0 XM1DQM_3 IO Memory port 1DRAM Data Mask 4bit XM1CKE_0 XM1CKE_1 IO Memory port 1DRAM Clock Enable 2bit XM1SCLK IO Memory port 1DRAM Clock XM1nSCLK IO Memory port 1DRAM Inverted Clock of Xm1SCLK XM1CSn_0 XM1CSn_1 IO Memory port 1DRAM Chip Select support up to 2 memory bank 2bit XM1RASn IO Memory port 1DRAM Row Address Strobe XM1CASn I...

Page 2405: ...3 IO Memory port 2DRAM Data Differential Strobe neg 4bit XM2DQM_0 XM2DQM_3 IO Memory port 2DRAM Data Mask 4bit XM2CKE_0 XM2CKE_1 IO Memory port 2DRAM Clock Enable 2bit XM2SCLK IO Memory port 2DRAM Clock XM2nSCLK IO Memory port 2DRAM Inverted Clock of Xm1SCLK XM2CSn_0 XM2CSn_1 IO Memory port 2DRAM Chip Select support up to 2 memory bank 2bit XM2RASn IO Memory port 2DRAM Row Address Strobe XM2CASn I...

Page 2406: ...gic Pull down resistor is connected XJTDI I XjTDI TAP Controller Data Input is the serial input for test instructions and data Pull up resistor is connected XJTDO O XjTDO TAP Controller Data Output is the serial output for test instructions and data XJDBGSEL I JTAG selection 0 CORTEXA8 Core JTAG 1 Peripherals JTAG RESET etc Dedicated Ball Name I O Description XOM_0 XOM_5 I Operating Mode control s...

Page 2407: ...nal capacitor connection XHDMITX0P O HDMI Phy TX0 P XHDMITX0N O HDMI Phy TX0 N XHDMITX1P O HDMI Phy TX1 P XHDMITX1N O HDMI Phy TX1 N XHDMITX2P O HDMI Phy TX2 P XHDMITX2N O HDMI Phy TX2 N XHDMITXCP O HDMI Phy TX Clock P XHDMITXCN O HDMI Phy TX Clock N XHDMIREXT I HDMI Phy Registance XHDMIXTI I HDMI crystal input XHDMIXTO O HDMI crystal output XMIPIMDP0 IO Master DATA LANE0 DP for MIPI DPHY XMIPIMDP...

Page 2408: ...K IO Slave CLK Lane DN for MIPI DPHY XMIPIVREG_0P4V IO Regulator capacitor for MIPI DPHY USB OTG USB HOST 1 1 Dedicated Ball Name I O Description XUOTGDRVVUBS O USB OTG charge pump enable XUHOSTPWREN O USB HOST charge pump enable XUHOSTOVERCUR I USB HOST over current flag XUOTGDP IO USB OTG Data pin DATA XUOTGREXT IO USB OTG External 44 2ohm 1 resistor connection XUOTGDM IO USB OTG Data pin DATA X...

Page 2409: ..._CKE_A IO POP_A DRAM Clock Enable POP_CSB_A IO POP_A DRAM Chip Select POP_RASB_A IO POP_A DRAM Row Address Strobe POP_CASB_A IO POP_A DRAM Column Address Strobe POP_WEB_A IO POP_A DRAM Write Enable POP_BA0_A POP_BA2_A IO POP_A DRAM Bank Address POP_DQM0_A POP_DQM3_A IO POP_A DRAM Data Differential Strobe neg POP_DQS0_A POP_DQS3_A IO POP_A DRAM Data Differential Strobe neg POP_INTB_A IO OneDRAM Por...

Page 2410: ...6 K16 XADCAIN_7 L15 XADCAIN_8 D16 XADCAIN_9 D14 VDD_ADC H17 P20 VSS_ADC H18 N20 DAC XDACCOMP K25 XDACIREF K22 XDACOUT K24 XDACVREF L22 VDD_DAC_A K20 VSS_DAC_A K21 VDD_DAC J22 VSS_DAC J21 MIPI DPHY XMIPIMDN0 G10 XMIPIMDN1 F11 XMIPIMDN2 G13 XMIPIMDN3 G14 XMIPIMDNCLK G12 XMIPIMDP0 F10 XMIPIMDP1 G11 XMIPIMDP2 F13 XMIPIMDP3 F14 XMIPIMDPCLK F12 XMIPISDN0 G15 XMIPISDN1 F16 XMIPISDN2 F18 XMIPISDN3 F19 XMI...

Page 2411: ... VSS_MIPI H13 H16 HDMI PHY XHDMIREXT P22 XHDMITX0N N26 XHDMITX0P N27 XHDMITX1N M26 XHDMITX1P M27 XHDMITX2N L26 XHDMITX2P L27 XHDMITXCN P26 XHDMITXCP P27 XHDMIXTI T22 XHDMIXTO R22 VDD_HDMI M22 VDD_HDMI_PLL N21 VDD_HDMI_OSC L20 VSS_HDMI M21 VSS_HDMI_PLL N22 VSS_HDMI_OSC L21 USB OTG XUOTGDM F6 XUOTGDP G6 XUOTGID D8 XUOTGREXT J6 XUOTGVBUS D9 VDD_UOTG_A F9 VDD_UOTG_D H10 VSS_UOTG_A H11 VSS_UOTG_AC G9 V...

Page 2412: ...ll No USB HOST XUHOSTDM G8 XUHOSTDP F8 XUHOSTREXT D10 VDD_UHOST_A D11 VDD_UHOST_D K12 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 APLL VDD_APLL N6 VSS_APLL P6 MPLL VDD_MPLL T6 VSS_MPLL T7 VPLL VDD_VPLL P8 VSS_VPLL P7 EPLL VDD_EPLL M7 VSS_EPLL N7 EPLL_FILTER T8 ...

Page 2413: ...DDR_11 AE26 XM0ADDR_12 AF23 XM0ADDR_13 AF22 XM0ADDR_14 AE23 XM0ADDR_15 AF26 XM0ADDR_2 V20 XM0ADDR_3 W21 XM0ADDR_4 W22 XM0ADDR_5 AD27 XM0ADDR_6 AD26 XM0ADDR_7 AF25 XM0ADDR_8 AF24 XM0ADDR_9 AE22 XM0BEN_0 AA24 XM0BEN_1 Y21 XM0CSN_0 U22 XM0CSN_1 W24 XM0CSN_2 AE24 XM0CSN_3 AA25 XM0CSN_4 Y25 XM0CSN_5 Y24 XM0DATA_0 V25 XM0DATA_1 U26 XM0DATA_10 R27 XM0DATA_11 R25 XM0DATA_12 P24 XM0DATA_13 M25 XM0DATA_14 J...

Page 2414: ...ATA_RDN AB26 XM0FALE W25 XM0FCLE Y26 XM0FREN W27 XM0FRNB_0 H26 XM0FRNB_1 AC26 XM0FRNB_2 V21 XM0FRNB_3 AC27 XM0FWEN AA27 XM0OEN G27 XM0WAITN V22 XM0WEN G26 VDD_M0 T20 U20 LCD XVHSYNC L14 XVSYS_OE G21 XVVCLK F22 XVVD_0 D20 XVVD_1 D21 XVVD_10 B25 XVVD_11 G24 XVVD_12 G22 XVVD_13 B26 XVVD_14 E26 XVVD_15 D27 XVVD_16 C25 XVVD_17 H22 XVVD_18 C26 XVVD_19 G25 XVVD_2 D22 XVVD_20 F20 ...

Page 2415: ...VD_9 F21 XVVDEN D19 XVVSYNC D18 XVVSYNC_LDI H24 VDD_LCD H19 CAMERA XCICLKENB H3 XCIDATA_0 J7 XCIDATA_1 M4 XCIDATA_2 G2 XCIDATA_3 H2 XCIDATA_4 H1 XCIDATA_5 G3 XCIDATA_6 J2 XCIDATA_7 J3 XCIFIELD F3 XCIHREF M6 XCIPCLK F1 XCIVSYNC K7 VDD_CAM H7 AUDIO XI2S0CDCLK M17 XI2S0LRCK U21 XI2S0SCLK N17 XI2S0SDI R24 XI2S0SDO_0 M24 XI2S0SDO_1 R20 XI2S0SDO_2 P18 XI2S1CDCLK T21 XI2S1LRCK R21 ...

Page 2416: ... AG19 XMSMADDR_1 AD18 XMSMADDR_10 AA20 XMSMADDR_11 AG23 XMSMADDR_12 AE18 XMSMADDR_13 AG17 XMSMADDR_2 AE20 XMSMADDR_3 AE17 XMSMADDR_4 AF21 XMSMADDR_5 AE21 XMSMADDR_6 AD20 XMSMADDR_7 AE19 XMSMADDR_8 AD19 XMSMADDR_9 AG22 XMSMADVN AF12 XMSMCSN AD14 XMSMDATA_0 AG11 XMSMDATA_1 AF14 XMSMDATA_10 AD15 XMSMDATA_11 AG13 XMSMDATA_12 AF15 XMSMDATA_13 AE16 XMSMDATA_14 AF16 XMSMDATA_15 AE15 XMSMDATA_2 AG14 XMSMD...

Page 2417: ...MSMRN AD13 XMSMWEN AE13 VDD_MODEM AA21 KEY XEINT_16 N3 XEINT_17 N2 XEINT_18 W4 XEINT_19 M3 XEINT_20 V2 XEINT_21 L3 XEINT_22 K1 XEINT_23 U3 XEINT_24 L2 XEINT_25 V4 XEINT_26 K3 XEINT_27 P4 XEINT_28 K2 XEINT_29 L4 XEINT_30 T2 XEINT_31 K4 VDD_KEY L10 System 0 XXTI AB2 XXTO AB3 XOM_0 Y4 XOM_1 Y3 XOM_2 Y2 XOM_3 AA6 XOM_4 Y1 XOM_5 AA2 XPWRRGTON AA7 XNRESET AB6 XNRSTOUT Y7 ...

Page 2418: ...VBUS F7 XUHOSTPWREN D6 XUHOSTOVERCUR H6 XDDR2SEL G7 XUSBXTI L6 XUSBXTO K6 XJTRSTN U18 XJTMS V18 XJTCK W20 XJTDI T18 XJTDO R18 XJDBGSEL AG24 VDD_SYS0 J8 M8 P21 System 1 XEINT_8 Y6 XEINT_9 V6 XEINT_10 U2 XEINT_11 AE2 XEINT_12 P2 XEINT_13 W3 XEINT_14 M2 XEINT_15 W1 VDD_SYS1 L7 External Peri 0 XMMC0CDN AG10 XMMC0CLK AF8 XMMC0CMD AD11 XMMC0DATA_0 AE11 XMMC0DATA_1 AF11 XMMC0DATA_2 AD12 ...

Page 2419: ...PICSN_0 AF4 XSPIMISO_0 AE3 XSPIMOSI_0 AE5 XURXD_0 AB14 XUTXD_0 AB11 XUCTSN_0 AE12 XURTSN_0 AB10 XURXD_1 AA14 XUTXD_1 AB13 XUCTSN_1 AB12 XURTSN_1 AB9 XI2C0SDA AB8 XI2C0SCL AD7 XPWMTOUT_0 Y16 XPWMTOUT_1 AB16 XPWMTOUT_2 AD9 XPWMTOUT_3 AA16 VDD_EXT0 Y18 External Peri 1 XMMC2CDN Y20 XMMC2CLK AA18 XMMC2CMD Y22 XMMC2DATA_0 AA19 XMMC2DATA_1 AA22 XMMC2DATA_2 AB22 XMMC2DATA_3 AB21 XI2C1SCL F2 XI2C1SDA H4 XI...

Page 2420: ...3 L12 VDD_EXT1 H8 L18 External Peri 2 XMMC3CDN Y15 XMMC3CLK AB20 XMMC3CMD Y19 XMMC3DATA_0 AB18 XMMC3DATA_1 Y17 XMMC3DATA_2 AB15 XMMC3DATA_3 AA17 XSPICLK_1 AF3 XSPICSN_1 AF5 XSPIMISO_1 AE4 XSPIMOSI_1 AG4 VDD_EXT2 AB17 RTC Clock Out XRTCCLKO AB7 VDD_CKO N10 RTC XRTCXTI AA3 XRTCXTO AA4 VDD_RTC N8 EFUSE Security XEFFSOURCE_0 U24 ...

Page 2421: ... R10 R11 R12 T10 T11 T12 U11 Alive VDD_ALIVE K8 L8 MCP Power Power Domain Ball Name Ball No MCP OneDRAM A IO Power POP_INTB_A C16 POP_A0_A C9 POP_A1_A C8 POP_A2_A B9 POP_A3_A C7 POP_A4_A B15 POP_A5_A A17 POP_A6_A C13 POP_A7_A A15 POP_A8_A C14 POP_A9_A C15 POP_A10_A B10 POP_A11_A B13 POP_A12_A C12 POP_A13_A A13 POP_BA0_A B11 POP_BA1_A A10 POP_BA2_A A14 POP_CASB_A C11 POP_RASB_A A11 POP_WEB_A B14 PO...

Page 2422: ..._A A3 POP_DQ8_A A4 POP_DQ9_A C5 POP_DQ10_A B5 POP_DQ11_A A5 POP_DQ12_A A6 POP_DQ13_A B6 POP_DQ14_A B7 POP_DQ15_A C6 POP_DQ16_A B18 POP_DQ17_A A18 POP_DQ18_A C18 POP_DQ19_A B19 POP_DQ20_A A19 POP_DQ21_A B20 POP_DQ22_A C19 POP_DQ23_A A20 POP_DQ24_A B22 POP_DQ25_A A23 POP_DQ26_A C21 POP_DQ27_A C22 POP_DQ28_A A24 POP_DQ29_A B24 POP_DQ30_A C23 POP_DQ31_A C20 POP_DQM0_A C4 POP_DQM1_A A9 POP_DQM2_A C17 ...

Page 2423: ...RAMA_IO A7 A22 C27 D1 OneDRAM B IO Power POP_INTB_B AF19 VDD_ODRAMB_IO AB1 AD25 AE1 AF20 AG3 AG8 AG20 AG25 OneDRAM Core Power VDD_ODRAM A16 AC3 AG16 E3 F24 MDDR IO Power POP_TQ E1 VDD_MDDR_IO AA1 G1 L1 M1 N1 U1 V1 MDDR Core Power VDD_MDDR AB4 AB25 F4 H25 N4 T26 OneNAND IO Power POP_CEB_O Y27 VDD_ONAND_IO J26 T27 OneNAND Core Power VDD_ONAND AA26 F26 ...

Page 2424: ...21 AG26 AG27 B1 B8 B16 B23 B27 E2 F25 F27 G4 K27 M20 N11 N12 N16 P1 P10 P11 P12 P16 P17 R16 R17 T1 T4 T13 T14 T15 T16 U4 U7 U10 U12 U13 U14 U15 U16 U25 V7 V10 V11 V12 V13 W7 Y9 Analog IO VSS_APLL P6 VSS_EPLL N7 VSS_MPLL T7 VSS_VPLL P7 VSS_ADC H18 N20 VSS_DAC J21 VSS_DAC_A K21 VSS_HDMI M21 VSS_HDMI_OSC L21 VSS_HDMI_PLL N22 VSS_MIPI H13 H16 VSS_UHOST_A D12 VSS_UHOST_AC L13 VSS_UHOST_D H12 VSS_UOTG_A...

Page 2425: ...S5PC110_UM 7 I TYPE SIZE BALL MAP 7 1 6 PACKAGE DIMENSION Figure 7 2 S5PC110 Package Dimension 596 FCFBGA Top View 7 54 ...

Page 2426: ...S5PC110_UM 7 I TYPE SIZE BALL MAP Figure 7 3 S5PC110 Package Dimension 596 FCFBGA Side View 7 55 ...

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