S5PC110_UM
7 SD/MMC CONTROLLER
7-58
7.10.8 CLOCK CONTROL REGISTER
7.10.8.1 Command Register
•
CLKCON0, R/W, Address = 0xEB00_002C
•
CLKCON1, R/W, Address = 0xEB10_002C
•
CLKCON2, R/W, Address = 0xEB20_002C
•
CLKCON3, R/W, Address = 0xEB30_002C
At the initialization of the Host Controller, the Host Driver sets the SDCLK Frequency Select according to the
Capabilities register.
CLKCON
Bit
Description
Initial State
SELFREQ
[15:8]
SDCLK Frequency Select
This register is used to select the frequency of SDCLK pin. The
frequency is not programmed directly; rather this register holds
the divisor of the Base Clock Frequency For SD Clock in the
Capabilities register. Only the following settings are allowed.
80h
base clock divided by 256
40h
base clock divided by 128
20h
base clock divided by 64
10h
base clock divided by 32
08h
base clock divided by 16
04h
base clock divided by 8
02h
base clock divided by 4
01h
base clock divided by 2
00h
base clock (10MHz-63MHz)
Setting 00h specifies the highest frequency of the SD Clock.
Setting multiple bits, the most significant bit is used as the
divisor. But multiple bits must not be set. The two default divider
values are calculated by the frequency that is defined by the
Base Clock Frequency For SD Clock in the Capabilities register.
(1) 25MHz divider value,
(2) 400kHz divider value
According to the SD Physical Specification Version 1.01 and the
SDIO Card Specification Version 1.0, maximum SD Clock
frequency is 25MHz, and never exceeds this limit.
The frequency of SDCLK is set by the following formula:
Clock Frequency = (Base Clock)/ divisor
Therefore, select the smallest possible divisor which results in a
clock frequency that is less than or equal to the target frequency.
For example, if the Base Clock Frequency For SD Clock in the
Capabilities register has the value 33MHz, and the target
frequency is 25MHz, then selecting the divisor value of 01h
yields 16.5MHz, which is the nearest frequency less than or
equal to the target. Similarly, to approach a clock value of
0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...