Samsung S5PC110, Manual

Page: 1068 / 2426

S5PC110_UM 7 SD/MMC CONTROLLER
7-88
7.10.24 CONTROL REGISTER 2
7.10.24.1 Control Register 2
•
CONTROL2_0, R/W, Address = 0xEB00_0080
•
CONTROL2_1, R/W, Address = 0xEB10_0080
•
CONTROL2_2, R/W, Address = 0xEB20_0080
•
CONTROL2_3, R/W, Address = 0xEB30_0080
This register contains the SD Command Argument.
CONTROL2 Bit Description Initial State
ENSTAASYNCCLR [31] Write Status Clear Async Mode Enable
This bit makes async-clear enable about Normal and Error
interrupt status bit. During the initialization procedure
command operation, this bit should be enabled.
0 = Disable
1 = Enable
0
ENCMDCNFMSK [30] Command Conflict Mask Enable
This bit can mask enable the Command Conflict Status (bit
[1:0] of the "ERROR INTERRUPT STATUS REGISTER")
0 = Mask Disable
1 = Mask Enable
Note: If the OUTEDGEINV field in the Host Control Register
is set (High Speed data transfer), this field should be enabled
to prevent from command conflict status alarm. 0
Reserved [29] Reserved (must be 1’b0) 0
SELCARDOUT [28] Card Removed Condition Selection
0 = Card Removed condition is "Not Card Insert" State
(When the transition from "Card Inserted" state to
"Debouncing" state in
Figure 7-17
)
1 = Card Removed state is "Card Out" State (If the transition
from "Debouncing" state to "No Card" state in
Figure 7-17
)
0
FLTCLKSEL [27:24] Filter Clock (iFLTCLK) Selection
Filter Clock period = 2^(Flt 5) x iSDCLK period
0000 = 25 x iSDCLK
0001 = 26 x iSDCLK
…
1111 = 220 x iSDCLK
0
LVLDAT [23:16] DAT line level
Bit[23]=DAT[7], BIT[22]=DAT[6], BIT[21]=DAT[5],
BIT[20]=DAT[4],
Bit[19]=DAT[3], BIT[18]=DAT[2], BIT[17]=DAT[1],
BIT[16]=DAT[0]
(Read Only)
Line state
ENFBCLKTX [15] Feedback Clock Enable for Tx Data/Command Clock
0 = Disable
1 = Enable 0