Samsung S5PC110, Manual

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S5PC110_UM 5 USB2.0 HS OTG
5-85
5.8.7.16 Device Endpoint-n Interrupt Register (DIEPINTn/DOEPINTn, R/W, Address = 0xEC0n*20h,
0xEC0n*20h)
Endpoint_number: 0
≤
n
≤
15
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The application
must read this register if the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of the Core Interrupt register
is set. Before the application reads this register, it must first read the Device All Endpoints Interrupt (DAINT)
register to get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear
the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
DIEPINTn/
DOEPINTn
Bit Description R/W Initial State
EPEna [31:15] Reserved - 17'h0
NYETIntrpt [14] NYET interrupt (NYETIntrpt) The core generates this
interrupt when a NYET response is transmitted for a non
isochronous OUT endpoint. R_SS
_WC
1'b0
NAKIntrpt [13] NAK interrupt (NAKIntrpt) The core generates this interrupt
when a NAK is transmitted or received by the device. In
case of isochronous IN endpoints the interrupt gets
generated when a zero length packet is transmitted due to
un-availability of data in the TXFifo. R_SS
_WC
1'b0
BbleErrIntrpt [12] BbleErr (Babble Error) interrupt (BbleErrIntrpt) The core
generates this interrupt when babble is received for the
endpoint. R_SS
_WC
1'b0
Packet Dropped
Status [11] PktDrpSts (Packet Dropped Status) This bit indicates to the
application that an ISOC OUT packet has been dropped.
This bit does not have an associated mask bit and does not
generate an interrupt. Dependency: This bit is valid in non
Scatter/Gather DMA mode when periodic transfer interrupt
feature is selected. R_SS
_WC
1'b0
Reserved [10] - - -
BNAIntr [9] Buffer Not Available Interrupt
This bit is valid only when Scatter/Gather DMA mode is
enabled. The core generates this interrupt when the
descriptor accessed is not ready for the Core to process,
such as Host busy or DMA done R_SS
_WC
TxfifoUndrn Fifo Underrun
Applies to IN endpoints Only This bit is valid only when
thresholding is enabled.
The core generates this interrupt when it detects a transmit
FIFO underrun condition for this endpoint.
OutPktErr
[8]
OUT Packet Error
Applies to OUT endpoints Only This interrupt is valid only
when thresholding is enabled.
This interrupt is asserted when the core detects an overflow
or a CRC error for non-Isochronous OUT packet.
R_SS
_WC
1’b0