S5PC110_UM
1 DRAM CONTROLLER
1-33
1.4.1.7 PHY Control0 Register (PhyControl0, R/W, Address = 0xF000_0018, 0xF140_0018)
PHYCONTROL0
Bit
Description
R/W
Initial
State
ctrl_force
[31:24] DLL Force Delay
This field is used instead of ctrl_lock_value[9:2] from the PHY
DLL when ctrl_dll_on is LOW. (i.e. If the DLL is off, this field is
used to generate 270' clock and shift DQS by 90'.)
R/W
0x0
ctrl_inc [23:16] DLL
Delay
Increment
Increase the amount of start point
This value should be 0x10
R/W
0x0
ctrl_start_point
[15:8]
DLL Lock Start Point
Initial DLL lock start point. This is the number of delay cells and
is the start point where "DLL" start tracing to lock. Calculates
Initial delay time by multiplying the unit delay of delay cell and
this value.
This value should be 0x10
R/W
0x0
dqs_delay
[7:4]
Delay Cycles for DQS Cleaning
This register is to enable PHY to clean incoming DQS signals
delayed by external circumstances. If DQS is coming with
read latency plus n mclk cycles, this registers must be set to n
mclk cycles.
R/W
0x0
ctrl_dfdqs [3]
Differential
DQS
If enabled, PHY generates differential DQS out signals for write
command and receives differential DQS input signals for read
command. This function is used in case of DDR2/LPDDR2.
R/W
0x0
ctrl_half
[2]
DLL Low Speed
HIGH active signal to activate the low speed mode for DLL. If
this bit is set, DLL runs at low speed (80MHz ~ 100MHz)
R/W
0x0
ctrl_dll_on [1]
DLL
On
HIGH active start signal to activate the DLL. This signal should
be kept HIGH for normal operation. If this signal becomes
LOW, DLL is turned off and ctrl_clock and ctrl_flock become
HIGH. This bit should be set before ctrl_start is set to turn on
the DLL
R/W
0x0
ctrl_start [0]
DLL
Start
HIGH active start signal to initiate the DLL run and lock. This
signal should be kept HIGH during normal operation. If this
signal becomes LOW, DLL stops running. To re-run DLL, make
this signal HIGH again. In the case of re-running, DLL loses
previous lock information. Before ctrl_start is set, make sure
that ctrl_dll_on is HIGH.
R/W
0x0
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...