Samsung S5PC110, Manual

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S5PC110_UM 6 SPDIF TRANSMITTER
6-12
SPDCON Bit Description Initial State
10 = 3 byte swap
o_data={in_data[7:0], in_data[15:8], in_data[23:16]}
11 = 2 byte swap
o_data={0x00,in_data[7:0], in_data[15:8]}
*in_data: BUS
→ in port of SPDIF
o_data: in port of SPDIF → Logic
user_data_attach [12] 0 = User data is stored in USERBIT register.
User data of subframe is out from USERBIT1,2,3
(96-bit)
1 = User data is stored in 23rd bit of audio data.
User data is out in PCM data's 23th bit.
0
User Data Interrupt Status [11] Read Operation
0 = No interrupt pending.
1 = Interrupt pending when 96-bit of user data is out.
Write Operation
0 = No effect.
1 = Clear this flag.
0
User Data Interrupt Enable [10] 0 = Interrupt masked
1 = Interrupt enable
0
Buffer Empty Interrupt
Status
[9] Read Operation
0 = No interrupt pending.
1 = Interrupt pending.
Write Operation
0 = No effect.
1 = Clear this flag.
0
Buffer Empty Interrupt Enable [8] 0 = Interrupt masked
1 = Interrupt enable
0
Stream End Interrupt
Status
[7] Read Operation
0 = No interrupt pending.
1 = Interrupt pending when the number of output
audio data reaches repetition count in SPDCNT
register.
Write Operation
0 = No effect.
1 = Clear this flag.
0
Stream End Interrupt Enable [6] 0 = Interrupt masked
1 = Interrupt enable
0
software reset [5] 0 = Normal operation
1 = Software reset
Software reset is 1-cycle pulse (auto clear)
Enable I_MCLK before software reset assertion
because SPDIF uses synchronous reset
0
Main Audio Clock
Frequency
[4:3] 00 = 256fs
01 = 384fs
0