Samsung S5PC110, Manual

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S5PC110_UM 4 POWER MANAGEMENT
4-4
4.3 SYSTEM POWER MODE
4.3.1 OVERVIEW
According to the power saving schemes and features explained in
Section 4.3
, S5PC110 provides six power
modes, namely, NORMAL, IDLE, DEEP-IDLE, STOP, DEEP-STOP, and SLEEP.
Power modes are summarized in
Table 4-3
.
In NORMAL mode, use module-based clock gating, block-based power gating, and frequency scaling to reduce
power consumption. To reduce dynamic power consumption, clock gating disables clock input to specific module
according to the operating scenario. Clock gating can be done in module-by-module basis.
To reduce static power consumption of a block or power domain (a group of modules), power gating disconnects a
leakage current path. Power gating can be done in block-by-block basis.
Frequency scaling lowers the operating frequency to reduce dynamic power consumption.
In IDLE mode, the CPU clock is disabled internally by entering Standby mode of Cortex-A8. CPU performs WFI
instruction to enter Standby mode. In this mode, Cortex-A8 core is not running, therefore dynamic power of CPU
is reduced. The remaining parts of the chip keep their states in NORMAL mode, that is, clock-gated modules are
still clock-gated and power-gated blocks are still power-gated.
In DEEP-IDLE mode, Cortex-A8 core is power-gated rather than clock-gated. In DEEP-IDLE mode, the leakage
power of CPU core is minimized. There are three options in DEEP-IDLE mode. The first option is that the
remaining parts of the chip keep their operations in NORMAL mode. The second option is that the remaining parts
of the chip keep their states in NORMAL mode. The third option is that for low-power MP3 playback, that is, TOP
and SUB blocks are also power-gated, but only Audio block is still power on. These three options can be selected
by setting TOP_LOGIC field of IDLE_CFG register in SYSCON, that is, TOP domain can either be power-on or
power-gated by setting TOP_LOGIC field of IDLE_CFG register before entry into IDLE mode.
•
TOP_LOGIC = 2’b01: TOP block and sub-blocks keep their states in NORMAL mode. Audio block is running
the operation.
•
TOP_LOGIC = 2’b10: TOP block, sub-blocks, and Audio block is running the operation.
‘DEEP’ means that Cortex-A8 Core is power-gated.
In STOP mode, the clock to modules (except RTC module), PLLs, and unnecessary oscillators are selectively
disabled in order to minimize dynamic power consumption. In this mode, Cortex-A8 Core enters into Standby
mode.
In DEEP-STOP mode, Cortex-A8 Core is power-gated rather than clock-gated as in STOP mode, and the
remaining parts of the chip are power-gated (except TOP, RTC, and ALIVE modules). However, TOP domain can
either be power-on or power-gated. To do so, set TOP_LOGIC field of STOP_CFG register before entry into
DEEP-STOP mode. Cortex-A8 L2 cache can be powered “ON” for memory retention or power-gated to save
power.
•
TOP_LOGIC = 2’b01, TOP block is power-gated.
•
TOP_LOGIC = 2’b10, TOP block is power “ON”.