S5PC110_UM
1 DMA CONTROLLER
1-25
1.3 INSTRUCTION
Table 1-5 Instruction Syntax Summary
Mnemonic
Instruction
Thread usage:
M = DMA manager
C = DMA channel
Description
DMAADDH
Add Halfword
-
C
See DMAADDH on page 4-5 of “PL330 TRM”.
DMAEND End M
C
See
DMAEND
on page 4-5 of “PL330 TRM”.
DMAFLUSHP
Flush and notify
Peripheral
-
C
See DMAFLUSHP on page 4-6 of “PL330
TRM”.
DMAGO
Go
M
-
See DMAGO on page 4-6 of “PL330 TRM”.
DMALD Load -
C
See
DMALD[S|B] on page 4-8 of “PL330
TRM”.
DMALDP Load
Peripheral -
C See
DMALDP<S|B> on page 4-9 of “PL330
TRM”.
DMALP
Loop
-
C
See DMALP on page 4-10 of “PL330 TRM”.
DMALPEND
Loop End
-
C
See DMALPEND[S|B] on page 4-11 of “PL330
TRM”.
DMALPFE
Loop Forever
-
C
See DMALPFE on page 4-13 of “PL330 TRM”.
DMAKILL Kill M
C
See
DMAKILL
on page 4-13 of “PL330 TRM”.
DMAMOV
Move
-
C
See DMAMOV on page 4-14 of “PL330 TRM”.
DMANOP
No operation
M
C
See DMANOP on page 4-16 of “PL330 TRM”.
DMARMB
Read Memory Barrier
-
C
See DMARMB on page 4-16 of “PL330 TRM”.
DMASEV
Send Event
M
C
See DMASEV on page 4-17 of “PL330 TRM”.
DMAST
Store
-
C
See DMAST[S|B] on page 4-17 of “PL330
TRM”.
DMASTP
Store and notify
Peripheral
-
C
See DMASTP<S|B> on page 4-19 of “PL330
TRM”.
DMASTZ
Store Zero
-
C
See DMASTZ on page 4-20 of “PL330 TRM”.
DMAWFE
Wait For Event
M
C
See DMAWFE on page 4-20 of “PL330 TRM”.
DMAWFP
Wait For Peripheral
-
C
See DMAWFP<S|B|P> on page 4-21 of
“PL330 TRM”.
DMAWMB
Write Memory Barrier
-
C
See DMAWMB on page 4-22 of “PL330 TRM”.
Each PL330 has a manager thread and eight channel threads. A manager thread controls the overall operation of
DMAC, including initiating and killing channel. The channel thread operates the DMA.
Summary of Contents for S5PC110
Page 4: ...Section 1 OVERVIEW ...
Page 28: ...Section 2 SYSTEM ...
Page 374: ...S5PC110_UM 4 POWER MANAGEMENT 4 14 4 Let DRAMs exit from self refresh mode ...
Page 473: ...S5PC110_UM 6 BOOTING SEQUENCE 6 10 Figure 6 3 Secure Booting Diagram ...
Page 474: ...Section 3 BUS ...
Page 491: ...S5PC110_UM 2 CORESIGHT Figure 2 4 Structure of the Coresight DAP Components 2 8 ...
Page 506: ...Section 4 INTERRUPT ...
Page 537: ...Section 5 MEMORY ...
Page 540: ......
Page 703: ...Section 6 DMA ...
Page 705: ...List of Figures Figure Title Page Number Number Figure 1 1 Two DMA Tops 1 1 ...
Page 737: ...Section 7 TIMER ...
Page 795: ...Section 8 CONNECTIVITY STORAGE ...
Page 883: ...S5PC110_UM 5 USB2 0 HS OTG 5 7 5 6 3 OTG FIFO ADDRESS MAPPING Figure 5 3 OTG FIFO Mapping ...
Page 1100: ...Section 9 MULTIMEDIA ...
Page 1116: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 5 Figure 1 2 Block Diagram of the Data Flow ...
Page 1125: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 14 1 3 3 2 7 16BPP Display 1555 P1 P2 P3 P4 P5 LCD Panel ...
Page 1145: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 34 Figure 1 10 Blending Decision Diagram ...
Page 1149: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 38 Figure 1 14 Hue Control Block Diagram ...
Page 1184: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 73 ...
Page 1226: ...S5PC110_UM 1 0BDISPLAY CONTROLLER 1 115 ...
Page 1328: ...S5PC110_UM 2 1BCAMERA INTERFACE 2 81 ...
Page 1369: ...S5PC110_UM 4 3BMIPI CSIS 4 2 4 2 BLOCK DIAGRAM Figure 4 1 MIPI CSI System Block Diagram ...
Page 1381: ...S5PC110_UM 4 3BMIPI CSIS 4 14 ...
Page 1431: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 39 ...
Page 1471: ...S5PC110_UM 6 5BMULTI FORMAT CODEC 6 79 Figure 6 7 VC1 Parameters ...
Page 1626: ...S5PC110_UM 10 9BHIGH DEFINITION MULTIMEDIA INTERFACE 10 17 Figure 10 10 Channel Status Block ...
Page 1775: ...S5PC110_UM 13 12BG2D 13 6 FIMG 2D FIMG 2D FIMG 2D Figure 13 3 Rotation and Flip Example ...
Page 1798: ...Section 10 AUDIO ETC ...
Page 1803: ...S5PC110_UM 1 AUDIO SUBSYSTEM 1 2 Figure 8 7 Keypad I F Block Diagram 8 8 ...
Page 1951: ...Section 11 SECURITY ...
Page 1954: ...List of Tables Table Title Page Number Number Table 1 1 Security Features of S5PC110 1 2 ...
Page 1964: ...S5PC110_UM 2 ADVANCED CRYPTO ENGINE Figure 2 9 DES Byte Swapping Scheme 2 9 ...
Page 2005: ...Section 12 ETC ...
Page 2039: ...Section 13 SIZE BALL MAP ...